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bsps
arm
stm32h7
include
stm32h7xx_hal_pwr.h
Go to the documentation of this file.
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H7xx_HAL_PWR_H
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#define STM32H7xx_HAL_PWR_H
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#ifdef __cplusplus
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extern
"C"
{
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#endif
/* __cplusplus */
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/* Includes ------------------------------------------------------------------*/
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#include "
stm32h7xx_hal_def.h
"
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/* Exported types ------------------------------------------------------------*/
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typedef
struct
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{
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uint32_t
PVDLevel
;
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uint32_t
Mode
;
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}
PWR_PVDTypeDef
;
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/* Exported constants --------------------------------------------------------*/
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#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
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#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
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#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
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#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
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#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
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#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
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#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
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#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7
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#define PWR_PVD_MODE_NORMAL (0x00000000U)
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#define PWR_PVD_MODE_IT_RISING (0x00010001U)
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#define PWR_PVD_MODE_IT_FALLING (0x00010002U)
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#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)
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#define PWR_PVD_MODE_EVENT_RISING (0x00020001U)
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#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U)
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#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)
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#define PWR_MAINREGULATOR_ON (0U)
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#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
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#define PWR_SLEEPENTRY_WFI (0x01U)
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#define PWR_SLEEPENTRY_WFE (0x02U)
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#define PWR_STOPENTRY_WFI (0x01U)
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#define PWR_STOPENTRY_WFE (0x02U)
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#if defined(PWR_SRDCR_VOS)
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#define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
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#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1)
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#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0)
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#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U)
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#else
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#define PWR_REGULATOR_VOLTAGE_SCALE0 (0U)
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#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
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#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
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#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
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#endif
/* PWR_SRDCR_VOS */
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/* PWR CPU flag */
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#define PWR_FLAG_STOP (0x01U)
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#if defined (PWR_CPUCR_SBF_D2)
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#define PWR_FLAG_SB_D1 (0x02U)
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#define PWR_FLAG_SB_D2 (0x03U)
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#endif
/* defined (PWR_CPUCR_SBF_D2) */
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#define PWR_FLAG_SB (0x04U)
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#if defined (DUAL_CORE)
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#define PWR_FLAG_CPU_HOLD (0x05U)
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#define PWR_FLAG_CPU2_HOLD (0x06U)
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#define PWR_FLAG2_STOP (0x07U)
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#define PWR_FLAG2_SB_D1 (0x08U)
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#define PWR_FLAG2_SB_D2 (0x09U)
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#define PWR_FLAG2_SB (0x0AU)
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#endif
/* defined (DUAL_CORE) */
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#define PWR_FLAG_PVDO (0x0BU)
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#define PWR_FLAG_AVDO (0x0CU)
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#define PWR_FLAG_ACTVOSRDY (0x0DU)
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#define PWR_FLAG_ACTVOS (0x0EU)
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#define PWR_FLAG_BRR (0x0FU)
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#define PWR_FLAG_VOSRDY (0x10U)
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#if defined (SMPS)
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#define PWR_FLAG_SMPSEXTRDY (0x11U)
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#else
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#define PWR_FLAG_SCUEN (0x11U)
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#endif
/* defined (SMPS) */
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#if defined (PWR_CSR1_MMCVDO)
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#define PWR_FLAG_MMCVDO (0x12U)
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#endif
/* defined (PWR_CSR1_MMCVDO) */
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#define PWR_FLAG_USB33RDY (0x13U)
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#define PWR_FLAG_TEMPH (0x14U)
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#define PWR_FLAG_TEMPL (0x15U)
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#define PWR_FLAG_VBATH (0x16U)
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#define PWR_FLAG_VBATL (0x17U)
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/* PWR Wake up flag */
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#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
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#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
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#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
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#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
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#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
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#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
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#define PWR_EWUP_MASK (0x0FFF3F3FU)
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/* Exported macro ------------------------------------------------------------*/
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#if defined (PWR_SRDCR_VOS)
/* STM32H7Axxx and STM32H7Bxxx lines */
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#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
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do { \
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__IO uint32_t tmpreg = 0x00; \
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/* Configure the Voltage Scaling */
\
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MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \
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/* Delay after setting the voltage scaling */
\
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tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \
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UNUSED(tmpreg); \
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} while(0)
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#else
/* 3 power domains devices */
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#if defined(SYSCFG_PWRCR_ODEN)
/* STM32H74xxx and STM32H75xxx lines */
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#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
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do { \
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__IO uint32_t tmpreg = 0x00; \
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/* Check the voltage scaling to be configured */
\
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if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
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{ \
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/* Configure the Voltage Scaling 1 */
\
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MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
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/* Delay after setting the voltage scaling */
\
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tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
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/* Enable the PWR overdrive */
\
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SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
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/* Delay after setting the syscfg boost setting */
\
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tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
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} \
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else \
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{ \
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/* Disable the PWR overdrive */
\
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CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
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/* Delay after setting the syscfg boost setting */
\
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tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
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/* Configure the Voltage Scaling x */
\
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MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
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/* Delay after setting the voltage scaling */
\
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tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
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} \
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UNUSED(tmpreg); \
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} while(0)
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#else
/* STM32H72xxx and STM32H73xxx lines */
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#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
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do { \
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__IO uint32_t tmpreg = 0x00; \
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/* Configure the Voltage Scaling */
\
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MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
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/* Delay after setting the voltage scaling */
\
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tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
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UNUSED(tmpreg); \
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} while(0)
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#endif
/* defined(SYSCFG_PWRCR_ODEN) */
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#endif
/* defined (PWR_SRDCR_VOS) */
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#if defined (DUAL_CORE)
/* Dual core lines */
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#define __HAL_PWR_GET_FLAG(__FLAG__) \
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(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
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((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
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((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
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((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
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((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\
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((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
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((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\
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((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\
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((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
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((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\
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((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
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((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\
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((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
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((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\
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((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
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((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\
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((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
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((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
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((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
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((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
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((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
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#else
/* Single core lines */
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#if defined (PWR_CPUCR_SBF_D2)
/* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */
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#if defined (SMPS)
/* STM32H725 and STM32H735 lines */
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#define __HAL_PWR_GET_FLAG(__FLAG__) \
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(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
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((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
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((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
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((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
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((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\
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((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
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((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
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((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
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((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
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((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
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((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
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((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
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((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
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((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
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((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
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#else
/* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */
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#define __HAL_PWR_GET_FLAG(__FLAG__) \
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(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
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((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
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((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
435
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
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((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\
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((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
438
((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
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((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
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((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
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((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
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((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
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((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
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((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
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((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
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((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
447
#endif
/* defined (SMPS) */
448
#else
/* STM32H7Axxx and STM32H7Bxxx lines */
449
#if defined (SMPS)
/* STM32H7AxxQ and STM32H7BxxQ lines */
450
#define __HAL_PWR_GET_FLAG(__FLAG__) \
451
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
452
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
453
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
454
((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
455
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\
456
((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
457
((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
458
((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\
459
((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\
460
((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
461
((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
462
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
463
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
464
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
465
#else
/* STM32H7Axx and STM32H7Bxx lines */
466
#define __HAL_PWR_GET_FLAG(__FLAG__) \
467
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
468
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
469
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
470
((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
471
((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\
472
((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\
473
((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
474
((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
475
((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\
476
((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
477
((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
478
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
479
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
480
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
481
#endif
/* SMPS */
482
#endif
/* PWR_CPUCR_SBF_D2 */
483
#endif
/* DUAL_CORE */
484
498
#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
499
500
#if defined (DUAL_CORE)
511
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
512
do { \
513
SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \
514
SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
515
} while(0)
516
#else
527
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
528
#endif
/* defined (DUAL_CORE) */
529
543
#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
544
549
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
550
551
#if defined (DUAL_CORE)
556
#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
557
#endif
/* defined (DUAL_CORE) */
558
563
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
564
565
#if defined (DUAL_CORE)
570
#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
571
#endif
/* defined (DUAL_CORE) */
572
577
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
578
579
#if defined (DUAL_CORE)
584
#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
585
#endif
/* defined (DUAL_CORE) */
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#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
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#if defined (DUAL_CORE)
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#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
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#endif
/* defined (DUAL_CORE) */
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#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
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#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
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#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
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#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
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#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
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do { \
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__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
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__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
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} while(0);
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#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
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do { \
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__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
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__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
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} while(0);
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#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
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#if defined (DUAL_CORE)
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#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
657
#endif
/* defined (DUAL_CORE) */
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#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
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#if defined (DUAL_CORE)
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#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
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#endif
/* defined (DUAL_CORE) */
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#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
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/* Include PWR HAL Extension module */
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#include "
stm32h7xx_hal_pwr_ex.h
"
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/* Exported functions --------------------------------------------------------*/
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693
/* Initialization and de-initialization functions *****************************/
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void
HAL_PWR_DeInit (
void
);
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void
HAL_PWR_EnableBkUpAccess (
void
);
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void
HAL_PWR_DisableBkUpAccess (
void
);
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/* Peripheral Control functions **********************************************/
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/* PVD configuration */
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void
HAL_PWR_ConfigPVD (
PWR_PVDTypeDef
*sConfigPVD);
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void
HAL_PWR_EnablePVD (
void
);
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void
HAL_PWR_DisablePVD (
void
);
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/* WakeUp pins configuration */
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void
HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity);
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void
HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx);
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/* Low Power modes entry */
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void
HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry);
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void
HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry);
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void
HAL_PWR_EnterSTANDBYMode (
void
);
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/* Power PVD IRQ Handler */
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void
HAL_PWR_PVD_IRQHandler (
void
);
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void
HAL_PWR_PVDCallback (
void
);
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/* Cortex System Control functions *******************************************/
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void
HAL_PWR_EnableSleepOnExit (
void
);
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void
HAL_PWR_DisableSleepOnExit (
void
);
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void
HAL_PWR_EnableSEVOnPend (
void
);
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void
HAL_PWR_DisableSEVOnPend (
void
);
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/* Private types -------------------------------------------------------------*/
737
/* Private variables ---------------------------------------------------------*/
738
/* Private constants ---------------------------------------------------------*/
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#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16
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/* Private macros ------------------------------------------------------------*/
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/* Check PVD level parameter */
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#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
769
((LEVEL) == PWR_PVDLEVEL_1) ||\
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((LEVEL) == PWR_PVDLEVEL_2) ||\
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((LEVEL) == PWR_PVDLEVEL_3) ||\
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((LEVEL) == PWR_PVDLEVEL_4) ||\
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((LEVEL) == PWR_PVDLEVEL_5) ||\
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((LEVEL) == PWR_PVDLEVEL_6) ||\
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((LEVEL) == PWR_PVDLEVEL_7))
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/* Check PVD mode parameter */
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#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\
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((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
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((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
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((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
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((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
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((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
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((MODE) == PWR_PVD_MODE_NORMAL))
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/* Check low power regulator parameter */
787
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\
788
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
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/* Check low power mode entry parameter */
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#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
792
((ENTRY) == PWR_SLEEPENTRY_WFE))
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794
/* Check low power mode entry parameter */
795
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
796
((ENTRY) == PWR_STOPENTRY_WFE))
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798
/* Check voltage scale level parameter */
799
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
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((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
801
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
802
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
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814
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819
#ifdef __cplusplus
820
}
821
#endif
/* __cplusplus */
822
823
#endif
/* STM32H7xx_HAL_PWR_H */
824
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
stm32h7xx_hal_pwr_ex.h
Header file of PWR HAL Extension module.
PWR_PVDTypeDef
PWR PVD configuration structure definition.
Definition
stm32h7xx_hal_pwr.h:49
PWR_PVDTypeDef::PVDLevel
uint32_t PVDLevel
Definition
stm32h7xx_hal_pwr.h:50
PWR_PVDTypeDef::Mode
uint32_t Mode
Definition
stm32h7xx_hal_pwr.h:55
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