stm32f4xxxx_rcc.h File Reference

STM32F4XXXX RCC support. More...

#include <bsp/utility.h>

Go to the source code of this file.

Data Structures
struct	stm32f4_rcc

Macros
#define	STM32F4_RCC_CR_PLLI2SRDY   BSP_BIT32(27)
#define	STM32F4_RCC_CR_PLLI2SON   BSP_BIT32(26)
#define	STM32F4_RCC_CR_PLLRDY   BSP_BIT32(25)
#define	STM32F4_RCC_CR_PLLON   BSP_BIT32(24)
#define	STM32F4_RCC_CR_CSSON   BSP_BIT32(19)
#define	STM32F4_RCC_CR_HSEBYP   BSP_BIT32(18)
#define	STM32F4_RCC_CR_HSERDY   BSP_BIT32(17)
#define	STM32F4_RCC_CR_HSEON   BSP_BIT32(16)
#define	STM32F4_RCC_CR_HSIRDY   BSP_BIT32(1)
#define	STM32F4_RCC_CR_HSION   BSP_BIT32(0)
#define	STM32F4_RCC_PLLCFGR_PLLQ(val)
#define	STM32F4_RCC_PLLCFGR_PLLQ_GET(reg)
#define	STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val)
#define	STM32F4_RCC_PLLCFGR_SRC   BSP_BIT32(22)
#define	STM32F4_RCC_PLLCFGR_SRC_HSE   STM32F4_RCC_PLLCFGR_SRC
#define	STM32F4_RCC_PLLCFGR_SRC_HSI   0
#define	STM32F4_RCC_PLLCFGR_PLLP(val)
#define	STM32F4_RCC_PLLCFGR_PLLP_GET(reg)
#define	STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val)
#define	STM32F4_RCC_PLLCFGR_PLLP_2   STM32F4_RCC_PLLCFGR_PLLP(0)
#define	STM32F4_RCC_PLLCFGR_PLLP_4   STM32F4_RCC_PLLCFGR_PLLP(1)
#define	STM32F4_RCC_PLLCFGR_PLLP_6   STM32F4_RCC_PLLCFGR_PLLP(2)
#define	STM32F4_RCC_PLLCFGR_PLLP_8   STM32F4_RCC_PLLCFGR_PLLP(3)
#define	STM32F4_RCC_PLLCFGR_PLLN(val)
#define	STM32F4_RCC_PLLCFGR_PLLN_GET(reg)
#define	STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val)
#define	STM32F4_RCC_PLLCFGR_PLLM(val)
#define	STM32F4_RCC_PLLCFGR_PLLM_GET(reg)
#define	STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val)
#define	STM32F4_RCC_CFGR_MCO2(val)
#define	STM32F4_RCC_CFGR_MCO2_GET(reg)
#define	STM32F4_RCC_CFGR_MCO2_SET(reg, val)
#define	STM32F4_RCC_CFGR_MCO2_SYSCLK   STM32F4_RCC_CFGR_MCO2(0)
#define	STM32F4_RCC_CFGR_MCO2_PLLI2S   STM32F4_RCC_CFGR_MCO2(1)
#define	STM32F4_RCC_CFGR_MCO2_HSE   STM32F4_RCC_CFGR_MCO2(2)
#define	STM32F4_RCC_CFGR_MCO2_PLL   STM32F4_RCC_CFGR_MCO2(3)
#define	STM32F4_RCC_CFGR_MCO2_PRE(val)
#define	STM32F4_RCC_CFGR_MCO2_PRE_GET(reg)
#define	STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val)
#define	STM32F4_RCC_CFGR_MCO2_DIV1   STM32F4_RCC_CFGR_MCO2_PRE(0)
#define	STM32F4_RCC_CFGR_MCO2_DIV2   STM32F4_RCC_CFGR_MCO2_PRE(4)
#define	STM32F4_RCC_CFGR_MCO2_DIV3   STM32F4_RCC_CFGR_MCO2_PRE(5)
#define	STM32F4_RCC_CFGR_MCO2_DIV4   STM32F4_RCC_CFGR_MCO2_PRE(6)
#define	STM32F4_RCC_CFGR_MCO2_DIV5   STM32F4_RCC_CFGR_MCO2_PRE(7)
#define	STM32F4_RCC_CFGR_MCO1_PRE(val)
#define	STM32F4_RCC_CFGR_MCO1_PRE_GET(reg)
#define	STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val)
#define	STM32F4_RCC_CFGR_MCO1_DIV1   STM32F4_RCC_CFGR_MCO1_PRE(0)
#define	STM32F4_RCC_CFGR_MCO1_DIV2   STM32F4_RCC_CFGR_MCO1_PRE(4)
#define	STM32F4_RCC_CFGR_MCO1_DIV3   STM32F4_RCC_CFGR_MCO1_PRE(5)
#define	STM32F4_RCC_CFGR_MCO1_DIV4   STM32F4_RCC_CFGR_MCO1_PRE(6)
#define	STM32F4_RCC_CFGR_MCO1_DIV5   STM32F4_RCC_CFGR_MCO1_PRE(7)
#define	STM32F4_RCC_CFGR_I2SSCR   BSP_BIT32(23)
#define	STM32F4_RCC_CFGR_MCO1(val)
#define	STM32F4_RCC_CFGR_MCO1_GET(reg)
#define	STM32F4_RCC_CFGR_MCO1_SET(reg, val)
#define	STM32F4_RCC_CFGR_MCO1_HSI   STM32F4_RCC_CFGR_MCO1(0)
#define	STM32F4_RCC_CFGR_MCO1_LSE   STM32F4_RCC_CFGR_MCO1(1)
#define	STM32F4_RCC_CFGR_MCO1_HSE   STM32F4_RCC_CFGR_MCO1(2)
#define	STM32F4_RCC_CFGR_MCO1_PLL   STM32F4_RCC_CFGR_MCO1(3)
#define	STM32F4_RCC_CFGR_RTCPRE(val)
#define	STM32F4_RCC_CFGR_RTCPRE_GET(reg)
#define	STM32F4_RCC_CFGR_RTCPRE_SET(reg, val)
#define	STM32F4_RCC_CFGR_PPRE2(val)
#define	STM32F4_RCC_CFGR_PPRE2_GET(reg)
#define	STM32F4_RCC_CFGR_PPRE2_SET(reg, val)
#define	STM32F4_RCC_CFGR_PPRE2_DIV1   STM32F4_RCC_CFGR_PPRE2(0)
#define	STM32F4_RCC_CFGR_PPRE2_DIV2   STM32F4_RCC_CFGR_PPRE2(4)
#define	STM32F4_RCC_CFGR_PPRE2_DIV4   STM32F4_RCC_CFGR_PPRE2(5)
#define	STM32F4_RCC_CFGR_PPRE2_DIV8   STM32F4_RCC_CFGR_PPRE2(6)
#define	STM32F4_RCC_CFGR_PPRE2_DIV16   STM32F4_RCC_CFGR_PPRE2(7)
#define	STM32F4_RCC_CFGR_PPRE1(val)
#define	STM32F4_RCC_CFGR_PPRE1_GET(reg)
#define	STM32F4_RCC_CFGR_PPRE1_SET(reg, val)
#define	STM32F4_RCC_CFGR_PPRE1_DIV1   STM32F4_RCC_CFGR_PPRE1(0)
#define	STM32F4_RCC_CFGR_PPRE1_DIV2   STM32F4_RCC_CFGR_PPRE1(4)
#define	STM32F4_RCC_CFGR_PPRE1_DIV4   STM32F4_RCC_CFGR_PPRE1(5)
#define	STM32F4_RCC_CFGR_PPRE1_DIV8   STM32F4_RCC_CFGR_PPRE1(6)
#define	STM32F4_RCC_CFGR_PPRE1_DIV16   STM32F4_RCC_CFGR_PPRE1(7)
#define	STM32F4_RCC_CFGR_HPRE(val)
#define	STM32F4_RCC_CFGR_HPRE_GET(reg)
#define	STM32F4_RCC_CFGR_HPRE_SET(reg, val)
#define	STM32F4_RCC_CFGR_HPRE_DIV1   STM32F4_RCC_CFGR_HPRE(0)
#define	STM32F4_RCC_CFGR_HPRE_DIV2   STM32F4_RCC_CFGR_HPRE(8)
#define	STM32F4_RCC_CFGR_HPRE_DIV4   STM32F4_RCC_CFGR_HPRE(9)
#define	STM32F4_RCC_CFGR_HPRE_DIV8   STM32F4_RCC_CFGR_HPRE(10)
#define	STM32F4_RCC_CFGR_HPRE_DIV16   STM32F4_RCC_CFGR_HPRE(11)
#define	STM32F4_RCC_CFGR_HPRE_DIV64   STM32F4_RCC_CFGR_HPRE(12)
#define	STM32F4_RCC_CFGR_HPRE_DIV128   STM32F4_RCC_CFGR_HPRE(13)
#define	STM32F4_RCC_CFGR_HPRE_DIV256   STM32F4_RCC_CFGR_HPRE(14)
#define	STM32F4_RCC_CFGR_HPRE_DIV512   STM32F4_RCC_CFGR_HPRE(15)
#define	STM32F4_RCC_CFGR_SWS(val)
#define	STM32F4_RCC_CFGR_SWS_GET(reg)
#define	STM32F4_RCC_CFGR_SWS_SET(reg, val)
#define	STM32F4_RCC_CFGR_SWS_HSI   STM32F4_RCC_CFGR_SWS(0)
#define	STM32F4_RCC_CFGR_SWS_HSE   STM32F4_RCC_CFGR_SWS(1)
#define	STM32F4_RCC_CFGR_SWS_PLL   STM32F4_RCC_CFGR_SWS(2)
#define	STM32F4_RCC_CFGR_SW(val)
#define	STM32F4_RCC_CFGR_SW_GET(reg)
#define	STM32F4_RCC_CFGR_SW_SET(reg, val)
#define	STM32F4_RCC_CFGR_SW_HSI   STM32F4_RCC_CFGR_SW(0)
#define	STM32F4_RCC_CFGR_SW_HSE   STM32F4_RCC_CFGR_SW(1)
#define	STM32F4_RCC_CFGR_SW_PLL   STM32F4_RCC_CFGR_SW(2)
#define	RCC_CR_HSION   BSP_BIT32( 0 )
#define	RCC_CR_HSIRDY   BSP_BIT32( 1 )
#define	RCC_CR_HSITRIM(val)
#define	RCC_CR_HSITRIM_MSK   BSP_MSK32( 3, 7 )
#define	RCC_CR_HSICAL(val)
#define	RCC_CR_HSICAL_MSK   BSP_MSK32( 8, 15 )
#define	RCC_CR_HSEON   BSP_BIT32( 16 )
#define	RCC_CR_HSERDY   BSP_BIT32( 17 )
#define	RCC_CR_HSEBYP   BSP_BIT32( 18 )
#define	RCC_CR_CSSON   BSP_BIT32( 19 )
#define	RCC_CR_PLLON   BSP_BIT32( 24 )
#define	RCC_CR_PLLRDY   BSP_BIT32( 25 )
#define	RCC_CR_PLLI2SON   BSP_BIT32( 26 )
#define	RCC_CR_PLLI2SRDY   BSP_BIT32( 27 )
#define	RCC_PLLCFGR_PLLM(val)
#define	RCC_PLLCFGR_PLLM_MSK   BSP_MSK32( 0, 5 )
#define	RCC_PLLCFGR_PLLN(val)
#define	RCC_PLLCFGR_PLLN_MSK   BSP_MSK32( 6, 14 )
#define	RCC_PLLCFGR_PLLP   16
#define	RCC_PLLCFGR_PLLP_MSK   BSP_MSK32( 16, 17 )
#define	RCC_PLLCFGR_PLLP_BY_2   0
#define	RCC_PLLCFGR_PLLP_BY_4   BSP_FLD32( 1, 16, 17 )
#define	RCC_PLLCFGR_PLLP_BY_6   BSP_FLD32( 2, 16, 17 )
#define	RCC_PLLCFGR_PLLP_BY_8   BSP_FLD32( 3, 16, 17 )
#define	RCC_PLLCFGR_PLLSRC_HSE   BSP_BIT32( 22 )
#define	RCC_PLLCFGR_PLLSRC_HSI   0
#define	RCC_PLLCFGR_PLLQ(val)
#define	RCC_PLLCFGR_PLLQ_MSK   BSP_MSK32( 24, 27 )
#define	RCC_CFGR_SW   0
#define	RCC_CFGR_SW_MSK   BSP_MSK32( 0, 1 )
#define	RCC_CFGR_SW_HSI   0
#define	RCC_CFGR_SW_HSE   1
#define	RCC_CFGR_SW_PLL   2
#define	RCC_CFGR_SWS   2
#define	RCC_CFGR_SWS_MSK   BSP_MSK32( 2, 3 )
#define	RCC_CFGR_SWS_HSI   0
#define	RCC_CFGR_SWS_HSE   BSP_FLD32( 1, 2, 3 )
#define	RCC_CFGR_SWS_PLL   BSP_FLD32( 2, 2, 3 )
#define	RCC_CFGR_HPRE   4
#define	RCC_CFGR_HPRE_BY_1   0
#define	RCC_CFGR_HPRE_BY_2   BSP_FLD32( 8, 4, 7 )
#define	RCC_CFGR_HPRE_BY_4   BSP_FLD32( 9, 4, 7 )
#define	RCC_CFGR_HPRE_BY_8   BSP_FLD32( 10, 4, 7 )
#define	RCC_CFGR_HPRE_BY_16   BSP_FLD32( 11, 4, 7 )
#define	RCC_CFGR_HPRE_BY_64   BSP_FLD32( 12, 4, 7 )
#define	RCC_CFGR_HPRE_BY_128   BSP_FLD32( 13, 4, 7 )
#define	RCC_CFGR_HPRE_BY_256   BSP_FLD32( 14, 4, 7 )
#define	RCC_CFGR_HPRE_BY_512   BSP_FLD32( 15, 4, 7 )
#define	RCC_CFGR_PPRE1   10
#define	RCC_CFGR_PPRE1_BY_1   0
#define	RCC_CFGR_PPRE1_BY_2   BSP_FLD32( 4, 10, 12 )
#define	RCC_CFGR_PPRE1_BY_4   BSP_FLD32( 5, 10, 12 )
#define	RCC_CFGR_PPRE1_BY_8   BSP_FLD32( 6, 10, 12 )
#define	RCC_CFGR_PPRE1_BY_16   BSP_FLD32( 7, 10, 12 )
#define	RCC_CFGR_PPRE2   13
#define	RCC_CFGR_PPRE2   BSP_MSK32( 13, 15 )
#define	RCC_CFGR_PPRE2_BY_1   0
#define	RCC_CFGR_PPRE2_BY_2   BSP_FLD32( 4, 13, 15 )
#define	RCC_CFGR_PPRE2_BY_4   BSP_FLD32( 5, 13, 15 )
#define	RCC_CFGR_PPRE2_BY_8   BSP_FLD32( 6, 13, 15 )
#define	RCC_CFGR_PPRE2_BY_16   BSP_FLD32( 7, 13, 15 )
#define	RCC_CFGR_RTCPRE(val)
#define	RCC_CFGR_RTCPRE_MSK   BSP_MSK32( 16, 20 )
#define	RCC_CFGR_MCO1   21
#define	RCC_CFGR_MCO1_MSK   BSP_MSK32( 21, 22 )
#define	RCC_CFGR_MCO1_HSI   0
#define	RCC_CFGR_MCO1_LSE   BSP_FLD32( 1, 21, 22 )
#define	RCC_CFGR_MCO1_HSE   BSP_FLD32( 2, 21, 22 )
#define	RCC_CFGR_MCO1_PLL   BSP_FLD32( 3, 21, 22 )
#define	RCC_CFGR_I2SSRC   BSP_BIT32( 23 )
#define	RCC_CFGR_MCO1PRE   24
#define	RCC_CFGR_MCO1PRE_MSK   BSP_MSK32( 24, 26 )
#define	RCC_CFGR_MCO1PRE_BY_1   0
#define	RCC_CFGR_MCO1PRE_BY_2   BSP_FLD32( 4, 24, 26 )
#define	RCC_CFGR_MCO1PRE_BY_3   BSP_FLD32( 5, 24, 26 )
#define	RCC_CFGR_MCO1PRE_BY_4   BSP_FLD32( 6, 24, 26 )
#define	RCC_CFGR_MCO1PRE_BY_5   BSP_FLD32( 7, 24, 26 )
#define	RCC_CFGR_MCO2PRE   27
#define	RCC_CFGR_MCO2PRE_MSK   BSP_MSK32( 27, 29 )
#define	RCC_CFGR_MCO2PRE_BY_1   0
#define	RCC_CFGR_MCO2PRE_BY_2   BSP_FLD32( 4, 27, 29 )
#define	RCC_CFGR_MCO2PRE_BY_3   BSP_FLD32( 5, 27, 29 )
#define	RCC_CFGR_MCO2PRE_BY_4   BSP_FLD32( 6, 27, 29 )
#define	RCC_CFGR_MCO2PRE_BY_5   BSP_FLD32( 7, 27, 29 )
#define	RCC_CFGR_MCO2   30
#define	RCC_CFGR_MCO2_MSK   BSP_MSK32( 30, 31 )
#define	RCC_CFGR_MCO2_SYSCLK   0
#define	RCC_CFGR_MCO2_PLLI2S   BSP_FLD32( 1, 30, 31 )
#define	RCC_CFGR_MCO2_HSE   BSP_FLD32( 2, 30, 31 )
#define	RCC_CFGR_MCO2_PLL   BSP_FLD32( 3, 30, 31 )

Detailed Description

STM32F4XXXX RCC support.

Macro Definition Documentation

RCC_CFGR_RTCPRE

#define RCC_CFGR_RTCPRE

(

val

)

Value:

BSP_FLD32( val, 16, 20 )

RCC_CR_HSICAL

#define RCC_CR_HSICAL

(

val

)

Value:

BSP_FLD32( val, 8, 15 )

RCC_CR_HSITRIM

#define RCC_CR_HSITRIM

(

val

)

Value:

BSP_FLD32( val, 3, 7 )

RCC_PLLCFGR_PLLM

#define RCC_PLLCFGR_PLLM

(

val

)

Value:

BSP_FLD32( val, 0, 5 )

RCC_PLLCFGR_PLLN

#define RCC_PLLCFGR_PLLN

(

val

)

Value:

BSP_FLD32( val, 6, 14 )

RCC_PLLCFGR_PLLQ

#define RCC_PLLCFGR_PLLQ

(

val

)

Value:

BSP_FLD32( val, 24, 27 )

STM32F4_RCC_CFGR_HPRE

#define STM32F4_RCC_CFGR_HPRE

(

val

)

Value:

BSP_FLD32(val, 4, 15)

STM32F4_RCC_CFGR_HPRE_GET

#define STM32F4_RCC_CFGR_HPRE_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 4, 7)

STM32F4_RCC_CFGR_HPRE_SET

#define STM32F4_RCC_CFGR_HPRE_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 4, 7)

STM32F4_RCC_CFGR_MCO1

#define STM32F4_RCC_CFGR_MCO1

(

val

)

Value:

BSP_FLD32(val, 21, 22)

STM32F4_RCC_CFGR_MCO1_GET

#define STM32F4_RCC_CFGR_MCO1_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 21, 22)

STM32F4_RCC_CFGR_MCO1_PRE

#define STM32F4_RCC_CFGR_MCO1_PRE

(

val

)

Value:

BSP_FLD32(val, 24, 26)

STM32F4_RCC_CFGR_MCO1_PRE_GET

#define STM32F4_RCC_CFGR_MCO1_PRE_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 24, 26)

STM32F4_RCC_CFGR_MCO1_PRE_SET

#define STM32F4_RCC_CFGR_MCO1_PRE_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 24, 26)

STM32F4_RCC_CFGR_MCO1_SET

#define STM32F4_RCC_CFGR_MCO1_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 21, 22)

STM32F4_RCC_CFGR_MCO2

#define STM32F4_RCC_CFGR_MCO2

(

val

)

Value:

BSP_FLD32(val, 30, 31)

STM32F4_RCC_CFGR_MCO2_GET

#define STM32F4_RCC_CFGR_MCO2_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 30, 31)

STM32F4_RCC_CFGR_MCO2_PRE

#define STM32F4_RCC_CFGR_MCO2_PRE

(

val

)

Value:

BSP_FLD32(val, 27, 29)

STM32F4_RCC_CFGR_MCO2_PRE_GET

#define STM32F4_RCC_CFGR_MCO2_PRE_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 27, 29)

STM32F4_RCC_CFGR_MCO2_PRE_SET

#define STM32F4_RCC_CFGR_MCO2_PRE_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 27, 29)

STM32F4_RCC_CFGR_MCO2_SET

#define STM32F4_RCC_CFGR_MCO2_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 30, 31)

STM32F4_RCC_CFGR_PPRE1

#define STM32F4_RCC_CFGR_PPRE1

(

val

)

Value:

BSP_FLD32(val, 10, 12)

STM32F4_RCC_CFGR_PPRE1_GET

#define STM32F4_RCC_CFGR_PPRE1_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 10, 12)

STM32F4_RCC_CFGR_PPRE1_SET

#define STM32F4_RCC_CFGR_PPRE1_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 10, 12)

STM32F4_RCC_CFGR_PPRE2

#define STM32F4_RCC_CFGR_PPRE2

(

val

)

Value:

BSP_FLD32(val, 13, 15)

STM32F4_RCC_CFGR_PPRE2_GET

#define STM32F4_RCC_CFGR_PPRE2_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 13, 15)

STM32F4_RCC_CFGR_PPRE2_SET

#define STM32F4_RCC_CFGR_PPRE2_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 13, 15)

STM32F4_RCC_CFGR_RTCPRE

#define STM32F4_RCC_CFGR_RTCPRE

(

val

)

Value:

BSP_FLD32(val, 16, 20)

STM32F4_RCC_CFGR_RTCPRE_GET

#define STM32F4_RCC_CFGR_RTCPRE_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 16, 20)

STM32F4_RCC_CFGR_RTCPRE_SET

#define STM32F4_RCC_CFGR_RTCPRE_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 16, 20)

STM32F4_RCC_CFGR_SW

#define STM32F4_RCC_CFGR_SW

(

val

)

Value:

BSP_FLD32(val, 0, 1)

STM32F4_RCC_CFGR_SW_GET

#define STM32F4_RCC_CFGR_SW_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 1)

STM32F4_RCC_CFGR_SW_SET

#define STM32F4_RCC_CFGR_SW_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 1)

STM32F4_RCC_CFGR_SWS

#define STM32F4_RCC_CFGR_SWS

(

val

)

Value:

BSP_FLD32(val, 2, 3)

STM32F4_RCC_CFGR_SWS_GET

#define STM32F4_RCC_CFGR_SWS_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 2, 3)

STM32F4_RCC_CFGR_SWS_SET

#define STM32F4_RCC_CFGR_SWS_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 2, 3)

STM32F4_RCC_PLLCFGR_PLLM

#define STM32F4_RCC_PLLCFGR_PLLM

(

val

)

Value:

BSP_FLD32(val, 0, 5)

STM32F4_RCC_PLLCFGR_PLLM_GET

#define STM32F4_RCC_PLLCFGR_PLLM_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 5)

STM32F4_RCC_PLLCFGR_PLLM_SET

#define STM32F4_RCC_PLLCFGR_PLLM_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 5)

STM32F4_RCC_PLLCFGR_PLLN

#define STM32F4_RCC_PLLCFGR_PLLN

(

val

)

Value:

BSP_FLD32(val, 6, 14)

STM32F4_RCC_PLLCFGR_PLLN_GET

#define STM32F4_RCC_PLLCFGR_PLLN_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 6, 14)

STM32F4_RCC_PLLCFGR_PLLN_SET

#define STM32F4_RCC_PLLCFGR_PLLN_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 6, 14)

STM32F4_RCC_PLLCFGR_PLLP

#define STM32F4_RCC_PLLCFGR_PLLP

(

val

)

Value:

BSP_FLD32(val, 16, 17)

STM32F4_RCC_PLLCFGR_PLLP_GET

#define STM32F4_RCC_PLLCFGR_PLLP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 16, 17)

STM32F4_RCC_PLLCFGR_PLLP_SET

#define STM32F4_RCC_PLLCFGR_PLLP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 16, 17)

STM32F4_RCC_PLLCFGR_PLLQ

#define STM32F4_RCC_PLLCFGR_PLLQ

(

val

)

Value:

BSP_FLD32(val, 24, 27)

STM32F4_RCC_PLLCFGR_PLLQ_GET

#define STM32F4_RCC_PLLCFGR_PLLQ_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 24, 27)

STM32F4_RCC_PLLCFGR_PLLQ_SET

#define STM32F4_RCC_PLLCFGR_PLLQ_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 24, 27)