6.3/docs/rtems-6.3-doxygen-html.tar.xz

/* ---------------------------------------------------------------------------- */

/*                  Atmel Microcontroller Software Support                      */

/*                       SAM Software Package License                           */

/* ---------------------------------------------------------------------------- */

/* Copyright (c) 2015, Atmel Corporation                                        */

/*                                                                              */

/* All rights reserved.                                                         */

/*                                                                              */

/* Redistribution and use in source and binary forms, with or without           */

/* modification, are permitted provided that the following condition is met:    */

/*                                                                              */

/* - Redistributions of source code must retain the above copyright notice,     */

/* this list of conditions and the disclaimer below.                            */

/*                                                                              */

/* Atmel's name may not be used to endorse or promote products derived from     */

/* this software without specific prior written permission.                     */

/*                                                                              */

/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */

/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */

/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */

/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */

/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */

/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */

/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */

/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */

/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */

/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */

/* ---------------------------------------------------------------------------- */


#ifndef _SAMV71_SSC_COMPONENT_

#define _SAMV71_SSC_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __O  uint32_t SSC_CR;

  __IO uint32_t SSC_CMR;

  __I  uint32_t Reserved1[2];

  __IO uint32_t SSC_RCMR;

  __IO uint32_t SSC_RFMR;

  __IO uint32_t SSC_TCMR;

  __IO uint32_t SSC_TFMR;

  __I  uint32_t SSC_RHR;

  __O  uint32_t SSC_THR;

  __I  uint32_t Reserved2[2];

  __I  uint32_t SSC_RSHR;

  __IO uint32_t SSC_TSHR;

  __IO uint32_t SSC_RC0R;

  __IO uint32_t SSC_RC1R;

  __I  uint32_t SSC_SR;

  __O  uint32_t SSC_IER;

  __O  uint32_t SSC_IDR;

  __I  uint32_t SSC_IMR;

  __I  uint32_t Reserved3[37];

  __IO uint32_t SSC_WPMR;

  __I  uint32_t SSC_WPSR;

  __I  uint32_t Reserved4[4];

  __I  uint32_t SSC_VERSION;

} Ssc;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */

#define SSC_CR_RXEN (0x1u << 0)

#define SSC_CR_RXDIS (0x1u << 1)

#define SSC_CR_TXEN (0x1u << 8)

#define SSC_CR_TXDIS (0x1u << 9)

#define SSC_CR_SWRST (0x1u << 15)

/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */

#define SSC_CMR_DIV_Pos 0

#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos)

#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))

/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */

#define SSC_RCMR_CKS_Pos 0

#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos)

#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)))

#define   SSC_RCMR_CKS_MCK (0x0u << 0)

#define   SSC_RCMR_CKS_TK (0x1u << 0)

#define   SSC_RCMR_CKS_RK (0x2u << 0)

#define SSC_RCMR_CKO_Pos 2

#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos)

#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)))

#define   SSC_RCMR_CKO_NONE (0x0u << 2)

#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2)

#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2)

#define SSC_RCMR_CKI (0x1u << 5)

#define SSC_RCMR_CKG_Pos 6

#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos)

#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)))

#define   SSC_RCMR_CKG_CONTINUOUS (0x0u << 6)

#define   SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6)

#define   SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6)

#define SSC_RCMR_START_Pos 8

#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos)

#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)))

#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8)

#define   SSC_RCMR_START_TRANSMIT (0x1u << 8)

#define   SSC_RCMR_START_RF_LOW (0x2u << 8)

#define   SSC_RCMR_START_RF_HIGH (0x3u << 8)

#define   SSC_RCMR_START_RF_FALLING (0x4u << 8)

#define   SSC_RCMR_START_RF_RISING (0x5u << 8)

#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8)

#define   SSC_RCMR_START_RF_EDGE (0x7u << 8)

#define   SSC_RCMR_START_CMP_0 (0x8u << 8)

#define SSC_RCMR_STOP (0x1u << 12)

#define SSC_RCMR_STTDLY_Pos 16

#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos)

#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))

#define SSC_RCMR_PERIOD_Pos 24

#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos)

#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))

/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */

#define SSC_RFMR_DATLEN_Pos 0

#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos)

#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))

#define SSC_RFMR_LOOP (0x1u << 5)

#define SSC_RFMR_MSBF (0x1u << 7)

#define SSC_RFMR_DATNB_Pos 8

#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos)

#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))

#define SSC_RFMR_FSLEN_Pos 16

#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos)

#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))

#define SSC_RFMR_FSOS_Pos 20

#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos)

#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)))

#define   SSC_RFMR_FSOS_NONE (0x0u << 20)

#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20)

#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20)

#define   SSC_RFMR_FSOS_LOW (0x3u << 20)

#define   SSC_RFMR_FSOS_HIGH (0x4u << 20)

#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20)

#define SSC_RFMR_FSEDGE (0x1u << 24)

#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24)

#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24)

#define SSC_RFMR_FSLEN_EXT_Pos 28

#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos)

#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))

/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */

#define SSC_TCMR_CKS_Pos 0

#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos)

#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)))

#define   SSC_TCMR_CKS_MCK (0x0u << 0)

#define   SSC_TCMR_CKS_RK (0x1u << 0)

#define   SSC_TCMR_CKS_TK (0x2u << 0)

#define SSC_TCMR_CKO_Pos 2

#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos)

#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)))

#define   SSC_TCMR_CKO_NONE (0x0u << 2)

#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2)

#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2)

#define SSC_TCMR_CKI (0x1u << 5)

#define SSC_TCMR_CKG_Pos 6

#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos)

#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)))

#define   SSC_TCMR_CKG_CONTINUOUS (0x0u << 6)

#define   SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6)

#define   SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6)

#define SSC_TCMR_START_Pos 8

#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos)

#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)))

#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8)

#define   SSC_TCMR_START_RECEIVE (0x1u << 8)

#define   SSC_TCMR_START_TF_LOW (0x2u << 8)

#define   SSC_TCMR_START_TF_HIGH (0x3u << 8)

#define   SSC_TCMR_START_TF_FALLING (0x4u << 8)

#define   SSC_TCMR_START_TF_RISING (0x5u << 8)

#define   SSC_TCMR_START_TF_LEVEL (0x6u << 8)

#define   SSC_TCMR_START_TF_EDGE (0x7u << 8)

#define SSC_TCMR_STTDLY_Pos 16

#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos)

#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))

#define SSC_TCMR_PERIOD_Pos 24

#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos)

#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))

/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */

#define SSC_TFMR_DATLEN_Pos 0

#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos)

#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))

#define SSC_TFMR_DATDEF (0x1u << 5)

#define SSC_TFMR_MSBF (0x1u << 7)

#define SSC_TFMR_DATNB_Pos 8

#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos)

#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))

#define SSC_TFMR_FSLEN_Pos 16

#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos)

#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))

#define SSC_TFMR_FSOS_Pos 20

#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos)

#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)))

#define   SSC_TFMR_FSOS_NONE (0x0u << 20)

#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20)

#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20)

#define   SSC_TFMR_FSOS_LOW (0x3u << 20)

#define   SSC_TFMR_FSOS_HIGH (0x4u << 20)

#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20)

#define SSC_TFMR_FSDEN (0x1u << 23)

#define SSC_TFMR_FSEDGE (0x1u << 24)

#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24)

#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24)

#define SSC_TFMR_FSLEN_EXT_Pos 28

#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos)

#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))

/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */

#define SSC_RHR_RDAT_Pos 0

#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos)

/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */

#define SSC_THR_TDAT_Pos 0

#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos)

#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))

/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */

#define SSC_RSHR_RSDAT_Pos 0

#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos)

/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */

#define SSC_TSHR_TSDAT_Pos 0

#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos)

#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))

/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */

#define SSC_RC0R_CP0_Pos 0

#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos)

#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))

/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */

#define SSC_RC1R_CP1_Pos 0

#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos)

#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))

/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */

#define SSC_SR_TXRDY (0x1u << 0)

#define SSC_SR_TXEMPTY (0x1u << 1)

#define SSC_SR_RXRDY (0x1u << 4)

#define SSC_SR_OVRUN (0x1u << 5)

#define SSC_SR_CP0 (0x1u << 8)

#define SSC_SR_CP1 (0x1u << 9)

#define SSC_SR_TXSYN (0x1u << 10)

#define SSC_SR_RXSYN (0x1u << 11)

#define SSC_SR_TXEN (0x1u << 16)

#define SSC_SR_RXEN (0x1u << 17)

/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */

#define SSC_IER_TXRDY (0x1u << 0)

#define SSC_IER_TXEMPTY (0x1u << 1)

#define SSC_IER_RXRDY (0x1u << 4)

#define SSC_IER_OVRUN (0x1u << 5)

#define SSC_IER_CP0 (0x1u << 8)

#define SSC_IER_CP1 (0x1u << 9)

#define SSC_IER_TXSYN (0x1u << 10)

#define SSC_IER_RXSYN (0x1u << 11)

/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */

#define SSC_IDR_TXRDY (0x1u << 0)

#define SSC_IDR_TXEMPTY (0x1u << 1)

#define SSC_IDR_RXRDY (0x1u << 4)

#define SSC_IDR_OVRUN (0x1u << 5)

#define SSC_IDR_CP0 (0x1u << 8)

#define SSC_IDR_CP1 (0x1u << 9)

#define SSC_IDR_TXSYN (0x1u << 10)

#define SSC_IDR_RXSYN (0x1u << 11)

/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */

#define SSC_IMR_TXRDY (0x1u << 0)

#define SSC_IMR_TXEMPTY (0x1u << 1)

#define SSC_IMR_RXRDY (0x1u << 4)

#define SSC_IMR_OVRUN (0x1u << 5)

#define SSC_IMR_CP0 (0x1u << 8)

#define SSC_IMR_CP1 (0x1u << 9)

#define SSC_IMR_TXSYN (0x1u << 10)

#define SSC_IMR_RXSYN (0x1u << 11)

/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */

#define SSC_WPMR_WPEN (0x1u << 0)

#define SSC_WPMR_WPKEY_Pos 8

#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos)

#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))

#define   SSC_WPMR_WPKEY_PASSWD (0x535343u << 8)

/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */

#define SSC_WPSR_WPVS (0x1u << 0)

#define SSC_WPSR_WPVSRC_Pos 8

#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos)

/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */

#define SSC_VERSION_VERSION_Pos 0

#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos)

#define SSC_VERSION_MFN_Pos 16

#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos)


#endif /* _SAMV71_SSC_COMPONENT_ */

__O
#define __O
Definition core_cm4.h:238

__IO
#define __IO
Definition core_cm4.h:239

__I
#define __I
Definition core_cm4.h:236

Ssc
Ssc hardware registers.
Definition component_ssc.h:41

Ssc::SSC_VERSION
__I uint32_t SSC_VERSION
(Ssc Offset: 0xFC) Version Register
Definition component_ssc.h:64