RTEMS
6.3
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bsps
arm
atsam
include
libchip
include
samv71
component
component_spi.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMV71_SPI_COMPONENT_
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#define _SAMV71_SPI_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__O
uint32_t SPI_CR;
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__IO
uint32_t SPI_MR;
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__I
uint32_t SPI_RDR;
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__O
uint32_t SPI_TDR;
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__I
uint32_t SPI_SR;
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__O
uint32_t SPI_IER;
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__O
uint32_t SPI_IDR;
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__I
uint32_t SPI_IMR;
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__I
uint32_t Reserved1[4];
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__IO
uint32_t SPI_CSR[4];
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__I
uint32_t Reserved2[41];
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__IO
uint32_t SPI_WPMR;
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__I
uint32_t SPI_WPSR;
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__I
uint32_t Reserved3[4];
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__I
uint32_t
SPI_VERSION
;
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}
Spi
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
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#define SPI_CR_SPIEN (0x1u << 0)
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#define SPI_CR_SPIDIS (0x1u << 1)
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#define SPI_CR_SWRST (0x1u << 7)
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#define SPI_CR_LASTXFER (0x1u << 24)
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/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
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#define SPI_MR_MSTR (0x1u << 0)
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#define SPI_MR_PS (0x1u << 1)
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#define SPI_MR_PCSDEC (0x1u << 2)
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#define SPI_MR_MODFDIS (0x1u << 4)
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#define SPI_MR_WDRBT (0x1u << 5)
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#define SPI_MR_LLB (0x1u << 7)
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#define SPI_MR_PCS_Pos 16
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#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos)
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#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
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#define SPI_MR_DLYBCS_Pos 24
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#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos)
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#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
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/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
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#define SPI_RDR_RD_Pos 0
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#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos)
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#define SPI_RDR_PCS_Pos 16
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#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos)
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/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
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#define SPI_TDR_TD_Pos 0
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#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos)
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#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
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#define SPI_TDR_PCS_Pos 16
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#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos)
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#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
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#define SPI_TDR_LASTXFER (0x1u << 24)
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/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
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#define SPI_SR_RDRF (0x1u << 0)
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#define SPI_SR_TDRE (0x1u << 1)
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#define SPI_SR_MODF (0x1u << 2)
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#define SPI_SR_OVRES (0x1u << 3)
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#define SPI_SR_NSSR (0x1u << 8)
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#define SPI_SR_TXEMPTY (0x1u << 9)
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#define SPI_SR_UNDES (0x1u << 10)
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#define SPI_SR_SPIENS (0x1u << 16)
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/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
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#define SPI_IER_RDRF (0x1u << 0)
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#define SPI_IER_TDRE (0x1u << 1)
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#define SPI_IER_MODF (0x1u << 2)
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#define SPI_IER_OVRES (0x1u << 3)
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#define SPI_IER_NSSR (0x1u << 8)
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#define SPI_IER_TXEMPTY (0x1u << 9)
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#define SPI_IER_UNDES (0x1u << 10)
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/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
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#define SPI_IDR_RDRF (0x1u << 0)
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#define SPI_IDR_TDRE (0x1u << 1)
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#define SPI_IDR_MODF (0x1u << 2)
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#define SPI_IDR_OVRES (0x1u << 3)
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#define SPI_IDR_NSSR (0x1u << 8)
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#define SPI_IDR_TXEMPTY (0x1u << 9)
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#define SPI_IDR_UNDES (0x1u << 10)
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/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
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#define SPI_IMR_RDRF (0x1u << 0)
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#define SPI_IMR_TDRE (0x1u << 1)
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#define SPI_IMR_MODF (0x1u << 2)
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#define SPI_IMR_OVRES (0x1u << 3)
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#define SPI_IMR_NSSR (0x1u << 8)
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#define SPI_IMR_TXEMPTY (0x1u << 9)
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#define SPI_IMR_UNDES (0x1u << 10)
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/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
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#define SPI_CSR_CPOL (0x1u << 0)
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#define SPI_CSR_NCPHA (0x1u << 1)
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#define SPI_CSR_CSNAAT (0x1u << 2)
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#define SPI_CSR_CSAAT (0x1u << 3)
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#define SPI_CSR_BITS_Pos 4
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#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos)
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#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))
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#define SPI_CSR_BITS_8_BIT (0x0u << 4)
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#define SPI_CSR_BITS_9_BIT (0x1u << 4)
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#define SPI_CSR_BITS_10_BIT (0x2u << 4)
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#define SPI_CSR_BITS_11_BIT (0x3u << 4)
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#define SPI_CSR_BITS_12_BIT (0x4u << 4)
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#define SPI_CSR_BITS_13_BIT (0x5u << 4)
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#define SPI_CSR_BITS_14_BIT (0x6u << 4)
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#define SPI_CSR_BITS_15_BIT (0x7u << 4)
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#define SPI_CSR_BITS_16_BIT (0x8u << 4)
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#define SPI_CSR_SCBR_Pos 8
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#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos)
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#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
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#define SPI_CSR_DLYBS_Pos 16
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#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos)
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#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
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#define SPI_CSR_DLYBCT_Pos 24
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#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos)
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#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
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/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */
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#define SPI_WPMR_WPEN (0x1u << 0)
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#define SPI_WPMR_WPKEY_Pos 8
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#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos)
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#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
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#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8)
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/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
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#define SPI_WPSR_WPVS (0x1u << 0)
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#define SPI_WPSR_WPVSRC_Pos 8
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#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos)
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/* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */
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#define SPI_VERSION_VERSION_Pos 0
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#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos)
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#define SPI_VERSION_MFN_Pos 16
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#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos)
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#endif
/* _SAMV71_SPI_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
Spi
Spi hardware registers.
Definition
component_spi.h:41
Spi::SPI_VERSION
__I uint32_t SPI_VERSION
(Spi Offset: 0xFC) Version Register
Definition
component_spi.h:56
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