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bsps
arm
atsam
include
libchip
include
samv71
component
component_dacc.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMV71_DACC_COMPONENT_
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#define _SAMV71_DACC_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__O
uint32_t DACC_CR;
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__IO
uint32_t DACC_MR;
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__IO
uint32_t DACC_TRIGR;
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__I
uint32_t Reserved1[1];
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__O
uint32_t DACC_CHER;
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__O
uint32_t DACC_CHDR;
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__I
uint32_t DACC_CHSR;
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__O
uint32_t DACC_CDR[2];
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__O
uint32_t DACC_IER;
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__O
uint32_t DACC_IDR;
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__I
uint32_t DACC_IMR;
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__I
uint32_t DACC_ISR;
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__I
uint32_t Reserved2[24];
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__IO
uint32_t DACC_ACR;
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__I
uint32_t Reserved3[19];
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__IO
uint32_t DACC_WPMR;
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__I
uint32_t DACC_WPSR;
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__I
uint32_t Reserved4[4];
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__I
uint32_t
DACC_VERSION
;
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}
Dacc
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
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#define DACC_CR_SWRST (0x1u << 0)
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/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
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#define DACC_MR_MAXS0 (0x1u << 0)
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#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0)
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#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0)
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#define DACC_MR_MAXS1 (0x1u << 1)
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#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1)
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#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1)
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#define DACC_MR_WORD (0x1u << 4)
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#define DACC_MR_WORD_DISABLED (0x0u << 4)
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#define DACC_MR_WORD_ENABLED (0x1u << 4)
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#define DACC_MR_ZERO (0x1u << 5)
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#define DACC_MR_DIFF (0x1u << 23)
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#define DACC_MR_DIFF_DISABLED (0x0u << 23)
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#define DACC_MR_DIFF_ENABLED (0x1u << 23)
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#define DACC_MR_PRESCALER_Pos 24
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#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos)
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#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))
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/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */
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#define DACC_TRIGR_TRGEN0 (0x1u << 0)
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#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0)
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#define DACC_TRIGR_TRGEN0_EN (0x1u << 0)
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#define DACC_TRIGR_TRGEN1 (0x1u << 1)
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#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1)
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#define DACC_TRIGR_TRGEN1_EN (0x1u << 1)
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#define DACC_TRIGR_TRGSEL0_Pos 4
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#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos)
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#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)))
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#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4)
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#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4)
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#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4)
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#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4)
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#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4)
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#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4)
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#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4)
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#define DACC_TRIGR_TRGSEL1_Pos 8
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#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos)
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#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)))
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#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8)
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#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8)
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#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8)
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#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8)
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#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8)
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#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8)
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#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8)
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#define DACC_TRIGR_OSR0_Pos 16
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#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos)
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#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)))
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#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16)
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#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16)
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#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16)
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#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16)
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#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16)
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#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16)
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#define DACC_TRIGR_OSR1_Pos 20
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#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos)
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#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)))
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#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20)
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#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20)
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#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20)
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#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20)
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#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20)
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#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20)
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/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
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#define DACC_CHER_CH0 (0x1u << 0)
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#define DACC_CHER_CH1 (0x1u << 1)
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/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
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#define DACC_CHDR_CH0 (0x1u << 0)
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#define DACC_CHDR_CH1 (0x1u << 1)
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/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
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#define DACC_CHSR_CH0 (0x1u << 0)
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#define DACC_CHSR_CH1 (0x1u << 1)
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#define DACC_CHSR_DACRDY0 (0x1u << 8)
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#define DACC_CHSR_DACRDY1 (0x1u << 9)
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/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */
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#define DACC_CDR_DATA0_Pos 0
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#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos)
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#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))
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#define DACC_CDR_DATA1_Pos 16
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#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos)
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#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))
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/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
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#define DACC_IER_TXRDY0 (0x1u << 0)
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#define DACC_IER_TXRDY1 (0x1u << 1)
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#define DACC_IER_EOC0 (0x1u << 4)
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#define DACC_IER_EOC1 (0x1u << 5)
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/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
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#define DACC_IDR_TXRDY0 (0x1u << 0)
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#define DACC_IDR_TXRDY1 (0x1u << 1)
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#define DACC_IDR_EOC0 (0x1u << 4)
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#define DACC_IDR_EOC1 (0x1u << 5)
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/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
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#define DACC_IMR_TXRDY0 (0x1u << 0)
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#define DACC_IMR_TXRDY1 (0x1u << 1)
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#define DACC_IMR_EOC0 (0x1u << 4)
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#define DACC_IMR_EOC1 (0x1u << 5)
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/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
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#define DACC_ISR_TXRDY0 (0x1u << 0)
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#define DACC_ISR_TXRDY1 (0x1u << 1)
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#define DACC_ISR_EOC0 (0x1u << 4)
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#define DACC_ISR_EOC1 (0x1u << 5)
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/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
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#define DACC_ACR_IBCTLCH0_Pos 0
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#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos)
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#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
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#define DACC_ACR_IBCTLCH1_Pos 2
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#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos)
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#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
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/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */
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#define DACC_WPMR_WPEN (0x1u << 0)
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#define DACC_WPMR_WPKEY_Pos 8
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#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos)
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#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
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#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8)
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/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */
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#define DACC_WPSR_WPVS (0x1u << 0)
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#define DACC_WPSR_WPVSRC_Pos 8
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#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos)
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/* -------- DACC_VERSION : (DACC Offset: 0xFC) Version Register -------- */
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#define DACC_VERSION_VERSION_Pos 0
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#define DACC_VERSION_VERSION_Msk (0xfffu << DACC_VERSION_VERSION_Pos)
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#define DACC_VERSION_MFN_Pos 16
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#define DACC_VERSION_MFN_Msk (0x7u << DACC_VERSION_MFN_Pos)
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#endif
/* _SAMV71_DACC_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
Dacc
Dacc hardware registers.
Definition
component_dacc.h:41
Dacc::DACC_VERSION
__I uint32_t DACC_VERSION
(Dacc Offset: 0xFC) Version Register
Definition
component_dacc.h:60
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