RTEMS
6.3
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bsps
arm
atsam
include
libchip
include
sams70
component
component_uart.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMS70_UART_COMPONENT_
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#define _SAMS70_UART_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__O
uint32_t UART_CR;
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__IO
uint32_t UART_MR;
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__O
uint32_t UART_IER;
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__O
uint32_t UART_IDR;
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__I
uint32_t UART_IMR;
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__I
uint32_t UART_SR;
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__I
uint32_t UART_RHR;
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__O
uint32_t UART_THR;
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__IO
uint32_t UART_BRGR;
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__IO
uint32_t UART_CMPR;
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__I
uint32_t Reserved1[47];
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__IO
uint32_t UART_WPMR;
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}
Uart
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
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#define UART_CR_RSTRX (0x1u << 2)
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#define UART_CR_RSTTX (0x1u << 3)
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#define UART_CR_RXEN (0x1u << 4)
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#define UART_CR_RXDIS (0x1u << 5)
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#define UART_CR_TXEN (0x1u << 6)
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#define UART_CR_TXDIS (0x1u << 7)
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#define UART_CR_RSTSTA (0x1u << 8)
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#define UART_CR_REQCLR (0x1u << 12)
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/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
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#define UART_MR_FILTER (0x1u << 4)
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#define UART_MR_FILTER_DISABLED (0x0u << 4)
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#define UART_MR_FILTER_ENABLED (0x1u << 4)
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#define UART_MR_PAR_Pos 9
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#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos)
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#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)))
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#define UART_MR_PAR_EVEN (0x0u << 9)
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#define UART_MR_PAR_ODD (0x1u << 9)
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#define UART_MR_PAR_SPACE (0x2u << 9)
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#define UART_MR_PAR_MARK (0x3u << 9)
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#define UART_MR_PAR_NO (0x4u << 9)
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#define UART_MR_BRSRCCK (0x1u << 12)
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#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12)
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#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12)
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#define UART_MR_CHMODE_Pos 14
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#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos)
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#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)))
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#define UART_MR_CHMODE_NORMAL (0x0u << 14)
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#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14)
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#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14)
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#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14)
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/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
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#define UART_IER_RXRDY (0x1u << 0)
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#define UART_IER_TXRDY (0x1u << 1)
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#define UART_IER_OVRE (0x1u << 5)
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#define UART_IER_FRAME (0x1u << 6)
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#define UART_IER_PARE (0x1u << 7)
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#define UART_IER_TXEMPTY (0x1u << 9)
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#define UART_IER_CMP (0x1u << 15)
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/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
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#define UART_IDR_RXRDY (0x1u << 0)
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#define UART_IDR_TXRDY (0x1u << 1)
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#define UART_IDR_OVRE (0x1u << 5)
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#define UART_IDR_FRAME (0x1u << 6)
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#define UART_IDR_PARE (0x1u << 7)
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#define UART_IDR_TXEMPTY (0x1u << 9)
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#define UART_IDR_CMP (0x1u << 15)
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/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
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#define UART_IMR_RXRDY (0x1u << 0)
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#define UART_IMR_TXRDY (0x1u << 1)
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#define UART_IMR_OVRE (0x1u << 5)
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#define UART_IMR_FRAME (0x1u << 6)
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#define UART_IMR_PARE (0x1u << 7)
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#define UART_IMR_TXEMPTY (0x1u << 9)
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#define UART_IMR_CMP (0x1u << 15)
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/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
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#define UART_SR_RXRDY (0x1u << 0)
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#define UART_SR_TXRDY (0x1u << 1)
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#define UART_SR_OVRE (0x1u << 5)
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#define UART_SR_FRAME (0x1u << 6)
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#define UART_SR_PARE (0x1u << 7)
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#define UART_SR_TXEMPTY (0x1u << 9)
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#define UART_SR_CMP (0x1u << 15)
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/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
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#define UART_RHR_RXCHR_Pos 0
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#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos)
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/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
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#define UART_THR_TXCHR_Pos 0
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#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos)
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#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
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/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
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#define UART_BRGR_CD_Pos 0
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#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos)
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#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
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/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */
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#define UART_CMPR_VAL1_Pos 0
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#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos)
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#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))
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#define UART_CMPR_CMPMODE (0x1u << 12)
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#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12)
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#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12)
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#define UART_CMPR_CMPPAR (0x1u << 14)
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#define UART_CMPR_VAL2_Pos 16
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#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos)
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#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))
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/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */
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#define UART_WPMR_WPEN (0x1u << 0)
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#define UART_WPMR_WPKEY_Pos 8
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#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos)
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#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)))
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#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8)
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#endif
/* _SAMS70_UART_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
Uart
Uart hardware registers.
Definition
component_uart.h:41
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