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bsps
arm
atsam
include
libchip
include
sams70
component
component_sdramc.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMS70_SDRAMC_COMPONENT_
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#define _SAMS70_SDRAMC_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__IO
uint32_t SDRAMC_MR;
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__IO
uint32_t SDRAMC_TR;
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__IO
uint32_t SDRAMC_CR;
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__I
uint32_t Reserved1[1];
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__IO
uint32_t SDRAMC_LPR;
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__O
uint32_t SDRAMC_IER;
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__O
uint32_t SDRAMC_IDR;
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__I
uint32_t SDRAMC_IMR;
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__I
uint32_t SDRAMC_ISR;
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__IO
uint32_t SDRAMC_MDR;
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__IO
uint32_t SDRAMC_CFR1;
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__IO
uint32_t SDRAMC_OCMS;
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__O
uint32_t SDRAMC_OCMS_KEY1;
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__O
uint32_t SDRAMC_OCMS_KEY2;
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}
Sdramc
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
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#define SDRAMC_MR_MODE_Pos 0
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#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos)
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#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos)))
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#define SDRAMC_MR_MODE_NORMAL (0x0u << 0)
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#define SDRAMC_MR_MODE_NOP (0x1u << 0)
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#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0)
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#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0)
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#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0)
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#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0)
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#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0)
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/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
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#define SDRAMC_TR_COUNT_Pos 0
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#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos)
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#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
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/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
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#define SDRAMC_CR_NC_Pos 0
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#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos)
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#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos)))
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#define SDRAMC_CR_NC_COL8 (0x0u << 0)
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#define SDRAMC_CR_NC_COL9 (0x1u << 0)
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#define SDRAMC_CR_NC_COL10 (0x2u << 0)
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#define SDRAMC_CR_NC_COL11 (0x3u << 0)
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#define SDRAMC_CR_NR_Pos 2
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#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos)
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#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos)))
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#define SDRAMC_CR_NR_ROW11 (0x0u << 2)
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#define SDRAMC_CR_NR_ROW12 (0x1u << 2)
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#define SDRAMC_CR_NR_ROW13 (0x2u << 2)
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#define SDRAMC_CR_NB (0x1u << 4)
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#define SDRAMC_CR_NB_BANK2 (0x0u << 4)
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#define SDRAMC_CR_NB_BANK4 (0x1u << 4)
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#define SDRAMC_CR_CAS_Pos 5
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#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos)
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#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos)))
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#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5)
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#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5)
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#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5)
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#define SDRAMC_CR_DBW (0x1u << 7)
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#define SDRAMC_CR_TWR_Pos 8
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#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos)
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#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
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#define SDRAMC_CR_TRC_TRFC_Pos 12
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#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos)
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#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
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#define SDRAMC_CR_TRP_Pos 16
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#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos)
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#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
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#define SDRAMC_CR_TRCD_Pos 20
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#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos)
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#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
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#define SDRAMC_CR_TRAS_Pos 24
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#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos)
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#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
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#define SDRAMC_CR_TXSR_Pos 28
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#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos)
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#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
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/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
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#define SDRAMC_LPR_LPCB_Pos 0
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#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos)
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#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos)))
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#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0)
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#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0)
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#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0)
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#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0)
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#define SDRAMC_LPR_PASR_Pos 4
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#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos)
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#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
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#define SDRAMC_LPR_TCSR_Pos 8
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#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos)
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#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
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#define SDRAMC_LPR_DS_Pos 10
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#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos)
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#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
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#define SDRAMC_LPR_TIMEOUT_Pos 12
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#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos)
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#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos)))
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#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12)
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#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12)
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#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12)
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/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
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#define SDRAMC_IER_RES (0x1u << 0)
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/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
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#define SDRAMC_IDR_RES (0x1u << 0)
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/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
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#define SDRAMC_IMR_RES (0x1u << 0)
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/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
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#define SDRAMC_ISR_RES (0x1u << 0)
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/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
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#define SDRAMC_MDR_MD_Pos 0
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#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos)
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#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos)))
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#define SDRAMC_MDR_MD_SDRAM (0x0u << 0)
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#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0)
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/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
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#define SDRAMC_CFR1_TMRD_Pos 0
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#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos)
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#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos)))
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#define SDRAMC_CFR1_UNAL (0x1u << 8)
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#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8)
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#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8)
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/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */
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#define SDRAMC_OCMS_SDR_SE (0x1u << 0)
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/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */
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#define SDRAMC_OCMS_KEY1_KEY1_Pos 0
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#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos)
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#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos)))
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/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */
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#define SDRAMC_OCMS_KEY2_KEY2_Pos 0
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#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos)
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#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos)))
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#endif
/* _SAMS70_SDRAMC_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
Sdramc
Sdramc hardware registers.
Definition
component_sdramc.h:41
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