RTEMS
6.3
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bsps
arm
atsam
include
libchip
include
sams70
component
component_aes.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMS70_AES_COMPONENT_
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#define _SAMS70_AES_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__O
uint32_t AES_CR;
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__IO
uint32_t AES_MR;
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__I
uint32_t Reserved1[2];
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__O
uint32_t AES_IER;
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__O
uint32_t AES_IDR;
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__I
uint32_t AES_IMR;
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__I
uint32_t AES_ISR;
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__O
uint32_t AES_KEYWR[8];
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__O
uint32_t AES_IDATAR[4];
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__I
uint32_t AES_ODATAR[4];
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__O
uint32_t AES_IVR[4];
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__IO
uint32_t AES_AADLENR;
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__IO
uint32_t AES_CLENR;
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__IO
uint32_t AES_GHASHR[4];
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__I
uint32_t AES_TAGR[4];
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__I
uint32_t AES_CTRR;
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__IO
uint32_t AES_GCMHR[4];
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}
Aes
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */
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#define AES_CR_START (0x1u << 0)
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#define AES_CR_SWRST (0x1u << 8)
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#define AES_CR_LOADSEED (0x1u << 16)
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/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */
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#define AES_MR_CIPHER (0x1u << 0)
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#define AES_MR_GTAGEN (0x1u << 1)
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#define AES_MR_DUALBUFF (0x1u << 3)
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#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3)
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#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3)
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#define AES_MR_PROCDLY_Pos 4
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#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos)
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#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))
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#define AES_MR_SMOD_Pos 8
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#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos)
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#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)))
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#define AES_MR_SMOD_MANUAL_START (0x0u << 8)
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#define AES_MR_SMOD_AUTO_START (0x1u << 8)
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#define AES_MR_SMOD_IDATAR0_START (0x2u << 8)
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#define AES_MR_KEYSIZE_Pos 10
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#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos)
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#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)))
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#define AES_MR_KEYSIZE_AES128 (0x0u << 10)
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#define AES_MR_KEYSIZE_AES192 (0x1u << 10)
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#define AES_MR_KEYSIZE_AES256 (0x2u << 10)
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#define AES_MR_OPMOD_Pos 12
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#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos)
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#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)))
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#define AES_MR_OPMOD_ECB (0x0u << 12)
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#define AES_MR_OPMOD_CBC (0x1u << 12)
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#define AES_MR_OPMOD_OFB (0x2u << 12)
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#define AES_MR_OPMOD_CFB (0x3u << 12)
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#define AES_MR_OPMOD_CTR (0x4u << 12)
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#define AES_MR_OPMOD_GCM (0x5u << 12)
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#define AES_MR_LOD (0x1u << 15)
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#define AES_MR_CFBS_Pos 16
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#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos)
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#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)))
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#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16)
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#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16)
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#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16)
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#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16)
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#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16)
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#define AES_MR_CKEY_Pos 20
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#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos)
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#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))
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#define AES_MR_CKEY_PASSWD (0xEu << 20)
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#define AES_MR_CMTYP1 (0x1u << 24)
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#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24)
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#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24)
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#define AES_MR_CMTYP2 (0x1u << 25)
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#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25)
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#define AES_MR_CMTYP2_PAUSE (0x1u << 25)
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#define AES_MR_CMTYP3 (0x1u << 26)
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#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26)
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#define AES_MR_CMTYP3_DUMMY (0x1u << 26)
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#define AES_MR_CMTYP4 (0x1u << 27)
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#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27)
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#define AES_MR_CMTYP4_RESTART (0x1u << 27)
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#define AES_MR_CMTYP5 (0x1u << 28)
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#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28)
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#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28)
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#define AES_MR_CMTYP6 (0x1u << 29)
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#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29)
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#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29)
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/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
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#define AES_IER_DATRDY (0x1u << 0)
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#define AES_IER_URAD (0x1u << 8)
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#define AES_IER_TAGRDY (0x1u << 16)
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/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
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#define AES_IDR_DATRDY (0x1u << 0)
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#define AES_IDR_URAD (0x1u << 8)
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#define AES_IDR_TAGRDY (0x1u << 16)
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/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
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#define AES_IMR_DATRDY (0x1u << 0)
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#define AES_IMR_URAD (0x1u << 8)
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#define AES_IMR_TAGRDY (0x1u << 16)
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/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */
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#define AES_ISR_DATRDY (0x1u << 0)
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#define AES_ISR_URAD (0x1u << 8)
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#define AES_ISR_URAT_Pos 12
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#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos)
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#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12)
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#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12)
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#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12)
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#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12)
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#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12)
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#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12)
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#define AES_ISR_TAGRDY (0x1u << 16)
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/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */
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#define AES_KEYWR_KEYW_Pos 0
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#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos)
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#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))
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/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */
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#define AES_IDATAR_IDATA_Pos 0
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#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos)
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#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))
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/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */
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#define AES_ODATAR_ODATA_Pos 0
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#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos)
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/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */
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#define AES_IVR_IV_Pos 0
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#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos)
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#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))
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/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */
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#define AES_AADLENR_AADLEN_Pos 0
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#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos)
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#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))
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/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */
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#define AES_CLENR_CLEN_Pos 0
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#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos)
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#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))
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/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */
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#define AES_GHASHR_GHASH_Pos 0
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#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos)
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#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))
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/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */
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#define AES_TAGR_TAG_Pos 0
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#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos)
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/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */
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#define AES_CTRR_CTR_Pos 0
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#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos)
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/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */
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#define AES_GCMHR_H_Pos 0
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#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos)
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#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))
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#endif
/* _SAMS70_AES_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
Aes
Aes hardware registers.
Definition
component_aes.h:41
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