RTEMS
6.3
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bsps
arm
tms570
include
bsp
ti_herc
reg_pbist.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: BSD-2-Clause */
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/* The header file is generated by make_header.py from PBIST.json */
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/* Current script's version can be found at: */
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/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
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/*
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* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
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*
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* Czech Technical University in Prague
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* Zikova 1903/4
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* 166 36 Praha 6
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* Czech Republic
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation are those
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* of the authors and should not be interpreted as representing official policies,
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* either expressed or implied, of the FreeBSD Project.
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*/
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#ifndef LIBBSP_ARM_TMS570_PBIST
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#define LIBBSP_ARM_TMS570_PBIST
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#include <
bsp/utility.h
>
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typedef
struct
{
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uint32_t DNW[88];
/*Reserved DO NOT WRITE*/
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uint32_t RAMT;
/*RAM Configuration Register*/
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uint32_t DLR;
/*Datalogger Register*/
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uint8_t reserved1 [24];
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uint32_t PACT;
/*PBIST Activate/ROM Clock Enable Register*/
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uint32_t PBISTID;
/*PBIST ID Register*/
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uint32_t OVER;
/*Override Register*/
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uint8_t reserved2 [4];
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uint32_t FSRF0;
/*Fail Status Fail Register 0*/
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uint8_t reserved3 [4];
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uint32_t FSRC0;
/*Fail Status Count Register 0*/
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uint32_t FSRC1;
/*Fail Status Count Register 1*/
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uint32_t FSRA0;
/*Fail Status Address 0 Register*/
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uint32_t FSRA1;
/*Fail Status Address 1 Register*/
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uint32_t FSRDL0;
/*Fail Status Data Register 0*/
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uint8_t reserved4 [4];
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uint32_t FSRDL1;
/*Fail Status Data Register 1*/
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uint8_t reserved5 [12];
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uint32_t ROM;
/*ROM Mask Register*/
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uint32_t ALGO;
/*ROM Algorithm Mask Register*/
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uint32_t RINFOL;
/*RAM Info Mask Lower Register*/
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uint32_t RINFOUL;
/*RAM Info Mask Lower Register*/
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}
tms570_pbist_t
;
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/*----------------------TMS570_PBIST_DNW----------------------*/
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/* field: Reserved - Do not write */
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/* Whole 32 bits */
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/*---------------------TMS570_PBIST_RAMT---------------------*/
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/* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */
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#define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31)
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#define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31)
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#define TMS570_PBIST_RAMT_RGS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
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/* field: RDS - Return Data Select. Refer Table 2-5 for information on the RDS values for each memory. */
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#define TMS570_PBIST_RAMT_RDS(val) BSP_FLD32(val,16, 23)
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#define TMS570_PBIST_RAMT_RDS_GET(reg) BSP_FLD32GET(reg,16, 23)
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#define TMS570_PBIST_RAMT_RDS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
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/* field: DWR - Data Width Register */
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#define TMS570_PBIST_RAMT_DWR(val) BSP_FLD32(val,8, 15)
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#define TMS570_PBIST_RAMT_DWR_GET(reg) BSP_FLD32GET(reg,8, 15)
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#define TMS570_PBIST_RAMT_DWR_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
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/* field: SMS - Sense Margin Select Register */
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#define TMS570_PBIST_RAMT_SMS(val) BSP_FLD32(val,6, 7)
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#define TMS570_PBIST_RAMT_SMS_GET(reg) BSP_FLD32GET(reg,6, 7)
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#define TMS570_PBIST_RAMT_SMS_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
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/* field: PLS - Pipeline Latency Select */
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#define TMS570_PBIST_RAMT_PLS(val) BSP_FLD32(val,2, 5)
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#define TMS570_PBIST_RAMT_PLS_GET(reg) BSP_FLD32GET(reg,2, 5)
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#define TMS570_PBIST_RAMT_PLS_SET(reg,val) BSP_FLD32SET(reg, val,2, 5)
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/* field: RLS - RAM Latency Select */
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#define TMS570_PBIST_RAMT_RLS(val) BSP_FLD32(val,0, 1)
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#define TMS570_PBIST_RAMT_RLS_GET(reg) BSP_FLD32GET(reg,0, 1)
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#define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
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/*----------------------TMS570_PBIST_DLR----------------------*/
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/* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */
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#define TMS570_PBIST_DLR_DLR4 BSP_BIT32(4)
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/* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */
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#define TMS570_PBIST_DLR_DLR2 BSP_BIT32(2)
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/*---------------------TMS570_PBIST_PACT---------------------*/
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/* field: PACT1 - PBIST Activate */
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#define TMS570_PBIST_PACT_PACT1 BSP_BIT32(1)
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/* field: PACT0 - ROM Clock Enable Register */
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#define TMS570_PBIST_PACT_PACT0 BSP_BIT32(0)
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/*--------------------TMS570_PBIST_PBISTID--------------------*/
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/* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */
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#define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7)
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#define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7)
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#define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
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/*---------------------TMS570_PBIST_OVER---------------------*/
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/* field: OVER0 - RINFO Override Bit */
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#define TMS570_PBIST_OVER_OVER0 BSP_BIT32(0)
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/*---------------------TMS570_PBIST_FSRF0---------------------*/
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/* field: FSRF0 - Fail Status 0. */
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#define TMS570_PBIST_FSRF0_FSRF0 BSP_BIT32(0)
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/*---------------------TMS570_PBIST_FSRC0---------------------*/
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/* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */
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#define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7)
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#define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7)
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#define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
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/*---------------------TMS570_PBIST_FSRC1---------------------*/
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/* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */
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#define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7)
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#define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7)
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#define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
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/*---------------------TMS570_PBIST_FSRA0---------------------*/
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/* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */
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#define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15)
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#define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15)
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#define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
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/*---------------------TMS570_PBIST_FSRA1---------------------*/
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/* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */
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#define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15)
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#define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15)
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#define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
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/*--------------------TMS570_PBIST_FSRDL0--------------------*/
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/* field: FSRDL1 - Failure data on port 1 */
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/* Whole 32 bits */
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/*--------------------TMS570_PBIST_FSRDL1--------------------*/
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/* field: FSRDL1 - Failure data on port 1 */
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/* Whole 32 bits */
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/*----------------------TMS570_PBIST_ROM----------------------*/
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/* field: ROM - ROM Mask */
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#define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1)
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#define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1)
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#define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
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/*---------------------TMS570_PBIST_ALGO---------------------*/
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/* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */
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/* Whole 32 bits */
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/*--------------------TMS570_PBIST_RINFOL--------------------*/
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/* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */
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/* Whole 32 bits */
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/*--------------------TMS570_PBIST_RINFOUL--------------------*/
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/* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */
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/* Whole 32 bits */
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#endif
/* LIBBSP_ARM_TMS570_PBIST */
utility.h
This header file provides utility macros for BSPs.
tms570_pbist_t
Definition
reg_pbist.h:54
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