RTEMS 6.3
Loading...
Searching...
No Matches
regs-edma.h
Go to the documentation of this file.
1
6
7/*
8 * Copyright (c) 2011 embedded brains GmbH & Co. KG
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15/*********************************************************************
16 *
17 * Copyright:
18 * Freescale Semiconductor, INC. All Rights Reserved.
19 * You are hereby granted a copyright license to use, modify, and
20 * distribute the SOFTWARE so long as this entire notice is
21 * retained without alteration in any modified and/or redistributed
22 * versions, and that such modified versions are clearly identified
23 * as such. No licenses are granted by implication, estoppel or
24 * otherwise under any patents or trademarks of Freescale
25 * Semiconductor, Inc. This software is provided on an "AS IS"
26 * basis and without warranty.
27 *
28 * To the maximum extent permitted by applicable law, Freescale
29 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
30 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
31 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
32 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
33 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
34 *
35 * To the maximum extent permitted by applicable law, IN NO EVENT
36 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
37 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
38 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
39 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
40 *
41 * Freescale Semiconductor assumes no responsibility for the
42 * maintenance and support of this software
43 *
44 ********************************************************************/
45
46#ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
47#define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
48
49#include <stdint.h>
50
51#include <bspopts.h>
52
53#ifdef __cplusplus
54extern "C" {
55#endif
56
57/****************************************************************************/
58/* MODULE : eDMA */
59/****************************************************************************/
60 struct EDMA_tag {
61 union EDMA_CR_tag {
62 uint32_t R;
63 struct {
64#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
65 uint32_t:14;
66 uint32_t CX:1;
67 uint32_t ECX:1;
68#else
69 uint32_t:16;
70#endif
71 uint32_t GRP3PRI:2;
72 uint32_t GRP2PRI:2;
73 uint32_t GRP1PRI:2;
74 uint32_t GRP0PRI:2;
75#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
76 uint32_t EMLM:1;
77 uint32_t CLM:1;
78 uint32_t HALT:1;
79 uint32_t HOE:1;
80#else
81 uint32_t:4;
82#endif
83 uint32_t ERGA:1;
84 uint32_t ERCA:1;
85 uint32_t EDBG:1;
86 uint32_t EBW:1;
87 } B;
88 } CR; /* Control Register */
89
90 union {
91 uint32_t R;
92 struct {
93 uint32_t VLD:1;
94#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
95 uint32_t:14;
96 uint32_t ECX:1;
97#else
98 uint32_t:15;
99#endif
100 uint32_t GPE:1;
101 uint32_t CPE:1;
102 uint32_t ERRCHN:6;
103 uint32_t SAE:1;
104 uint32_t SOE:1;
105 uint32_t DAE:1;
106 uint32_t DOE:1;
107 uint32_t NCE:1;
108 uint32_t SGE:1;
109 uint32_t SBE:1;
110 uint32_t DBE:1;
111 } B;
112 } ESR; /* Error Status Register */
113
114 union {
115 uint32_t R;
116 struct {
117 uint32_t ERQ63:1;
118 uint32_t ERQ62:1;
119 uint32_t ERQ61:1;
120 uint32_t ERQ60:1;
121 uint32_t ERQ59:1;
122 uint32_t ERQ58:1;
123 uint32_t ERQ57:1;
124 uint32_t ERQ56:1;
125 uint32_t ERQ55:1;
126 uint32_t ERQ54:1;
127 uint32_t ERQ53:1;
128 uint32_t ERQ52:1;
129 uint32_t ERQ51:1;
130 uint32_t ERQ50:1;
131 uint32_t ERQ49:1;
132 uint32_t ERQ48:1;
133 uint32_t ERQ47:1;
134 uint32_t ERQ46:1;
135 uint32_t ERQ45:1;
136 uint32_t ERQ44:1;
137 uint32_t ERQ43:1;
138 uint32_t ERQ42:1;
139 uint32_t ERQ41:1;
140 uint32_t ERQ40:1;
141 uint32_t ERQ39:1;
142 uint32_t ERQ38:1;
143 uint32_t ERQ37:1;
144 uint32_t ERQ36:1;
145 uint32_t ERQ35:1;
146 uint32_t ERQ34:1;
147 uint32_t ERQ33:1;
148 uint32_t ERQ32:1;
149 } B;
150 } ERQRH; /* DMA Enable Request Register High */
151
152 union {
153 uint32_t R;
154 struct {
155 uint32_t ERQ31:1;
156 uint32_t ERQ30:1;
157 uint32_t ERQ29:1;
158 uint32_t ERQ28:1;
159 uint32_t ERQ27:1;
160 uint32_t ERQ26:1;
161 uint32_t ERQ25:1;
162 uint32_t ERQ24:1;
163 uint32_t ERQ23:1;
164 uint32_t ERQ22:1;
165 uint32_t ERQ21:1;
166 uint32_t ERQ20:1;
167 uint32_t ERQ19:1;
168 uint32_t ERQ18:1;
169 uint32_t ERQ17:1;
170 uint32_t ERQ16:1;
171 uint32_t ERQ15:1;
172 uint32_t ERQ14:1;
173 uint32_t ERQ13:1;
174 uint32_t ERQ12:1;
175 uint32_t ERQ11:1;
176 uint32_t ERQ10:1;
177 uint32_t ERQ09:1;
178 uint32_t ERQ08:1;
179 uint32_t ERQ07:1;
180 uint32_t ERQ06:1;
181 uint32_t ERQ05:1;
182 uint32_t ERQ04:1;
183 uint32_t ERQ03:1;
184 uint32_t ERQ02:1;
185 uint32_t ERQ01:1;
186 uint32_t ERQ00:1;
187 } B;
188 } ERQRL; /* DMA Enable Request Register Low */
189
190 union {
191 uint32_t R;
192 struct {
193 uint32_t EEI63:1;
194 uint32_t EEI62:1;
195 uint32_t EEI61:1;
196 uint32_t EEI60:1;
197 uint32_t EEI59:1;
198 uint32_t EEI58:1;
199 uint32_t EEI57:1;
200 uint32_t EEI56:1;
201 uint32_t EEI55:1;
202 uint32_t EEI54:1;
203 uint32_t EEI53:1;
204 uint32_t EEI52:1;
205 uint32_t EEI51:1;
206 uint32_t EEI50:1;
207 uint32_t EEI49:1;
208 uint32_t EEI48:1;
209 uint32_t EEI47:1;
210 uint32_t EEI46:1;
211 uint32_t EEI45:1;
212 uint32_t EEI44:1;
213 uint32_t EEI43:1;
214 uint32_t EEI42:1;
215 uint32_t EEI41:1;
216 uint32_t EEI40:1;
217 uint32_t EEI39:1;
218 uint32_t EEI38:1;
219 uint32_t EEI37:1;
220 uint32_t EEI36:1;
221 uint32_t EEI35:1;
222 uint32_t EEI34:1;
223 uint32_t EEI33:1;
224 uint32_t EEI32:1;
225 } B;
226 } EEIRH; /* DMA Enable Error Interrupt Register High */
227
228 union {
229 uint32_t R;
230 struct {
231 uint32_t EEI31:1;
232 uint32_t EEI30:1;
233 uint32_t EEI29:1;
234 uint32_t EEI28:1;
235 uint32_t EEI27:1;
236 uint32_t EEI26:1;
237 uint32_t EEI25:1;
238 uint32_t EEI24:1;
239 uint32_t EEI23:1;
240 uint32_t EEI22:1;
241 uint32_t EEI21:1;
242 uint32_t EEI20:1;
243 uint32_t EEI19:1;
244 uint32_t EEI18:1;
245 uint32_t EEI17:1;
246 uint32_t EEI16:1;
247 uint32_t EEI15:1;
248 uint32_t EEI14:1;
249 uint32_t EEI13:1;
250 uint32_t EEI12:1;
251 uint32_t EEI11:1;
252 uint32_t EEI10:1;
253 uint32_t EEI09:1;
254 uint32_t EEI08:1;
255 uint32_t EEI07:1;
256 uint32_t EEI06:1;
257 uint32_t EEI05:1;
258 uint32_t EEI04:1;
259 uint32_t EEI03:1;
260 uint32_t EEI02:1;
261 uint32_t EEI01:1;
262 uint32_t EEI00:1;
263 } B;
264 } EEIRL; /* DMA Enable Error Interrupt Register Low */
265
266 union { /* DMA Set Enable Request Register */
267 uint8_t R;
268 struct {
269 uint8_t NOP:1;
270 uint8_t SERQ:7;
271 } B;
272 } SERQR;
273
274 union { /* DMA Clear Enable Request Register */
275 uint8_t R;
276 struct {
277 uint8_t NOP:1;
278 uint8_t CERQ:7;
279 } B;
280 } CERQR;
281
282 union { /* DMA Set Enable Error Interrupt Register */
283 uint8_t R;
284 struct {
285 uint8_t NOP:1;
286 uint8_t SEEI:7;
287 } B;
288 } SEEIR;
289
290 union { /* DMA Clear Enable Error Interrupt Register */
291 uint8_t R;
292 struct {
293 uint8_t NOP:1;
294 uint8_t CEEI:7;
295 } B;
296 } CEEIR;
297
298 union { /* DMA Clear Interrupt Request Register */
299 uint8_t R;
300 struct {
301 uint8_t NOP:1;
302 uint8_t CINT:7;
303 } B;
304 } CIRQR;
305
306 union { /* DMA Clear error Register */
307 uint8_t R;
308 struct {
309 uint8_t NOP:1;
310 uint8_t CERR:7;
311 } B;
312 } CER;
313
314 union { /* Set Start Bit Register */
315 uint8_t R;
316 struct {
317 uint8_t NOP:1;
318 uint8_t SSB:7;
319 } B;
320 } SSBR;
321
322 union { /* Clear Done Status Bit Register */
323 uint8_t R;
324 struct {
325 uint8_t NOP:1;
326 uint8_t CDSB:7;
327 } B;
328 } CDSBR;
329
330 union {
331 uint32_t R;
332 struct {
333 uint32_t INT63:1;
334 uint32_t INT62:1;
335 uint32_t INT61:1;
336 uint32_t INT60:1;
337 uint32_t INT59:1;
338 uint32_t INT58:1;
339 uint32_t INT57:1;
340 uint32_t INT56:1;
341 uint32_t INT55:1;
342 uint32_t INT54:1;
343 uint32_t INT53:1;
344 uint32_t INT52:1;
345 uint32_t INT51:1;
346 uint32_t INT50:1;
347 uint32_t INT49:1;
348 uint32_t INT48:1;
349 uint32_t INT47:1;
350 uint32_t INT46:1;
351 uint32_t INT45:1;
352 uint32_t INT44:1;
353 uint32_t INT43:1;
354 uint32_t INT42:1;
355 uint32_t INT41:1;
356 uint32_t INT40:1;
357 uint32_t INT39:1;
358 uint32_t INT38:1;
359 uint32_t INT37:1;
360 uint32_t INT36:1;
361 uint32_t INT35:1;
362 uint32_t INT34:1;
363 uint32_t INT33:1;
364 uint32_t INT32:1;
365 } B;
366 } IRQRH; /* DMA Interrupt Request High */
367
368 union {
369 uint32_t R;
370 struct {
371 uint32_t INT31:1;
372 uint32_t INT30:1;
373 uint32_t INT29:1;
374 uint32_t INT28:1;
375 uint32_t INT27:1;
376 uint32_t INT26:1;
377 uint32_t INT25:1;
378 uint32_t INT24:1;
379 uint32_t INT23:1;
380 uint32_t INT22:1;
381 uint32_t INT21:1;
382 uint32_t INT20:1;
383 uint32_t INT19:1;
384 uint32_t INT18:1;
385 uint32_t INT17:1;
386 uint32_t INT16:1;
387 uint32_t INT15:1;
388 uint32_t INT14:1;
389 uint32_t INT13:1;
390 uint32_t INT12:1;
391 uint32_t INT11:1;
392 uint32_t INT10:1;
393 uint32_t INT09:1;
394 uint32_t INT08:1;
395 uint32_t INT07:1;
396 uint32_t INT06:1;
397 uint32_t INT05:1;
398 uint32_t INT04:1;
399 uint32_t INT03:1;
400 uint32_t INT02:1;
401 uint32_t INT01:1;
402 uint32_t INT00:1;
403 } B;
404 } IRQRL; /* DMA Interrupt Request Low */
405
406 union {
407 uint32_t R;
408 struct {
409 uint32_t ERR63:1;
410 uint32_t ERR62:1;
411 uint32_t ERR61:1;
412 uint32_t ERR60:1;
413 uint32_t ERR59:1;
414 uint32_t ERR58:1;
415 uint32_t ERR57:1;
416 uint32_t ERR56:1;
417 uint32_t ERR55:1;
418 uint32_t ERR54:1;
419 uint32_t ERR53:1;
420 uint32_t ERR52:1;
421 uint32_t ERR51:1;
422 uint32_t ERR50:1;
423 uint32_t ERR49:1;
424 uint32_t ERR48:1;
425 uint32_t ERR47:1;
426 uint32_t ERR46:1;
427 uint32_t ERR45:1;
428 uint32_t ERR44:1;
429 uint32_t ERR43:1;
430 uint32_t ERR42:1;
431 uint32_t ERR41:1;
432 uint32_t ERR40:1;
433 uint32_t ERR39:1;
434 uint32_t ERR38:1;
435 uint32_t ERR37:1;
436 uint32_t ERR36:1;
437 uint32_t ERR35:1;
438 uint32_t ERR34:1;
439 uint32_t ERR33:1;
440 uint32_t ERR32:1;
441 } B;
442 } ERH; /* DMA Error High */
443
444 union {
445 uint32_t R;
446 struct {
447 uint32_t ERR31:1;
448 uint32_t ERR30:1;
449 uint32_t ERR29:1;
450 uint32_t ERR28:1;
451 uint32_t ERR27:1;
452 uint32_t ERR26:1;
453 uint32_t ERR25:1;
454 uint32_t ERR24:1;
455 uint32_t ERR23:1;
456 uint32_t ERR22:1;
457 uint32_t ERR21:1;
458 uint32_t ERR20:1;
459 uint32_t ERR19:1;
460 uint32_t ERR18:1;
461 uint32_t ERR17:1;
462 uint32_t ERR16:1;
463 uint32_t ERR15:1;
464 uint32_t ERR14:1;
465 uint32_t ERR13:1;
466 uint32_t ERR12:1;
467 uint32_t ERR11:1;
468 uint32_t ERR10:1;
469 uint32_t ERR09:1;
470 uint32_t ERR08:1;
471 uint32_t ERR07:1;
472 uint32_t ERR06:1;
473 uint32_t ERR05:1;
474 uint32_t ERR04:1;
475 uint32_t ERR03:1;
476 uint32_t ERR02:1;
477 uint32_t ERR01:1;
478 uint32_t ERR00:1;
479 } B;
480 } ERL; /* DMA Error Low */
481
482#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
483 union { /* hardware request status high */
484 uint32_t R;
485 struct {
486 uint32_t HRS63:1;
487 uint32_t HRS62:1;
488 uint32_t HRS61:1;
489 uint32_t HRS60:1;
490 uint32_t HRS59:1;
491 uint32_t HRS58:1;
492 uint32_t HRS57:1;
493 uint32_t HRS56:1;
494 uint32_t HRS55:1;
495 uint32_t HRS54:1;
496 uint32_t HRS53:1;
497 uint32_t HRS52:1;
498 uint32_t HRS51:1;
499 uint32_t HRS50:1;
500 uint32_t HRS49:1;
501 uint32_t HRS48:1;
502 uint32_t HRS47:1;
503 uint32_t HRS46:1;
504 uint32_t HRS45:1;
505 uint32_t HRS44:1;
506 uint32_t HRS43:1;
507 uint32_t HRS42:1;
508 uint32_t HRS41:1;
509 uint32_t HRS40:1;
510 uint32_t HRS39:1;
511 uint32_t HRS38:1;
512 uint32_t HRS37:1;
513 uint32_t HRS36:1;
514 uint32_t HRS35:1;
515 uint32_t HRS34:1;
516 uint32_t HRS33:1;
517 uint32_t HRS32:1;
518 } B;
519 } HRSH;
520
521 union { /* hardware request status low */
522 uint32_t R;
523 struct {
524 uint32_t HRS31:1;
525 uint32_t HRS30:1;
526 uint32_t HRS29:1;
527 uint32_t HRS28:1;
528 uint32_t HRS27:1;
529 uint32_t HRS26:1;
530 uint32_t HRS25:1;
531 uint32_t HRS24:1;
532 uint32_t HRS23:1;
533 uint32_t HRS22:1;
534 uint32_t HRS21:1;
535 uint32_t HRS20:1;
536 uint32_t HRS19:1;
537 uint32_t HRS18:1;
538 uint32_t HRS17:1;
539 uint32_t HRS16:1;
540 uint32_t HRS15:1;
541 uint32_t HRS14:1;
542 uint32_t HRS13:1;
543 uint32_t HRS12:1;
544 uint32_t HRS11:1;
545 uint32_t HRS10:1;
546 uint32_t HRS09:1;
547 uint32_t HRS08:1;
548 uint32_t HRS07:1;
549 uint32_t HRS06:1;
550 uint32_t HRS05:1;
551 uint32_t HRS04:1;
552 uint32_t HRS03:1;
553 uint32_t HRS02:1;
554 uint32_t HRS01:1;
555 uint32_t HRS00:1;
556 } B;
557 } HRSL;
558
559 uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
560#else
561 uint32_t edma_reserved1[52];
562#endif
563
564 union {
565 uint8_t R;
566 struct {
567 uint8_t ECP:1;
568#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
569 uint8_t DPA:1;
570#else
571 uint8_t:1;
572#endif
573 uint8_t GRPPRI:2;
574 uint8_t CHPRI:4;
575 } B;
576 } CPR[64];
577
578 uint32_t edma_reserved2[944];
579
580/****************************************************************************/
581/* DMA2 Transfer Control Descriptor */
582/****************************************************************************/
583 struct tcd_t {
584 uint32_t SADDR; /* source address */
585
586 /* Source and destination fields */
587 union tcd_SDF_tag {
588 uint32_t R;
589 struct {
590 uint16_t SMOD:5; /* source address modulo */
591 uint16_t SSIZE:3; /* source transfer size */
592 uint16_t DMOD:5; /* destination address modulo */
593 uint16_t DSIZE:3; /* destination transfer size */
594 int16_t SOFF; /* signed source address offset */
595 } B;
596 } SDF;
597
598 uint32_t NBYTES; /* inner (“minor”) byte count */
599
600 int32_t SLAST; /* last destination address adjustment, or
601 scatter/gather address (if e_sg = 1) */
602
603 uint32_t DADDR; /* destination address */
604
605 /* CITER and destination fields */
606 union tcd_CDF_tag {
607 uint32_t R;
608 struct {
609 uint16_t CITERE_LINK:1;
610 uint16_t CITER:15;
611 int16_t DOFF; /* signed destination address offset */
612 } B;
613 struct {
614 uint16_t CITERE_LINK:1;
615 uint16_t CITERLINKCH:6;
616 uint16_t CITER:9;
617 int16_t DOFF;
618 } B_ALT;
619 struct {
620 uint16_t CITER;
621 int16_t DOFF;
622 } B_NOLINK;
623 } CDF;
624
625 int32_t DLAST_SGA;
626
627 /* BITER and misc fields */
628 union tcd_BMF_tag {
629 uint32_t R;
630 struct {
631 uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */
632 uint32_t BITER:15;
633 uint32_t BWC:2; /* bandwidth control */
634 uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */
635 uint32_t DONE:1; /* channel done */
636 uint32_t ACTIVE:1; /* channel active */
637 uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */
638 uint32_t E_SG:1; /* enable scatter/gather descriptor */
639 uint32_t D_REQ:1; /* disable ipd_req when done */
640 uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
641 uint32_t INT_MAJ:1; /* interrupt on major loop completion */
642 uint32_t START:1; /* explicit channel start */
643 } B;
644 struct {
645 uint32_t BITERE_LINK:1;
646 uint32_t BITERLINKCH:6;
647 uint32_t BITER:9;
648 uint32_t BWC:2;
649 uint32_t MAJORLINKCH:6;
650 uint32_t DONE:1;
651 uint32_t ACTIVE:1;
652 uint32_t MAJORE_LINK:1;
653 uint32_t E_SG:1;
654 uint32_t D_REQ:1;
655 uint32_t INT_HALF:1;
656 uint32_t INT_MAJ:1;
657 uint32_t START:1;
658 } B_ALT;
659 struct {
660 uint16_t BITER;
661 uint16_t BWC:2;
662 uint16_t MAJORLINKCH:6;
663 uint16_t DONE:1;
664 uint16_t ACTIVE:1;
665 uint16_t MAJORE_LINK:1;
666 uint16_t E_SG:1;
667 uint16_t D_REQ:1;
668 uint16_t INT_HALF:1;
669 uint16_t INT_MAJ:1;
670 uint16_t START:1;
671 } B_NOLINK;
672 } BMF;
673 } TCD[64]; /* transfer_control_descriptor */
674 };
675
676#ifndef __cplusplus
677 static const struct tcd_t EDMA_TCD_DEFAULT = {
678 .SADDR = 0,
679 .SDF = { .R = 0 },
680 .NBYTES = 0,
681 .SLAST = 0,
682 .DADDR = 0,
683 .CDF = { .R = 0 },
684 .DLAST_SGA = 0,
685 .BMF = { .R = 0 }
686 };
687#endif /* __cplusplus */
688
689#define EDMA_TCD_BITER_MASK 0x7fff
690
691#define EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1)
692
693#define EDMA_TCD_BITER_LINKED_MASK 0x1ff
694
695#define EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1)
696
697#define EDMA_TCD_LINK_AND_BITER(link, biter) \
698 (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK))
699
700#ifdef __cplusplus
701}
702#endif /* __cplusplus */
703
704#endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */
EDMA_tag::tcd_t
Definition regs-edma.h:583
EDMA_tag
Definition regs-edma.h:60
EDMA_tag::EDMA_CR_tag
Definition regs-edma.h:61
EDMA_tag::tcd_t::tcd_BMF_tag
Definition regs-edma.h:628
EDMA_tag::tcd_t::tcd_CDF_tag
Definition regs-edma.h:606
EDMA_tag::tcd_t::tcd_SDF_tag
Definition regs-edma.h:587
Generated by doxygen 1.18.0