RTEMS
6.3
Toggle main menu visibility
Loading...
Searching...
No Matches
cpukit
score
cpu
powerpc
include
rtems
powerpc
registers.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: BSD-2-Clause */
2
12
13
/*
14
* COPYRIGHT (C) 1999 Eric Valette (valette@crf.canon.fr)
15
* Canon Centre Recherche France.
16
*
17
* Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
18
* Surrey Satellite Technology Limited
19
*
20
*
21
* Redistribution and use in source and binary forms, with or without
22
* modification, are permitted provided that the following conditions
23
* are met:
24
* 1. Redistributions of source code must retain the above copyright
25
* notice, this list of conditions and the following disclaimer.
26
* 2. Redistributions in binary form must reproduce the above copyright
27
* notice, this list of conditions and the following disclaimer in the
28
* documentation and/or other materials provided with the distribution.
29
*
30
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
34
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40
* POSSIBILITY OF SUCH DAMAGE.
41
*/
42
43
#ifndef _RTEMS_POWERPC_REGISTERS_H
44
#define _RTEMS_POWERPC_REGISTERS_H
45
46
/* Bit encodings for Machine State Register (MSR) */
47
#define MSR_CM (1<<31)
/* Computation mode */
48
#define MSR_GS (1<<28)
/* Guest state */
49
#define MSR_UCLE (1<<26)
/* User-mode cache lock enable (e500) */
50
#define MSR_VE (1<<25)
/* Alti-Vec enable (7400+) */
51
#define MSR_SPE (1<<25)
/* SPE enable (e500) */
52
#define MSR_AP (1<<25)
/* Auxiliary processor available */
53
#define MSR_APE (1<<19)
/* APU exception enable */
54
#define MSR_POW (1<<18)
/* Enable Power Management */
55
#define MSR_WE (1<<18)
/* Wait state enable (e500, 4xx) */
56
#define MSR_TGPR (1<<17)
/* TLB Update registers in use */
57
#define MSR_CE (1<<17)
/* BookE critical interrupt */
58
#define MSR_ILE (1<<16)
/* Interrupt Little-Endian enable */
59
#define MSR_EE (1<<15)
/* External Interrupt enable */
60
#define MSR_PR (1<<14)
/* Supervisor/User privilege */
61
#define MSR_FP (1<<13)
/* Floating Point enable */
62
#define MSR_ME (1<<12)
/* Machine Check enable */
63
#define MSR_FE0 (1<<11)
/* Floating Exception mode 0 */
64
#define MSR_SE (1<<10)
/* Single Step */
65
#define MSR_UBLE (1<<10)
/* User-mode BTB lock enable (e500) */
66
#define MSR_DWE (1<<10)
/* Debug wait enable (4xx) */
67
#define MSR_BE (1<<9)
/* Branch Trace */
68
#define MSR_DE (1<<9)
/* BookE debug exception */
69
#define MSR_FE1 (1<<8)
/* Floating Exception mode 1 */
70
#define MSR_E300_CE (1<<7)
/* e300 critical interrupt */
71
#define MSR_IP (1<<6)
/* Exception prefix 0x000/0xFFF */
72
#define MSR_IR (1<<5)
/* Instruction MMU enable */
73
#define MSR_DR (1<<4)
/* Data MMU enable */
74
#define MSR_IS (1<<5)
/* Instruction address space */
75
#define MSR_DS (1<<4)
/* Data address space */
76
#define MSR_PMM (1<<2)
/* Performance monitor mark */
77
#define MSR_RI (1<<1)
/* Recoverable Exception */
78
#define MSR_LE (1<<0)
/* Little-Endian enable */
79
80
/* Bit encodings for Hardware Implementation Register (HID0)
81
on PowerPC 603, 604, etc. processors (not 601). */
82
83
/* WARNING: HID0/HID1 are *truely* implementation dependent!
84
* you *cannot* rely on the same bits to be present,
85
* at the same place or even in the same register
86
* on different CPU familys.
87
* E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the
88
* on the 7450s. IFFT is XBSEN on 7450 and so on...
89
*/
90
#define HID0_EMCP (1<<31)
/* Enable Machine Check pin */
91
#define HID0_EBA (1<<29)
/* Enable Bus Address Parity */
92
#define HID0_EBD (1<<28)
/* Enable Bus Data Parity */
93
#define HID0_SBCLK (1<<27)
94
#define HID0_TBEN (1<<26)
/* 7455:this bit must be set
95
* and TBEN signal must be asserted
96
* to enable the time base and
97
* decrementer.
98
*/
99
#define HID0_EICE (1<<26)
100
#define HID0_ECLK (1<<25)
101
#define HID0_PAR (1<<24)
102
#define HID0_DOZE (1<<23)
103
/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !! */
104
#define HID0_7455_HIGH_BAT_EN (1<<23)
105
106
#define HID0_NAP (1<<22)
107
#define HID0_SLEEP (1<<21)
108
#define HID0_DPM (1<<20)
109
#define HID0_ICE (1<<15)
/* Instruction Cache Enable */
110
#define HID0_DCE (1<<14)
/* Data Cache Enable */
111
#define HID0_ILOCK (1<<13)
/* Instruction Cache Lock */
112
#define HID0_DLOCK (1<<12)
/* Data Cache Lock */
113
#define HID0_ICFI (1<<11)
/* Instruction Cache Flash Invalidate */
114
#define HID0_DCI (1<<10)
/* Data Cache Invalidate */
115
/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */
116
#define HID0_7455_XBSEN (1<<8)
117
#define HID0_SIED (1<<7)
/* Serial Instruction Execution [Disable] */
118
#define HID0_BTIC (1<<5)
/* Branch Target Instruction Cache [Enable] */
119
/* S.K. Feng 10/03, added for MPC7455 */
120
#define HID0_LRSTK (1<<4)
/* Link register stack enable (7455) */
121
#define HID0_FOLD (1<<3)
/* Branch folding enable (7455) */
122
123
#define HID0_BHTE (1<<2)
/* Branch History Table Enable */
124
#define HID0_BTCD (1<<1)
/* Branch target cache disable */
125
126
/* fpscr settings */
127
#define FPSCR_FX (1<<31)
128
#define FPSCR_FEX (1<<30)
129
130
#define _MACH_prep 1
131
#define _MACH_Pmac 2
/* pmac or pmac clone (non-chrp) */
132
#define _MACH_chrp 4
/* chrp machine */
133
#define _MACH_mbx 8
/* Motorola MBX board */
134
#define _MACH_apus 16
/* amiga with phase5 powerup */
135
#define _MACH_fads 32
/* Motorola FADS board */
136
137
/* see residual.h for these */
138
#define _PREP_Motorola 0x01
/* motorola prep */
139
#define _PREP_Firm 0x02
/* firmworks prep */
140
#define _PREP_IBM 0x00
/* ibm prep */
141
#define _PREP_Bull 0x03
/* bull prep */
142
143
/* these are arbitrary */
144
#define _CHRP_Motorola 0x04
/* motorola chrp, the cobra */
145
#define _CHRP_IBM 0x05
/* IBM chrp, the longtrail and longtrail 2 */
146
147
#define _GLOBAL(n)\
148
.globl n;\
149
n:
150
151
#define TBRU 269
/* Time base Upper/Lower (Reading) */
152
#define TBRL 268
153
#define TBWU 285
/* Time base Upper/Lower (Writing) */
154
#define TBWL 284
155
#define PPC_XER 1
156
#define PPC_LR 8
157
#define PPC_CTR 9
158
#define HID0 1008
/* Hardware Implementation 0 */
159
#define HID1 1009
/* Hardware Implementation 1 */
160
#define HID2 1011
/* Hardware Implementation 2 */
161
#define DABR 1013
/* Data Access Breakpoint */
162
#define PPC_PVR 287
/* Processor Version */
163
#define IBAT0U 528
/* Instruction BAT #0 Upper/Lower */
164
#define IBAT0L 529
165
#define IBAT1U 530
/* Instruction BAT #1 Upper/Lower */
166
#define IBAT1L 531
167
#define IBAT2U 532
/* Instruction BAT #2 Upper/Lower */
168
#define IBAT2L 533
169
#define IBAT3U 534
/* Instruction BAT #3 Upper/Lower */
170
#define IBAT3L 535
171
172
/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
173
#define IBAT4U 560
/* Instruction BAT #4 Upper/Lower */
174
#define IBAT4L 561
175
#define IBAT5U 562
/* Instruction BAT #5 Upper/Lower */
176
#define IBAT5L 563
177
#define IBAT6U 564
/* Instruction BAT #6 Upper/Lower */
178
#define IBAT6L 565
179
#define IBAT7U 566
/* Instruction BAT #7 Upper/Lower */
180
#define IBAT7L 567
181
182
#define DBAT0U 536
/* Data BAT #0 Upper/Lower */
183
#define DBAT0L 537
184
#define DBAT1U 538
/* Data BAT #1 Upper/Lower */
185
#define DBAT1L 539
186
#define DBAT2U 540
/* Data BAT #2 Upper/Lower */
187
#define DBAT2L 541
188
#define DBAT3U 542
/* Data BAT #3 Upper/Lower */
189
#define DBAT3L 543
190
191
/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
192
#define DBAT4U 568
/* Instruction BAT #4 Upper/Lower */
193
#define DBAT4L 569
194
#define DBAT5U 570
/* Instruction BAT #5 Upper/Lower */
195
#define DBAT5L 571
196
#define DBAT6U 572
/* Instruction BAT #6 Upper/Lower */
197
#define DBAT6L 573
198
#define DBAT7U 574
/* Instruction BAT #7 Upper/Lower */
199
#define DBAT7L 575
200
201
#define DMISS 976
/* TLB Lookup/Refresh registers */
202
#define DCMP 977
203
#define HASH1 978
204
#define HASH2 979
205
#define IMISS 980
206
#define ICMP 981
207
#define PPC_RPA 982
208
#define SDR1 25
/* MMU hash base register */
209
#define PPC_DAR 19
/* Data Address Register */
210
#define DEAR_BOOKE 61
211
#define DEAR_405 981
212
#define SPR0 272
/* Supervisor Private Registers */
213
#define SPRG0 272
214
#define SPR1 273
215
#define SPRG1 273
216
#define SPR2 274
217
#define SPRG2 274
218
#define SPR3 275
219
#define SPRG3 275
220
#define SPRG4 276
221
#define SPRG5 277
222
#define SPRG6 278
223
#define SPRG7 279
224
#define USPRG0 256
225
#define DSISR 18
226
#define SRR0 26
/* Saved Registers (exception) */
227
#define SRR1 27
228
#define IABR 1010
/* Instruction Address Breakpoint */
229
#define PPC_DEC 22
/* Decrementer */
230
#define PPC_EAR 282
/* External Address Register */
231
232
#define MSSCR0 1014
/* Memory Subsystem Control Register */
233
234
#define L2CR 1017
/* PPC 750 and 74xx L2 control register */
235
236
#define L2CR_L2E (1<<31)
/* enable */
237
#define L2CR_L2I (1<<21)
/* global invalidate */
238
239
/* watch out L2IO and L2DO are different between 745x and 7400/7410 */
240
/* Oddly, the following L2CR bit defintions in 745x
241
* is different from that of 7400 and 7410.
242
* Though not used in 7400 and 7410, it is appeded with _745x just
243
* to be clarified.
244
*/
245
#define L2CR_L2IO_745x 0x100000
/* (1<<20) L2 Instruction-Only */
246
#define L2CR_L2DO_745x 0x10000
/* (1<<16) L2 Data-Only */
247
#define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x)
248
#define L2CR_L3OH0 0x00080000
/* 12:L3 output hold 0 */
249
250
#define L3CR 1018
/* PPC 7450/7455 L3 control register */
251
#define L3CR_L3IO_745x 0x400000
/* (1<<22) L3 Instruction-Only */
252
#define L3CR_L3DO_745x 0x40
/* (1<<6) L3 Data-Only */
253
254
#define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x)
255
256
#define L3CR_RESERVED 0x0438003a
/* Reserved bits in L3CR */
257
#define L3CR_L3E 0x80000000
/* 0: L3 enable */
258
#define L3CR_L3PE 0x40000000
/* 1: L3 data parity checking enable */
259
#define L3CR_L3APE 0x20000000
/* 2: L3 address parity checking enable */
260
#define L3CR_L3SIZ 0x10000000
/* 3: L3 size (0=1MB, 1=2MB) */
261
#define L3SIZ_1M 0x00000000
262
#define L3SIZ_2M 0x10000000
263
#define L3CR_L3CLKEN 0x08000000
/* 4: Enables the L3_CLK[0:1] signals */
264
#define L3CR_L3CLK 0x03800000
/* 6-8: L3 clock ratio */
265
#define L3CLK_60 0x00000000
/* core clock / 6 */
266
#define L3CLK_20 0x01000000
/* / 2 */
267
#define L3CLK_25 0x01800000
/* / 2.5 */
268
#define L3CLK_30 0x02000000
/* / 3 */
269
#define L3CLK_35 0x02800000
/* / 3.5 */
270
#define L3CLK_40 0x03000000
/* / 4 */
271
#define L3CLK_50 0x03800000
/* / 5 */
272
#define L3CR_L3IO 0x00400000
/* 9: L3 instruction-only mode */
273
#define L3CR_L3SPO 0x00040000
/* 13: L3 sample point override */
274
#define L3CR_L3CKSP 0x00030000
/* 14-15: L3 clock sample point */
275
#define L3CKSP_2 0x00000000
/* 2 clocks */
276
#define L3CKSP_3 0x00010000
/* 3 clocks */
277
#define L3CKSP_4 0x00020000
/* 4 clocks */
278
#define L3CKSP_5 0x00030000
/* 5 clocks */
279
#define L3CR_L3PSP 0x0000e000
/* 16-18: L3 P-clock sample point */
280
#define L3PSP_0 0x00000000
/* 0 clocks */
281
#define L3PSP_1 0x00002000
/* 1 clocks */
282
#define L3PSP_2 0x00004000
/* 2 clocks */
283
#define L3PSP_3 0x00006000
/* 3 clocks */
284
#define L3PSP_4 0x00008000
/* 4 clocks */
285
#define L3PSP_5 0x0000a000
/* 5 clocks */
286
#define L3CR_L3REP 0x00001000
/* 19: L3 replacement algorithm (0=default, 1=alternate) */
287
#define L3CR_L3HWF 0x00000800
/* 20: L3 hardware flush */
288
#define L3CR_L3I 0x00000400
/* 21: L3 global invaregisters.h.orig
289
lidate */
290
#define L3CR_L3RT 0x00000300
/* 22-23: L3 SRAM type */
291
#define L3RT_MSUG2_DDR 0x00000000
/* MSUG2 DDR SRAM */
292
#define L3RT_PIPELINE_LATE 0x00000100
/* Pipelined (register-register) synchronous late-write SRAM */
293
#define L3RT_PB2_SRAM 0x00000300
/* PB2 SRAM */
294
#define L3CR_L3NIRCA 0x00000080
/* 24: L3 non-integer ratios clock adjustment for the SRAM */
295
#define L3CR_L3DO 0x00000040
/* 25: L3 data-only mode */
296
#define L3CR_PMEN 0x00000004
/* 29: Private memory enable */
297
#define L3CR_PMSIZ 0x00000004
/* 31: Private memory size (0=1MB, 1=2MB) */
298
299
#define THRM1 1020
300
#define THRM2 1021
301
#define THRM3 1022
302
#define THRM1_TIN (1<<(31-0))
303
#define THRM1_TIV (1<<(31-1))
304
#define THRM1_THRES (0x7f<<(31-8))
305
#define THRM1_TID (1<<(31-29))
306
#define THRM1_TIE (1<<(31-30))
307
#define THRM1_V (1<<(31-31))
308
#define THRM3_SITV (0x1fff << (31-30))
309
#define THRM3_E (1<<(31-31))
310
311
/* Segment Registers */
312
#define PPC_SR0 0
313
#define PPC_SR1 1
314
#define PPC_SR2 2
315
#define PPC_SR3 3
316
#define PPC_SR4 4
317
#define PPC_SR5 5
318
#define PPC_SR6 6
319
#define PPC_SR7 7
320
#define PPC_SR8 8
321
#define PPC_SR9 9
322
#define PPC_SR10 10
323
#define PPC_SR11 11
324
#define PPC_SR12 12
325
#define PPC_SR13 13
326
#define PPC_SR14 14
327
#define PPC_SR15 15
328
329
#define BOOKE_DECAR 54
330
331
#define PPC405_MCSR 0x23C
332
#define PPC405_ESR 0x3D4
333
#define PPC405_DEAR 0x3D5
334
#define BOOKE_DEAR 61
335
336
#define PPC405_TSR 0x3D8
337
#define BOOKE_TSR 336
338
#define BOOKE_TSR_ENW (1<<31)
339
#define BOOKE_TSR_WIS (1<<30)
340
#define BOOKE_TSR_DIS (1<<27)
341
#define BOOKE_TSR_FIS (1<<26)
342
343
#define PPC405_TCR 0x3DA
344
#define BOOKE_TCR 340
345
#define BOOKE_TCR_WP(x) (((x)&3)<<30)
346
#define BOOKE_TCR_WP_MASK (3<<30)
347
#define BOOKE_TCR_WRC(x) (((x)&3)<<28)
348
#define BOOKE_TCR_WRC_MASK (3<<28)
349
#define BOOKE_TCR_WIE (1<<27)
350
#define BOOKE_TCR_DIE (1<<26)
351
#define BOOKE_TCR_FP(x) (((x)&3)<<24)
352
#define BOOKE_TCR_FIE (1<<23)
353
#define BOOKE_TCR_ARE (1<<22)
354
#define BOOKE_TCR_WPEXT(x) (((x)&0xf)<<17)
355
#define BOOKE_TCR_WPEXT_MASK (0xf<<17)
356
#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13)
357
#define BOOKE_TCR_FPEXT_MASK (0xf<<13)
358
359
#define BOOKE_PID 48
/* Process ID */
360
#define BOOKE_CSRR0 58
/* Critical Save/Restore Register 0 */
361
#define BOOKE_CSRR1 59
/* Critical Save/Restore Register 1 */
362
#define BOOKE_ESR 62
/* Exception Syndrome Register */
363
#define BOOKE_IVPR 63
/* Interrupt Vector Prefix Register */
364
#define BOOKE_SPRG4_W 260
/* Special Purpose Register General 4 (WO) */
365
#define BOOKE_SPRG5_W 261
/* Special Purpose Register General 5 (WO) */
366
#define BOOKE_SPRG6_W 262
/* Special Purpose Register General 6 (WO) */
367
#define BOOKE_SPRG7_W 263
/* Special Purpose Register General 7 (WO) */
368
#define BOOKE_PIR 286
/* Processor ID Register */
369
#define BOOKE_DBSR 304
/* Debug Status Register */
370
371
#define BOOKE_EPCR 307
/* Embedded Processor Control Register */
372
#define BOOKE_EPCR_EXTGS (1 << 31)
373
#define BOOKE_EPCR_DTLBGS (1 << 30)
374
#define BOOKE_EPCR_ITLBGS (1 << 29)
375
#define BOOKE_EPCR_DSIGS (1 << 28)
376
#define BOOKE_EPCR_ISIGS (1 << 27)
377
#define BOOKE_EPCR_DUVD (1 << 26)
378
#define BOOKE_EPCR_ICM (1 << 25)
379
#define BOOKE_EPCR_GICM (1 << 24)
380
#define BOOKE_EPCR_DGTMI (1 << 23)
381
#define BOOKE_EPCR_DMIUH (1 << 22)
382
#define BOOKE_EPCR_PMGS (1 << 21)
383
384
#define BOOKE_DBCR0 308
/* Debug Control Register 0 */
385
#define BOOKE_DBCR1 309
/* Debug Control Register 1 */
386
#define BOOKE_DBCR2 310
/* Debug Control Register 2 */
387
#define BOOKE_IAC1 312
/* Instruction Address Compare 1 */
388
#define BOOKE_IAC2 313
/* Instruction Address Compare 2 */
389
#define BOOKE_IAC3 314
/* Instruction Address Compare 3 */
390
#define BOOKE_IAC4 315
/* Instruction Address Compare 4 */
391
#define BOOKE_DAC1 316
/* Data Address Compare 1 */
392
#define BOOKE_DAC2 317
/* Data Address Compare 2 */
393
#define BOOKE_DVC1 318
/* Data Value Compare 1 */
394
#define BOOKE_DVC2 319
/* Data Value Compare 2 */
395
#define BOOKE_GSRR0 378
/* Guest Save/Restore Register 0 */
396
#define BOOKE_GSRR1 379
/* Guest Save/Restore Register 1 */
397
#define BOOKE_GEPR 380
/* Guest External Proxy Register */
398
#define BOOKE_GDEAR 381
/* Guest Data Exception Address Register */
399
#define BOOKE_GPIR 382
/* Guest Processor ID Register */
400
#define BOOKE_GESR 383
/* Guest Exception Syndrome Register */
401
#define BOOKE_IVOR0 400
/* Interrupt Vector Offset Register 0 */
402
#define BOOKE_IVOR1 401
/* Interrupt Vector Offset Register 1 */
403
#define BOOKE_IVOR2 402
/* Interrupt Vector Offset Register 2 */
404
#define BOOKE_IVOR3 403
/* Interrupt Vector Offset Register 3 */
405
#define BOOKE_IVOR4 404
/* Interrupt Vector Offset Register 4 */
406
#define BOOKE_IVOR5 405
/* Interrupt Vector Offset Register 5 */
407
#define BOOKE_IVOR6 406
/* Interrupt Vector Offset Register 6 */
408
#define BOOKE_IVOR7 407
/* Interrupt Vector Offset Register 7 */
409
#define BOOKE_IVOR8 408
/* Interrupt Vector Offset Register 8 */
410
#define BOOKE_IVOR9 409
/* Interrupt Vector Offset Register 9 */
411
#define BOOKE_IVOR10 410
/* Interrupt Vector Offset Register 10 */
412
#define BOOKE_IVOR11 411
/* Interrupt Vector Offset Register 11 */
413
#define BOOKE_IVOR12 412
/* Interrupt Vector Offset Register 12 */
414
#define BOOKE_IVOR13 413
/* Interrupt Vector Offset Register 13 */
415
#define BOOKE_IVOR14 414
/* Interrupt Vector Offset Register 14 */
416
#define BOOKE_IVOR15 415
/* Interrupt Vector Offset Register 15 */
417
#define BOOKE_IVOR42 436
/* Interrupt Vector Offset Register 42 */
418
#define BOOKE_IVOR32 528
/* Interrupt Vector Offset Register 32 */
419
#define BOOKE_IVOR33 529
/* Interrupt Vector Offset Register 33 */
420
#define BOOKE_IVOR34 530
/* Interrupt Vector Offset Register 34 */
421
#define BOOKE_IVOR35 531
/* Interrupt Vector Offset Register 35 */
422
#define BOOKE_IVOR36 532
/* Interrupt Vector Offset Register 36 */
423
#define BOOKE_IVOR37 533
/* Interrupt Vector Offset Register 37 */
424
#define BOOKE_IVOR38 432
/* Interrupt Vector Offset Register 38 */
425
#define BOOKE_IVOR39 433
/* Interrupt Vector Offset Register 39 */
426
#define BOOKE_IVOR40 434
/* Interrupt Vector Offset Register 40 */
427
#define BOOKE_IVOR41 435
/* Interrupt Vector Offset Register 41 */
428
#define BOOKE_GIVOR2 440
/* Guest Interrupt Vector Offset Register 2 */
429
#define BOOKE_GIVOR3 441
/* Guest Interrupt Vector Offset Register 3 */
430
#define BOOKE_GIVOR4 442
/* Guest Interrupt Vector Offset Register 4 */
431
#define BOOKE_GIVOR8 443
/* Guest Interrupt Vector Offset Register 8 */
432
#define BOOKE_GIVOR13 444
/* Guest Interrupt Vector Offset Register 13 */
433
#define BOOKE_GIVOR14 445
/* Guest Interrupt Vector Offset Register 14 */
434
#define BOOKE_GIVPR 446
/* Guest Interrupt Vector Prefix Register */
435
#define BOOKE_MCSRR0 570
/* Machine Check Save/Restore Register 0 */
436
#define BOOKE_MCSRR1 571
/* Machine Check Save/Restore Register 1 */
437
#define BOOKE_MCSR 572
/* Machine Check Status Register */
438
#define BOOKE_DSRR0 574
/* Debug Save/Restore Register 0 */
439
#define BOOKE_DSRR1 575
/* Debug Save/Restore Register 1 */
440
441
#define PPC440_INV0 880
/* Instruction Cache Normal Victim 0 */
442
#define PPC440_INV1 881
/* Instruction Cache Normal Victim 1 */
443
#define PPC440_INV2 882
/* Instruction Cache Normal Victim 2 */
444
#define PPC440_INV3 883
/* Instruction Cache Normal Victim 3 */
445
#define PPC440_ITV0 884
/* Instruction Cache Transient Victim 0 */
446
#define PPC440_ITV1 885
/* Instruction Cache Transient Victim 1 */
447
#define PPC440_ITV2 886
/* Instruction Cache Transient Victim 2 */
448
#define PPC440_ITV3 887
/* Instruction Cache Transient Victim 3 */
449
#define PPC440_CCR1 888
/* Core Configuration Register 1 */
450
#define PPC440_DNV0 912
/* Data Cache Normal Victim 0 */
451
#define PPC440_DNV1 913
/* Data Cache Normal Victim 1 */
452
#define PPC440_DNV2 914
/* Data Cache Normal Victim 2 */
453
#define PPC440_DNV3 915
/* Data Cache Normal Victim 3 */
454
#define PPC440_DTV0 916
/* Data Cache Transient Victim 0 */
455
#define PPC440_DTV1 917
/* Data Cache Transient Victim 1 */
456
#define PPC440_DTV2 918
/* Data Cache Transient Victim 2 */
457
#define PPC440_DTV3 919
/* Data Cache Transient Victim 3 */
458
#define PPC440_DVLIM 920
/* Data Cache Victim Limit */
459
#define PPC440_IVLIM 921
/* Instruction Cache Victim Limit */
460
#define PPC440_RSTCFG 923
/* Reset Configuration */
461
#define PPC440_DCDBTRL 924
/* Data Cache Debug Tag Register Low */
462
#define PPC440_DCDBTRH 925
/* Data Cache Debug Tag Register High */
463
#define PPC440_ICDBTRL 926
/* Instruction Cache Debug Tag Register Low */
464
#define PPC440_ICDBTRH 927
/* Instruction Cache Debug Tag Register High */
465
#define PPC440_MMUCR 946
/* Memory Management Unit Control Register */
466
#define PPC440_CCR0 947
/* Core Configuration Register 0 */
467
#define PPC440_ICDBDR 979
/* Instruction Cache Debug Data Register */
468
#define PPC440_DBDR 1011
/* Debug Data Register */
469
470
#define PPC440_TLB0_EPN(n) ( (((1<<22)-1)&(n)) << (31-21))
/* Etended Page Number */
471
#define PPC440_TLB0_EPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1))
472
#define PPC440_TLB0_V ( 1 << (31-22))
/* Entry valid */
473
#define PPC440_TLB0_TS ( 1 << (31-23))
/* Translation space */
474
#define PPC440_TLB0_TSIZE(n) ( (0xf & (n)) << (31-27))
/* Page size */
475
#define PPC440_TLB0_TSIZE_GET(n) ( ((n) >> (31-27)) & 0xf)
476
#define PPC440_TLB0_TPAR(n) ( (0xf & (n)) << (31-31))
/* Tag Parity */
477
#define PPC440_TLB0_TPAR_GET(n) ( ((n) >> (31-31)) & 0xf)
478
479
#define PPC440_PID_TID(n) ( (0xff & (n)) << (31-31))
/* Translation ID */
480
#define PPC440_PID_TID_GET(n) ( ((n) >> (31-31)) & 0xff)
481
482
#define PPC440_TLB1_RPN(n) ( (((1<<22)-1)&(n)) << (31-21))
/* Real Page Number */
483
#define PPC440_TLB1_RPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1))
484
#define PPC440_TLB1_PAR1(n) ( (0x3 & (n)) << (31-23))
/* Parity for TLB word 1 */
485
#define PPC440_TLB1_PAR1_GET(n) ( ((n) >> (31-23)) & 0x3)
486
#define PPC440_TLB1_ERPN(n) ( (0xf & (n)) << (31-31))
/* Extended Real Page No. */
487
#define PPC440_TLB1_ERPN_GET(n) ( ((n) >> (31-31)) & 0xf)
488
489
#define PPC440_TLB2_PAR2(n) ( (0x3 & (n)) << (31- 1))
/* Parity for TLB word 2 */
490
#define PPC440_TLB2_PAR2_GET(n) ( ((n) >> (31- 1)) & 0x3)
491
#define PPC440_TLB2_U0 ( 1 << (31-16))
/* User attr. 0 */
492
#define PPC440_TLB2_U1 ( 1 << (31-17))
/* User attr. 1 */
493
#define PPC440_TLB2_U2 ( 1 << (31-18))
/* User attr. 2 */
494
#define PPC440_TLB2_U3 ( 1 << (31-19))
/* User attr. 3 */
495
#define PPC440_TLB2_W ( 1 << (31-20))
/* Write-through */
496
#define PPC440_TLB2_I ( 1 << (31-21))
/* Cache-inhibited */
497
#define PPC440_TLB2_M ( 1 << (31-22))
/* Memory-coherence req. */
498
#define PPC440_TLB2_G ( 1 << (31-23))
/* Guarded */
499
#define PPC440_TLB2_E ( 1 << (31-24))
/* Little-endian */
500
#define PPC440_TLB2_UX ( 1 << (31-26))
/* User exec. */
501
#define PPC440_TLB2_UW ( 1 << (31-27))
/* User write */
502
#define PPC440_TLB2_UR ( 1 << (31-28))
/* User read */
503
#define PPC440_TLB2_SX ( 1 << (31-29))
/* Super exec. */
504
#define PPC440_TLB2_SW ( 1 << (31-30))
/* Super write */
505
#define PPC440_TLB2_SR ( 1 << (31-31))
/* Super read */
506
507
#define PPC440_TLB2_ATTR(x) ( ((x) & 0x1ff) << 7 )
508
#define PPC440_TLB2_ATTR_GET(x) ( ((x) >> 7) & 0x1ff )
509
510
#define PPC440_TLB2_PERM(n) ( (n) & 0x3f )
511
#define PPC440_TLB2_PERM_GET(n) ( (n) & 0x3f )
512
513
/* Freescale Book E Implementation Standards (EIS): Branch Operations */
514
515
#define FSL_EIS_BUCSR 1013
516
#define FSL_EIS_BUCSR_STAC_EN (1 << (63 - 39))
517
#define FSL_EIS_BUCSR_LS_EN (1 << (63 - 41))
518
#define FSL_EIS_BUCSR_BBFI (1 << (63 - 54))
519
#define FSL_EIS_BUCSR_BALLOC_ALL (0x0 << (63 - 59))
520
#define FSL_EIS_BUCSR_BALLOC_FORWARD (0x1 << (63 - 59))
521
#define FSL_EIS_BUCSR_BALLOC_BACKWARD (0x2 << (63 - 59))
522
#define FSL_EIS_BUCSR_BALLOC_NONE (0x3 << (63 - 59))
523
#define FSL_EIS_BUCSR_BPRED_TAKEN (0x0 << (63 - 61))
524
#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_FORWARD (0x1 << (63 - 62))
525
#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_BACKWARD (0x2 << (63 - 62))
526
#define FSL_EIS_BUCSR_BPRED_NOT_TAKEN (0x3 << (63 - 62))
527
#define FSL_EIS_BUCSR_BPEN (1 << (63 - 63))
528
529
/* Freescale Book E Implementation Standards (EIS): Hardware Implementation-Dependent Registers */
530
531
#define FSL_EIS_SVR 1023
532
533
/* Freescale Book E Implementation Standards (EIS): Thread Management and Control Registers */
534
535
#define FSL_EIS_TENSR 437
536
#define FSL_EIS_TENS 438
537
#define FSL_EIS_TENC 439
538
#define FSL_EIS_PPR32 898
539
540
/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */
541
542
#define FSL_EIS_MAS0 624
543
#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35))
544
#define FSL_EIS_MAS0_ESEL(n) ((0xfff & (n)) << (63 - 47))
545
#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xfff)
546
#define FSL_EIS_MAS0_NV (1 << (63 - 63))
547
548
#define FSL_EIS_MAS1 625
549
#define FSL_EIS_MAS1_V (1 << (63 - 32))
550
#define FSL_EIS_MAS1_IPROT (1 << (63 - 33))
551
#define FSL_EIS_MAS1_TID(n) ((0xff & (n)) << (63 - 47))
552
#define FSL_EIS_MAS1_TID_GET(n) (((n) >> (63 - 47)) & 0xfff)
553
#define FSL_EIS_MAS1_TS (1 << (63 - 51))
554
#define FSL_EIS_MAS1_TSIZE(n) ((0xf & (n)) << (63 - 55))
555
#define FSL_EIS_MAS1_TSIZE_GET(n) (((n)>>(63 - 55)) & 0xf)
556
557
#define FSL_EIS_MAS2 626
558
#define FSL_EIS_MAS2_EPN(n) ((((1 << 21) - 1)&(n)) << (63-51))
559
#define FSL_EIS_MAS2_EPN_GET(n) (((n) >> (63 - 51)) & 0xfffff)
560
#define FSL_EIS_MAS2_EA(n) FSL_EIS_MAS2_EPN((n) >> 12)
561
#define FSL_EIS_MAS2_EA_GET(n) (FSL_EIS_MAS2_EPN_GET(n) << 12)
562
#define FSL_EIS_MAS2_X0 (1 << (63 - 57))
563
#define FSL_EIS_MAS2_X1 (1 << (63 - 58))
564
#define FSL_EIS_MAS2_W (1 << (63 - 59))
565
#define FSL_EIS_MAS2_I (1 << (63 - 60))
566
#define FSL_EIS_MAS2_M (1 << (63 - 61))
567
#define FSL_EIS_MAS2_G (1 << (63 - 62))
568
#define FSL_EIS_MAS2_E (1 << (63 - 63))
569
#define FSL_EIS_MAS2_ATTR(x) ((x) & 0x7f)
570
#define FSL_EIS_MAS2_ATTR_GET(x) ((x) & 0x7f)
571
572
#define FSL_EIS_MAS3 627
573
#define FSL_EIS_MAS3_RPN(n) ((((1 << 21) - 1) & (n)) << (63-51))
574
#define FSL_EIS_MAS3_RPN_GET(n) (((n)>>(63 - 51)) & 0xfffff)
575
#define FSL_EIS_MAS3_RA(n) FSL_EIS_MAS3_RPN((n) >> 12)
576
#define FSL_EIS_MAS3_RA_GET(n) (FSL_EIS_MAS3_RPN_GET(n) << 12)
577
#define FSL_EIS_MAS3_U0 (1 << (63 - 54))
578
#define FSL_EIS_MAS3_U1 (1 << (63 - 55))
579
#define FSL_EIS_MAS3_U2 (1 << (63 - 56))
580
#define FSL_EIS_MAS3_U3 (1 << (63 - 57))
581
#define FSL_EIS_MAS3_UX (1 << (63 - 58))
582
#define FSL_EIS_MAS3_SX (1 << (63 - 59))
583
#define FSL_EIS_MAS3_UW (1 << (63 - 60))
584
#define FSL_EIS_MAS3_SW (1 << (63 - 61))
585
#define FSL_EIS_MAS3_UR (1 << (63 - 62))
586
#define FSL_EIS_MAS3_SR (1 << (63 - 63))
587
#define FSL_EIS_MAS3_PERM(n) ((n) & 0x3ff)
588
#define FSL_EIS_MAS3_PERM_GET(n) ((n) & 0x3ff)
589
590
#define FSL_EIS_MAS4 628
591
#define FSL_EIS_MAS4_TLBSELD (1 << (63 - 35))
592
#define FSL_EIS_MAS4_TIDSELD(n) ((0x3 & (n)) << (63 - 47))
593
#define FSL_EIS_MAS4_TSIZED(n) ((0xf & (n)) << (63 - 55))
594
#define FSL_EIS_MAS4_X0D FSL_EIS_MAS2_X0
595
#define FSL_EIS_MAS4_X1D FSL_EIS_MAS2_X1
596
#define FSL_EIS_MAS4_WD FSL_EIS_MAS2_W
597
#define FSL_EIS_MAS4_ID FSL_EIS_MAS2_I
598
#define FSL_EIS_MAS4_MD FSL_EIS_MAS2_M
599
#define FSL_EIS_MAS4_GD FSL_EIS_MAS2_G
600
#define FSL_EIS_MAS4_ED FSL_EIS_MAS2_E
601
602
#define FSL_EIS_MAS5 629
603
604
#define FSL_EIS_MAS6 630
605
#define FSL_EIS_MAS6_SPID0(n) ((0xff & (n)) << (63 - 55))
606
#define FSL_EIS_MAS6_SAS (1 << (63 - 63))
607
608
#define FSL_EIS_MAS7 944
609
610
#define FSL_EIS_MAS8 341
611
612
#define FSL_EIS_MMUCFG 1015
613
#define FSL_EIS_MMUCSR0 1012
614
#define FSL_EIS_PID0 48
615
#define FSL_EIS_PID1 633
616
#define FSL_EIS_PID2 634
617
#define FSL_EIS_TLB0CFG 688
618
#define FSL_EIS_TLB1CFG 689
619
620
/* Freescale Book E Implementation Standards (EIS): L1 Cache */
621
622
#define FSL_EIS_L1CFG0 515
623
#define FSL_EIS_L1CFG1 516
624
#define FSL_EIS_L1CSR0 1010
625
#define FSL_EIS_L1CSR0_CFI (1 << (63 - 62))
626
#define FSL_EIS_L1CSR1 1011
627
#define FSL_EIS_L1CSR1_ICFI (1 << (63 - 62))
628
629
/* Freescale Book E Implementation Standards (EIS): L2 Cache */
630
631
#define FSL_EIS_L2CFG0 519
632
#define FSL_EIS_L2CSR0 1017
633
#define FSL_EIS_L2CSR0_L2FI (1 << (63 - 42))
634
#define FSL_EIS_L2CSR0_L2FL (1 << (63 - 52))
635
#define FSL_EIS_L2CSR1 1018
636
637
/* Freescale Book E Implementation Standards (EIS): Timer */
638
639
#define FSL_EIS_ATBL 526
640
#define FSL_EIS_ATBU 527
641
642
/* Freescale Book E Implementation Standards (EIS): Interrupt */
643
644
#define FSL_EIS_MCAR 573
645
#define FSL_EIS_DSRR0 574
646
#define FSL_EIS_DSRR1 575
647
#define FSL_EIS_EPR 702
648
649
/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */
650
651
#define FSL_EIS_SPEFSCR 512
652
653
/* Freescale Book E Implementation Standards (EIS): Software-Use SPRs */
654
655
#define FSL_EIS_SPRG8 604
656
#define FSL_EIS_SPRG9 605
657
658
/* Freescale Book E Implementation Standards (EIS): Debug */
659
660
#define FSL_EIS_DBCR3 561
661
#define FSL_EIS_DBCR4 563
662
#define FSL_EIS_DBCR5 564
663
#define FSL_EIS_DBCR6 603
664
#define FSL_EIS_DBCNT 562
665
672
#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
673
674
#ifndef ASM
675
676
#include <stdint.h>
677
678
#ifdef __cplusplus
679
extern
"C"
{
680
#endif
/* __cplusplus */
681
682
#define _CPU_MSR_GET( _msr_value ) \
683
do { \
684
_msr_value = 0; \
685
__asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
686
} while (0)
687
688
#define _CPU_MSR_SET( _msr_value ) \
689
{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
690
696
#if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE)
697
extern
char
_PPC_INTERRUPT_DISABLE_MASK
[];
698
699
static
inline
uint32_t ppc_interrupt_get_disable_mask(
void
)
700
{
701
return
(uint32_t) (uintptr_t)
_PPC_INTERRUPT_DISABLE_MASK
;
702
}
703
704
static
inline
uint32_t ppc_interrupt_disable(
void
)
705
{
706
uint32_t level;
707
708
#if defined(__PPC_CPU_E6500__)
709
__asm__
volatile
(
710
"mfmsr %0;"
711
"wrteei 0"
712
:
"=r"
(level)
713
);
714
#else
715
uint32_t mask;
716
717
__asm__
volatile
(
718
"mfmsr %0;"
719
"lis %1, _PPC_INTERRUPT_DISABLE_MASK@h;"
720
"ori %1, %1, _PPC_INTERRUPT_DISABLE_MASK@l;"
721
"andc %1, %0, %1;"
722
"mtmsr %1"
723
:
"=r"
(level),
"=r"
(mask)
724
);
725
#endif
726
727
return
level;
728
}
729
730
static
inline
void
ppc_interrupt_enable( uint32_t level )
731
{
732
#if defined(__PPC_CPU_E6500__)
733
__asm__
volatile
(
734
"wrtee %0"
735
:
736
:
"r"
(level)
737
);
738
#else
739
__asm__
volatile
(
740
"mtmsr %0"
741
:
742
:
"r"
(level)
743
);
744
#endif
745
}
746
747
static
inline
void
ppc_interrupt_flash( uint32_t level )
748
{
749
uint32_t current_level;
750
751
__asm__
volatile
(
752
"mfmsr %0;"
753
"mtmsr %1;"
754
"mtmsr %0"
755
:
"=&r"
(current_level)
756
:
"r"
(level)
757
);
758
}
759
#else
760
uint32_t ppc_interrupt_get_disable_mask(
void
);
761
uint32_t ppc_interrupt_disable(
void
);
762
void
ppc_interrupt_enable( uint32_t level );
763
void
ppc_interrupt_flash( uint32_t level );
764
#endif
/* PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE */
765
766
#define _CPU_ISR_Disable( _isr_cookie ) \
767
do { \
768
_isr_cookie = ppc_interrupt_disable(); \
769
} while (0)
770
771
/*
772
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
773
* This indicates the end of an RTEMS critical section. The parameter
774
* _isr_cookie is not modified.
775
*/
776
777
#define _CPU_ISR_Enable( _isr_cookie ) \
778
ppc_interrupt_enable(_isr_cookie)
779
780
/*
781
* This temporarily restores the interrupt to _isr_cookie before immediately
782
* disabling them again. This is used to divide long RTEMS critical
783
* sections into two or more parts. The parameter _isr_cookie is not
784
* modified.
785
*
786
* NOTE: The version being used is not very optimized but it does
787
* not trip a problem in gcc where the disable mask does not
788
* get loaded. Check this for future (post 10/97 gcc versions.
789
*/
790
791
#define _CPU_ISR_Flash( _isr_cookie ) \
792
ppc_interrupt_flash(_isr_cookie)
793
794
/* end of ISR handler macros */
795
796
#ifdef __cplusplus
797
}
798
#endif
/* __cplusplus */
799
800
#endif
/* ASM */
801
802
#endif
/* _RTEMS_POWERPC_REGISTERS_H */
_PPC_INTERRUPT_DISABLE_MASK
char _PPC_INTERRUPT_DISABLE_MASK[]
A global symbol used to disable interrupts in the MSR.
Generated by
1.18.0
1.18.0