RTEMS 6.3
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mpc8xx.h
1/*
2**************************************************************************
3**************************************************************************
4** **
5** MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR **
6** **
7** HARDWARE DECLARATIONS **
8** **
9** **
10** Submitted By: **
11** **
12** Eric Norum <eric.norum.ca> **
13** **
14** Modified for use with the MPC860 (original code was for MC68360) **
15** by **
16** Jay Monkman **
17** Frasca International, Inc. **
18** 906 E. Airport Rd. **
19** Urbana, IL, 61801 **
20** **
21** jmonkman@frasca.com **
22** **
23** Modified further for use with the MPC821 by: **
24** Andrew Bray <andy@chaos.org.uk> **
25** **
26** With some corrections/additions by: **
27** Darlene A. Stewart and **
28** Charles-Antoine Gauthier **
29** Institute for Information Technology **
30** National Research Council of Canada **
31** Ottawa, ON K1A 0R6 **
32** **
33** Darlene.Stewart@iit.nrc.ca **
34** charles.gauthier@iit.nrc.ca **
35** **
36** Corrections/additions: **
37** Copyright (c) 1999, National Research Council of Canada **
38**************************************************************************
39**************************************************************************
40*/
41#ifndef _MPC8XX_H
42#define _MPC8XX_H
43
44#ifndef ASM
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50/*
51 * Macros for accessing Special Purpose Registers (SPRs)
52 */
53#define _mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
54#define _mfspr(_reg,_spr) __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) )
55
56#define _isync __asm__ volatile ("isync\n"::)
57
58/*
59 * Core Registers (SPRs)
60 */
61#define M8xx_DEC 22 /* Decrementer Register */
62#define M8xx_DER 149 /* Debug Enable Register */
63#define M8xx_ICTRL 158 /* Instruction Support Control Register */
64#define M8xx_TBL_WR 284 /* Timebase Lower Write Register */
65#define M8xx_TBU_WR 285 /* Timebase Upper Write Register */
66#define M8xx_IMMR 638 /* Internal Memory Map Register */
67
68/*
69 * Cache Control Registers (SPRs)
70 */
71#define M8xx_IC_CST 560 /* Instruction Cache Control and Status Register */
72#define M8xx_DC_CST 568 /* Data Cache Control and Status Register */
73#define M8xx_IC_ADR 561 /* Instruction Cache Address Register */
74#define M8xx_DC_ADR 569 /* Data Cache Address Register */
75#define M8xx_IC_DAT 562 /* Instruction Cache Data Port Register */
76#define M8xx_DC_DAT 570 /* Data Cache Data Port Register */
77
78/*
79 * MMU Registers (SPRs)
80 */
81/* Control Registers */
82#define M8xx_MI_CTR 784 /* IMMU Control Register */
83#define M8xx_MD_CTR 792 /* DMMU Control Register */
84/* TLB Source Registers */
85#define M8xx_MI_EPN 787 /* IMMU Effective Page Number Register (EPN) */
86#define M8xx_MD_EPN 795 /* DMMU Effective Page Number Register (EPN) */
87#define M8xx_MI_TWC 789 /* IMMU Tablewalk Control Register (TWC) */
88#define M8xx_MD_TWC 797 /* DMMU Tablewalk Control Register (TWC) */
89#define M8xx_MI_RPN 790 /* IMMU Real (physical) Page Number Register (RPN) */
90#define M8xx_MD_RPN 798 /* DMMU Real (physical) Page Number Register (RPN) */
91/* Tablewalk Assist Registers */
92#define M8xx_M_TWB 796 /* MMU Tablewalk Base Register (TWB) */
93/* Protection Registers */
94#define M8xx_M_CASID 793 /* MMU Current Address Space ID Register */
95#define M8xx_MI_AP 786 /* IMMU Access Protection Register */
96#define M8xx_MD_AP 794 /* DMMU Access Protection Register */
97/* Scratch Register */
98#define M8xx_M_TW 799 /* MMU Tablewalk Special Register */
99/* Debug Registers */
100#define M8xx_MI_CAM 816 /* IMMU CAM Entry Read Register */
101#define M8xx_MI_RAM0 817 /* IMMU RAM Entry Read Register 0 */
102#define M8xx_MI_RAM1 818 /* IMMU RAM Entry Read Register 1 */
103#define M8xx_MD_CAM 824 /* DMMU CAM Entry Read Register */
104#define M8xx_MD_RAM0 825 /* DMMU RAM Entry Read Register 0 */
105#define M8xx_MD_RAM1 826 /* DMMU RAM Entry Read Register 1 */
106
107#define M8xx_MI_CTR_GPM (1<<31)
108#define M8xx_MI_CTR_PPM (1<<30)
109#define M8xx_MI_CTR_CIDEF (1<<29)
110#define M8xx_MI_CTR_RSV4I (1<<27)
111#define M8xx_MI_CTR_PPCS (1<<25)
112#define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8) /* ITLB index */
113
114#define M8xx_MD_CTR_GPM (1<<31)
115#define M8xx_MD_CTR_PPM (1<<30)
116#define M8xx_MD_CTR_CIDEF (1<<29)
117#define M8xx_MD_CTR_WTDEF (1<<28)
118#define M8xx_MD_CTR_RSV4D (1<<27)
119#define M8xx_MD_CTR_TWAM (1<<26)
120#define M8xx_MD_CTR_PPCS (1<<25)
121#define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8) /* DTLB index */
122
123#define M8xx_MI_EPN_VALID (1<<9)
124
125#define M8xx_MD_EPN_VALID (1<<9)
126
127#define M8xx_MI_TWC_G (1<<4)
128#define M8xx_MI_TWC_PSS (0<<2)
129#define M8xx_MI_TWC_PS512 (1<<2)
130#define M8xx_MI_TWC_PS8 (3<<2)
131#define M8xx_MI_TWC_VALID (1)
132
133#define M8xx_MD_TWC_G (1<<4)
134#define M8xx_MD_TWC_PSS (0<<2)
135#define M8xx_MD_TWC_PS512 (1<<2)
136#define M8xx_MD_TWC_PS8 (3<<2)
137#define M8xx_MD_TWC_WT (1<<1)
138#define M8xx_MD_TWC_VALID (1)
139
140#define M8xx_MI_RPN_F (0xf<<4)
141#define M8xx_MI_RPN_16K (1<<3)
142#define M8xx_MI_RPN_SHARED (1<<2)
143#define M8xx_MI_RPN_CI (1<<1)
144#define M8xx_MI_RPN_VALID (1)
145
146#define M8xx_MD_RPN_CHANGE (1<<8)
147#define M8xx_MD_RPN_F (0xf<<4)
148#define M8xx_MD_RPN_16K (1<<3)
149#define M8xx_MD_RPN_SHARED (1<<2)
150#define M8xx_MD_RPN_CI (1<<1)
151#define M8xx_MD_RPN_VALID (1)
152
153#define M8xx_MI_AP_Kp (1)
154
155#define M8xx_MD_AP_Kp (1)
156
157#define M8xx_CACHE_CMD_SFWT (0x1<<24)
158#define M8xx_CACHE_CMD_ENABLE (0x2<<24)
159#define M8xx_CACHE_CMD_CFWT (0x3<<24)
160#define M8xx_CACHE_CMD_DISABLE (0x4<<24)
161#define M8xx_CACHE_CMD_STLES (0x5<<24)
162#define M8xx_CACHE_CMD_LLCB (0x6<<24)
163#define M8xx_CACHE_CMD_CLES (0x7<<24)
164#define M8xx_CACHE_CMD_UNLOCK (0x8<<24)
165#define M8xx_CACHE_CMD_UNLOCKALL (0xa<<24)
166#define M8xx_CACHE_CMD_INVALIDATE (0xc<<24)
167#define M8xx_CACHE_CMD_FLUSH (0xe<<24)
168
169/*
170*************************************************************************
171* REGISTER SUBBLOCKS *
172*************************************************************************
173*/
174
175/*
176 * Memory controller registers
177 */
178typedef struct m8xxMEMCRegisters_ {
179 uint32_t _br;
180 uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */
181} m8xxMEMCRegisters_t;
182
183/*
184 * Serial Communications Controller registers
185 */
186typedef struct m8xxSCCRegisters_ {
187 uint32_t gsmr_l;
188 uint32_t gsmr_h;
189 uint16_t psmr;
190 uint16_t _pad0;
191 uint16_t todr;
192 uint16_t dsr;
193 uint16_t scce;
194 uint16_t _pad1;
195 uint16_t sccm;
196 uint8_t _pad2;
197 uint8_t sccs;
198 uint32_t _pad3[2];
199} m8xxSCCRegisters_t;
200
201/*
202 * Serial Management Controller registers
203 */
204typedef struct m8xxSMCRegisters_ {
205 uint16_t _pad0;
206 uint16_t smcmr;
207 uint16_t _pad1;
208 uint8_t smce;
209 uint8_t _pad2;
210 uint16_t _pad3;
211 uint8_t smcm;
212 uint8_t _pad4;
213 uint32_t _pad5;
214} m8xxSMCRegisters_t;
215
216/*
217 * Fast Ethernet Controller registers (Only on MPC8xxT)
218 */
219typedef struct m8xxFECRegisters_ {
220 uint32_t addr_low;
221 uint32_t addr_high;
222 uint32_t hash_table_high;
223 uint32_t hash_table_low;
224 uint32_t r_des_start;
225 uint32_t x_des_start;
226 uint32_t r_buf_size;
227 uint32_t _pad0[9];
228 uint32_t ecntrl;
229 uint32_t ievent;
230 uint32_t imask;
231 uint32_t ivec;
232 uint32_t r_des_active;
233 uint32_t x_des_active;
234 uint32_t _pad1[10];
235 uint32_t mii_data;
236 uint32_t mii_speed;
237 uint32_t _pad2[17];
238 uint32_t r_bound;
239 uint32_t r_fstart;
240 uint32_t _pad3[6];
241 uint32_t x_fstart;
242 uint32_t _pad4[17];
243 uint32_t fun_code;
244 uint32_t _pad5[3];
245 uint32_t r_cntrl;
246 uint32_t r_hash;
247 uint32_t _pad6[14];
248 uint32_t x_cntrl;
249 uint32_t _pad7[30];
250
251} m8xxFECRegisters_t;
252
253#define M8xx_FEC_IEVENT_HBERR (1 << 31)
254#define M8xx_FEC_IEVENT_BABR (1 << 30)
255#define M8xx_FEC_IEVENT_BABT (1 << 29)
256#define M8xx_FEC_IEVENT_GRA (1 << 28)
257#define M8xx_FEC_IEVENT_TFINT (1 << 27)
258#define M8xx_FEC_IEVENT_TXB (1 << 26)
259#define M8xx_FEC_IEVENT_RFINT (1 << 25)
260#define M8xx_FEC_IEVENT_RXB (1 << 24)
261#define M8xx_FEC_IEVENT_MII (1 << 23)
262#define M8xx_FEC_IEVENT_EBERR (1 << 22)
263#define M8xx_FEC_IMASK_HBEEN (1 << 31)
264#define M8xx_FEC_IMASK_BREEN (1 << 30)
265#define M8xx_FEC_IMASK_BTEN (1 << 29)
266#define M8xx_FEC_IMASK_GRAEN (1 << 28)
267#define M8xx_FEC_IMASK_TFIEN (1 << 27)
268#define M8xx_FEC_IMASK_TBIEN (1 << 26)
269#define M8xx_FEC_IMASK_RFIEN (1 << 25)
270#define M8xx_FEC_IMASK_RBIEN (1 << 24)
271#define M8xx_FEC_IMASK_MIIEN (1 << 23)
272#define M8xx_FEC_IMASK_EBERREN (1 << 22)
273
274 /*
275 * access macros to write to mii_data register
276 */
277#define M8xx_FEC_MII_DATA_ST ( 1 << (31- 1))
278#define M8xx_FEC_MII_DATA_OP_RD ( 2 << (31- 3))
279#define M8xx_FEC_MII_DATA_OP_WR ( 1 << (31- 3))
280#define M8xx_FEC_MII_DATA_PHYAD(n) (((n) & 0x3f) << (31- 8))
281#define M8xx_FEC_MII_DATA_PHYRA(n) (((n) & 0x3f) << (31-13))
282#define M8xx_FEC_MII_DATA_TA ( 2 << (31-15))
283#define M8xx_FEC_MII_DATA_WDATA(n) ((n) & 0xffff )
284#define M8xx_FEC_MII_DATA_RDATA(reg) ((reg) & 0xffff )
285 /*
286 * bits for FEC ECNTRL register
287 */
288#define M8xx_FEC_ECNTRL_FEC_PINMUX ( 1 << (31-29))
289#define M8xx_FEC_ECNTRL_ETHER_EN ( 1 << (31-30))
290#define M8xx_FEC_ECNTRL_RESET ( 1 << (31-31))
291
292 /*
293 * bits for FEC R_CNTRL register
294 */
295#define M8xx_FEC_R_CNTRL_BC_REJ ( 1 << (31-27))
296#define M8xx_FEC_R_CNTRL_PROM ( 1 << (31-28))
297#define M8xx_FEC_R_CNTRL_MII_MODE ( 1 << (31-29))
298#define M8xx_FEC_R_CNTRL_DRT ( 1 << (31-30))
299#define M8xx_FEC_R_CNTRL_LOOP ( 1 << (31-31))
300
301 /*
302 * bits for FEC X_CNTRL register
303 */
304#define M8xx_FEC_X_CNTRL_FDEN ( 1 << (31-29))
305#define M8xx_FEC_X_CNTRL_HBC ( 1 << (31-30))
306#define M8xx_FEC_X_CNTRL_GTS ( 1 << (31-31))
307/*
308*************************************************************************
309* Miscellaneous Parameters *
310*************************************************************************
311*/
312typedef struct m8xxMiscParms_ {
313 uint16_t rev_num;
314 uint16_t _res1;
315 uint32_t _res2;
316 uint32_t _res3;
317} m8xxMiscParms_t;
318
319/*
320*************************************************************************
321* RISC Timers *
322*************************************************************************
323*/
324typedef struct m8xxTimerParms_ {
325 uint16_t tm_base;
326 uint16_t _tm_ptr;
327 uint16_t _r_tmr;
328 uint16_t _r_tmv;
329 uint32_t tm_cmd;
330 uint32_t tm_cnt;
331} m8xxTimerParms_t;
332
333/*
334 * RISC Controller Configuration Register (RCCR)
335 * All other bits in this register are reserved.
336 */
337#define M8xx_RCCR_TIME (1<<15) /* Enable timer */
338#define M8xx_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
339#define M8xx_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */
340#define M8xx_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */
341#define M8xx_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */
342#define M8xx_RCCR_EIE (1<<3) /* External Interrupt Enable */
343#define M8xx_RCCR_SCD (1<<2) /* Scheduler Configuration */
344#define M8xx_RCCR_ERAM(x) (x) /* Enable RAM Microcode */
345
346/*
347 * Command register
348 * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command.
349 */
350#define M8xx_TM_CMD_V (1<<31) /* Set to enable timer */
351#define M8xx_TM_CMD_R (1<<30) /* Set for automatic restart */
352#define M8xx_TM_CMD_PWM (1<<29) /* Set for PWM operation */
353#define M8xx_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
354#define M8xx_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
355
356/*
357*************************************************************************
358* DMA Controllers *
359*************************************************************************
360*/
361typedef struct m8xxIDMAparms_ {
362 uint16_t ibase;
363 uint16_t dcmr;
364 uint32_t _sapr;
365 uint32_t _dapr;
366 uint16_t ibptr;
367 uint16_t _write_sp;
368 uint32_t _s_byte_c;
369 uint32_t _d_byte_c;
370 uint32_t _s_state;
371 uint32_t _itemp[4];
372 uint32_t _sr_mem;
373 uint16_t _read_sp;
374 uint16_t _res0;
375 uint16_t _res1;
376 uint16_t _res2;
377 uint32_t _d_state;
378} m8xxIDMAparms_t;
379
380
381/*
382*************************************************************************
383* DSP *
384*************************************************************************
385*/
386typedef struct m8xxDSPparms_ {
387 uint32_t fdbase;
388 uint32_t _fd_ptr;
389 uint32_t _dstate;
390 uint32_t _pad0;
391 uint16_t _dstatus;
392 uint16_t _i;
393 uint16_t _tap;
394 uint16_t _cbase;
395 uint16_t _pad1;
396 uint16_t _xptr;
397 uint16_t _pad2;
398 uint16_t _yptr;
399 uint16_t _m;
400 uint16_t _pad3;
401 uint16_t _n;
402 uint16_t _pad4;
403 uint16_t _k;
404 uint16_t _pad5;
405} m8xxDSPparms_t;
406
407/*
408*************************************************************************
409* Serial Communication Controllers *
410*************************************************************************
411*/
412typedef struct m8xxSCCparms_ {
413 uint16_t rbase;
414 uint16_t tbase;
415 uint8_t rfcr;
416 uint8_t tfcr;
417 uint16_t mrblr;
418 uint32_t _rstate;
419 uint32_t _pad0;
420 uint16_t _rbptr;
421 uint16_t _pad1;
422 uint32_t _pad2;
423 uint32_t _tstate;
424 uint32_t _pad3;
425 uint16_t _tbptr;
426 uint16_t _pad4;
427 uint32_t _pad5;
428 uint32_t _rcrc;
429 uint32_t _tcrc;
430 union {
431 struct {
432 uint32_t _res0;
433 uint32_t _res1;
434 uint16_t max_idl;
435 uint16_t _idlc;
436 uint16_t brkcr;
437 uint16_t parec;
438 uint16_t frmec;
439 uint16_t nosec;
440 uint16_t brkec;
441 uint16_t brkln;
442 uint16_t uaddr[2];
443 uint16_t _rtemp;
444 uint16_t toseq;
445 uint16_t character[8];
446 uint16_t rccm;
447 uint16_t rccr;
448 uint16_t rlbc;
449 } uart;
450 } un;
451} m8xxSCCparms_t;
452
453typedef struct m8xxSCCENparms_ {
454 uint16_t rbase;
455 uint16_t tbase;
456 uint8_t rfcr;
457 uint8_t tfcr;
458 uint16_t mrblr;
459 uint32_t _rstate;
460 uint32_t _pad0;
461 uint16_t _rbptr;
462 uint16_t _pad1;
463 uint32_t _pad2;
464 uint32_t _tstate;
465 uint32_t _pad3;
466 uint16_t _tbptr;
467 uint16_t _pad4;
468 uint32_t _pad5;
469 uint32_t _rcrc;
470 uint32_t _tcrc;
471 union {
472 struct {
473 uint32_t _res0;
474 uint32_t _res1;
475 uint16_t max_idl;
476 uint16_t _idlc;
477 uint16_t brkcr;
478 uint16_t parec;
479 uint16_t frmec;
480 uint16_t nosec;
481 uint16_t brkec;
482 uint16_t brkln;
483 uint16_t uaddr[2];
484 uint16_t _rtemp;
485 uint16_t toseq;
486 uint16_t character[8];
487 uint16_t rccm;
488 uint16_t rccr;
489 uint16_t rlbc;
490 } uart;
491 struct {
492 uint32_t c_pres;
493 uint32_t c_mask;
494 uint32_t crcec;
495 uint32_t alec;
496 uint32_t disfc;
497 uint16_t pads;
498 uint16_t ret_lim;
499 uint16_t _ret_cnt;
500 uint16_t mflr;
501 uint16_t minflr;
502 uint16_t maxd1;
503 uint16_t maxd2;
504 uint16_t _maxd;
505 uint16_t dma_cnt;
506 uint16_t _max_b;
507 uint16_t gaddr1;
508 uint16_t gaddr2;
509 uint16_t gaddr3;
510 uint16_t gaddr4;
511 uint32_t _tbuf0data0;
512 uint32_t _tbuf0data1;
513 uint32_t _tbuf0rba0;
514 uint32_t _tbuf0crc;
515 uint16_t _tbuf0bcnt;
516 uint16_t paddr_h;
517 uint16_t paddr_m;
518 uint16_t paddr_l;
519 uint16_t p_per;
520 uint16_t _rfbd_ptr;
521 uint16_t _tfbd_ptr;
522 uint16_t _tlbd_ptr;
523 uint32_t _tbuf1data0;
524 uint32_t _tbuf1data1;
525 uint32_t _tbuf1rba0;
526 uint32_t _tbuf1crc;
527 uint16_t _tbuf1bcnt;
528 uint16_t _tx_len;
529 uint16_t iaddr1;
530 uint16_t iaddr2;
531 uint16_t iaddr3;
532 uint16_t iaddr4;
533 uint16_t _boff_cnt;
534 uint16_t taddr_m;
535 uint16_t taddr_l;
536 uint16_t taddr_h;
537 } ethernet;
538 } un;
539} m8xxSCCENparms_t;
540
541/*
542 * Receive and transmit function code register bits
543 * These apply to the function code registers of all devices, not just SCC.
544 */
545#define M8xx_RFCR_BO(x) ((x)<<3)
546#define M8xx_RFCR_MOT (2<<3)
547#define M8xx_RFCR_DMA_SPACE(x) (x)
548#define M8xx_TFCR_BO(x) ((x)<<3)
549#define M8xx_TFCR_MOT (2<<3)
550#define M8xx_TFCR_DMA_SPACE(x) (x)
551
552/*
553 * Event and mask registers (SCCE, SCCM)
554 */
555#define M8xx_SCCE_BRKE (1<<6)
556#define M8xx_SCCE_BRK (1<<4)
557#define M8xx_SCCE_BSY (1<<2)
558#define M8xx_SCCE_TX (1<<1)
559#define M8xx_SCCE_RX (1<<0)
560
561/*
562*************************************************************************
563* Serial Management Controllers *
564*************************************************************************
565*/
566typedef struct m8xxSMCparms_ {
567 uint16_t rbase;
568 uint16_t tbase;
569 uint8_t rfcr;
570 uint8_t tfcr;
571 uint16_t mrblr;
572 uint32_t _rstate;
573 uint32_t _pad0;
574 uint16_t _rbptr;
575 uint16_t _pad1;
576 uint32_t _pad2;
577 uint32_t _tstate;
578 uint32_t _pad3;
579 uint16_t _tbptr;
580 uint16_t _pad4;
581 uint32_t _pad5;
582 union {
583 struct {
584 uint16_t max_idl;
585 uint16_t _idlc;
586 uint16_t brkln;
587 uint16_t brkec;
588 uint16_t brkcr;
589 uint16_t _r_mask;
590 } uart;
591 struct {
592 uint16_t _pad0[5];
593 } transparent;
594 } un;
595} m8xxSMCparms_t;
596
597/*
598 * Mode register
599 */
600#define M8xx_SMCMR_CLEN(x) ((x)<<11) /* Character length */
601#define M8xx_SMCMR_2STOP (1<<10) /* 2 stop bits */
602#define M8xx_SMCMR_PARITY (1<<9) /* Enable parity */
603#define M8xx_SMCMR_EVEN (1<<8) /* Even parity */
604#define M8xx_SMCMR_SM_GCI (0<<4) /* GCI Mode */
605#define M8xx_SMCMR_SM_UART (2<<4) /* UART Mode */
606#define M8xx_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
607#define M8xx_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
608#define M8xx_SMCMR_DM_ECHO (2<<2) /* Echo mode */
609#define M8xx_SMCMR_TEN (1<<1) /* Enable transmitter */
610#define M8xx_SMCMR_REN (1<<0) /* Enable receiver */
611
612/*
613 * Event and mask registers (SMCE, SMCM)
614 */
615#define M8xx_SMCE_BRKE (1<<6)
616#define M8xx_SMCE_BRK (1<<4)
617#define M8xx_SMCE_BSY (1<<2)
618#define M8xx_SMCE_TX (1<<1)
619#define M8xx_SMCE_RX (1<<0)
620
621/*
622*************************************************************************
623* Serial Peripheral Interface *
624*************************************************************************
625*/
626typedef struct m8xxSPIparms_ {
627 uint16_t rbase;
628 uint16_t tbase;
629 uint8_t rfcr;
630 uint8_t tfcr;
631 uint16_t mrblr;
632 uint32_t _rstate;
633 uint32_t _pad0;
634 uint16_t _rbptr;
635 uint16_t _pad1;
636 uint32_t _pad2;
637 uint32_t _tstate;
638 uint32_t _pad3;
639 uint16_t _tbptr;
640 uint16_t _pad4;
641 uint32_t _pad5;
642} m8xxSPIparms_t;
643
644/*
645 * Mode register (SPMODE)
646 */
647#define M8xx_SPMODE_LOOP (1<<14) /* Local loopback mode */
648#define M8xx_SPMODE_CI (1<<13) /* Clock invert */
649#define M8xx_SPMODE_CP (1<<12) /* Clock phase */
650#define M8xx_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
651#define M8xx_SPMODE_REV (1<<10) /* Reverse data */
652#define M8xx_SPMODE_MASTER (1<<9) /* SPI is master */
653#define M8xx_SPMODE_EN (1<<8) /* Enable SPI */
654#define M8xx_SPMODE_CLEN(x) ((x)<<4) /* Character length */
655#define M8xx_SPMODE_PM(x) (x) /* Prescaler modulus */
656
657/*
658 * Mode register (SPCOM)
659 */
660#define M8xx_SPCOM_STR (1<<7) /* Start transmit */
661
662/*
663 * Event and mask registers (SPIE, SPIM)
664 */
665#define M8xx_SPIE_MME (1<<5) /* Multi-master error */
666#define M8xx_SPIE_TXE (1<<4) /* Tx error */
667#define M8xx_SPIE_BSY (1<<2) /* Busy condition*/
668#define M8xx_SPIE_TXB (1<<1) /* Tx buffer */
669#define M8xx_SPIE_RXB (1<<0) /* Rx buffer */
670
671/*
672*************************************************************************
673* SDMA (SCC, SMC, SPI) Buffer Descriptors *
674*************************************************************************
675*/
676typedef struct m8xxBufferDescriptor_ {
677 volatile uint16_t status;
678 uint16_t length;
679 void *buffer;
680} m8xxBufferDescriptor_t;
681
682/*
683 * Bits in receive buffer descriptor status word
684 */
685#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
686#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
687#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
688#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */
689#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */
690#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
691#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */
692#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
693#define M8xx_BD_MISS (1<<8) /* Ethernet */
694#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */
695#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
696#define M8xx_BD_LONG (1<<5) /* Ethernet */
697#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */
698#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet */
699#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
700#define M8xx_BD_SHORT (1<<3) /* Ethernet */
701#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
702#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet */
703#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
704#define M8xx_BD_COLLISION (1<<0) /* Ethernet */
705#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
706#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */
707
708/*
709 * Bits in transmit buffer descriptor status word
710 * Many bits have the same meaning as those in receiver buffer descriptors.
711 */
712#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
713#define M8xx_BD_PAD (1<<14) /* Ethernet */
714#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */
715#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */
716#define M8xx_BD_DEFER (1<<9) /* Ethernet */
717#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */
718#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
719#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */
720#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */
721#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */
722#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
723#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
724#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */
725#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART */
726
727/*
728*************************************************************************
729* IDMA Buffer Descriptors *
730*************************************************************************
731*/
732typedef struct m8xxIDMABufferDescriptor_ {
733 uint16_t status;
734 uint8_t dfcr;
735 uint8_t sfcr;
736 uint32_t length;
737 void *source;
738 void *destination;
739} m8xxIDMABufferDescriptor_t;
740
741/*
742*************************************************************************
743* RISC Communication Processor Module Command Register (CR) *
744*************************************************************************
745*/
746#define M8xx_CR_RST (1<<15) /* Reset communication processor */
747#define M8xx_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
748#define M8xx_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
749#define M8xx_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
750#define M8xx_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
751#define M8xx_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
752#define M8xx_CR_OP_GR_STOP_TX (5<<8) /* SCC */
753#define M8xx_CR_OP_INIT_IDMA (5<<8) /* IDMA */
754#define M8xx_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
755#define M8xx_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
756#define M8xx_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
757#define M8xx_CR_OP_SET_TIMER (8<<8) /* Timer */
758#define M8xx_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
759#define M8xx_CR_OP_RESERT_BCS (10<<8) /* SCC */
760#define M8xx_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
761#define M8xx_CR_OP_STOP_IDMA (11<<8) /* IDMA */
762#define M8xx_CR_OP_START_DSP (12<<8) /* DSP */
763#define M8xx_CR_OP_INIT_DSP (13<<8) /* DSP */
764
765#define M8xx_CR_CHAN_SCC1 (0<<4) /* Channel selection */
766#define M8xx_CR_CHAN_I2C (1<<4)
767#define M8xx_CR_CHAN_IDMA1 (1<<4)
768#define M8xx_CR_CHAN_SCC2 (4<<4)
769#define M8xx_CR_CHAN_SPI (5<<4)
770#define M8xx_CR_CHAN_IDMA2 (5<<4)
771#define M8xx_CR_CHAN_TIMER (5<<4)
772#define M8xx_CR_CHAN_SCC3 (8<<4)
773#define M8xx_CR_CHAN_SMC1 (9<<4)
774#define M8xx_CR_CHAN_DSP1 (9<<4)
775#define M8xx_CR_CHAN_SCC4 (12<<4)
776#define M8xx_CR_CHAN_SMC2 (13<<4)
777#define M8xx_CR_CHAN_DSP2 (13<<4)
778#define M8xx_CR_FLG (1<<0) /* Command flag */
779
780/*
781*************************************************************************
782* System Protection Control Register (SYPCR) *
783*************************************************************************
784*/
785#define M8xx_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
786#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
787#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */
788#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */
789#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */
790#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
791#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */
792
793/*
794*************************************************************************
795* PCMCIA Control Registers
796*************************************************************************
797*/
798#define M8xx_PCMCIA_POR_BSIZE_1B (0x00 << (31-4))
799#define M8xx_PCMCIA_POR_BSIZE_2B (0x01 << (31-4))
800#define M8xx_PCMCIA_POR_BSIZE_4B (0x03 << (31-4))
801#define M8xx_PCMCIA_POR_BSIZE_8B (0x02 << (31-4))
802#define M8xx_PCMCIA_POR_BSIZE_16B (0x06 << (31-4))
803#define M8xx_PCMCIA_POR_BSIZE_32B (0x07 << (31-4))
804#define M8xx_PCMCIA_POR_BSIZE_64B (0x05 << (31-4))
805#define M8xx_PCMCIA_POR_BSIZE_128B (0x04 << (31-4))
806#define M8xx_PCMCIA_POR_BSIZE_256B (0x0C << (31-4))
807#define M8xx_PCMCIA_POR_BSIZE_512B (0x0D << (31-4))
808#define M8xx_PCMCIA_POR_BSIZE_1KB (0x0F << (31-4))
809#define M8xx_PCMCIA_POR_BSIZE_2KB (0x0E << (31-4))
810#define M8xx_PCMCIA_POR_BSIZE_4KB (0x0A << (31-4))
811#define M8xx_PCMCIA_POR_BSIZE_8KB (0x0B << (31-4))
812#define M8xx_PCMCIA_POR_BSIZE_16KB (0x09 << (31-4))
813#define M8xx_PCMCIA_POR_BSIZE_32KB (0x08 << (31-4))
814#define M8xx_PCMCIA_POR_BSIZE_64KB (0x18 << (31-4))
815#define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4))
816#define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4))
817#define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4))
818#define M8xx_PCMCIA_POR_BSIZE_1MB (0x1E << (31-4))
819#define M8xx_PCMCIA_POR_BSIZE_2MB (0x1F << (31-4))
820#define M8xx_PCMCIA_POR_BSIZE_4MB (0x1D << (31-4))
821#define M8xx_PCMCIA_POR_BSIZE_8MB (0x1C << (31-4))
822#define M8xx_PCMCIA_POR_BSIZE_16MB (0x14 << (31-4))
823#define M8xx_PCMCIA_POR_BSIZE_32MB (0x15 << (31-4))
824#define M8xx_PCMCIA_POR_BSIZE_64MB (0x17 << (31-4))
825
826#define M8xx_PCMCIA_POR_PSHT(x) (((x) & 0x0f) << (31-15))
827#define M8xx_PCMCIA_POR_PSST(x) (((x) & 0x0f) << (31-19))
828#define M8xx_PCMCIA_POR_PSL(x) (((x) & 0x1f) << (31-24))
829#define M8xx_PCMCIA_POR_PPS_8 ((0) << (31-19))
830#define M8xx_PCMCIA_POR_PPS_16 ((1) << (31-19))
831
832#define M8xx_PCMCIA_POR_PRS_MEM ((0) << (31-28))
833#define M8xx_PCMCIA_POR_PRS_ATT ((2) << (31-28))
834#define M8xx_PCMCIA_POR_PRS_IO ((3) << (31-28))
835#define M8xx_PCMCIA_POR_PRS_DMA ((4) << (31-28))
836#define M8xx_PCMCIA_POR_PRS_DML ((5) << (31-28))
837
838#define M8xx_PCMCIA_POR_PSLOT_A ((0) << (31-29))
839#define M8xx_PCMCIA_POR_PSLOT_B ((1) << (31-29))
840
841#define M8xx_PCMCIA_POR_WP ((1) << (31-30))
842#define M8xx_PCMCIA_POR_VALID ((1) << (31-31))
843
844#define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7))
845#define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15))
846#define M8xx_PCMCIA_PGCR_CDRQ_OFF ((0) << (31-17))
847#define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17))
848#define M8xx_PCMCIA_PGCR_CDRQ_SPKR ((3) << (31-17))
849#define M8xx_PCMCIA_PGCR_COE ((1) << (31-24))
850#define M8xx_PCMCIA_PGCR_CRESET ((1) << (31-25))
851
852#define M8xx_PCMCIA_PIPR_CAVS1 ((1) << (31- 0))
853#define M8xx_PCMCIA_PIPR_CAVS2 ((1) << (31- 1))
854#define M8xx_PCMCIA_PIPR_CAWP ((1) << (31- 2))
855#define M8xx_PCMCIA_PIPR_CACD2 ((1) << (31- 3))
856#define M8xx_PCMCIA_PIPR_CACD1 ((1) << (31- 4))
857#define M8xx_PCMCIA_PIPR_CABVD2 ((1) << (31- 5))
858#define M8xx_PCMCIA_PIPR_CABVD1 ((1) << (31- 6))
859#define M8xx_PCMCIA_PIPR_CARDY ((1) << (31- 7))
860#define M8xx_PCMCIA_PIPR_CBVS1 ((1) << (31-16))
861#define M8xx_PCMCIA_PIPR_CBVS2 ((1) << (31-17))
862#define M8xx_PCMCIA_PIPR_CBWP ((1) << (31-18))
863#define M8xx_PCMCIA_PIPR_CBCD2 ((1) << (31-19))
864#define M8xx_PCMCIA_PIPR_CBCD1 ((1) << (31-20))
865#define M8xx_PCMCIA_PIPR_CBBVD2 ((1) << (31-21))
866#define M8xx_PCMCIA_PIPR_CBBVD1 ((1) << (31-22))
867#define M8xx_PCMCIA_PIPR_CBRDY ((1) << (31-23))
868
869
870#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
871#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */
872#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */
873#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */
874#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
875#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */
876
877/*
878*************************************************************************
879* Memory Control Registers *
880*************************************************************************
881*/
882#define M8xx_UPM_AMX_8col (0<<20) /* 8 column DRAM */
883#define M8xx_UPM_AMX_9col (1<<20) /* 9 column DRAM */
884#define M8xx_UPM_AMX_10col (2<<20) /* 10 column DRAM */
885#define M8xx_UPM_AMX_11col (3<<20) /* 11 column DRAM */
886#define M8xx_UPM_AMX_12col (4<<20) /* 12 column DRAM */
887#define M8xx_UPM_AMX_13col (5<<20) /* 13 column DRAM */
888#define M8xx_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */
889#define M8xx_MSR_WPER (1<<7) /* Write protection error */
890#define M8xx_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */
891#define M8xx_BR_BA(x) ((x)&0xffff8000) /* Base address */
892#define M8xx_BR_AT(x) ((x)<<12) /* Address type */
893#define M8xx_BR_PS8 (1<<10) /* 8 bit port */
894#define M8xx_BR_PS16 (2<<10) /* 16 bit port */
895#define M8xx_BR_PS32 (0<<10) /* 32 bit port */
896#define M8xx_BR_PARE (1<<9) /* Parity checking enable */
897#define M8xx_BR_WP (1<<8) /* Write protect */
898#define M8xx_BR_MS_GPCM (0<<6) /* GPCM */
899#define M8xx_BR_MS_UPMA (2<<6) /* UPM A */
900#define M8xx_BR_MS_UPMB (3<<6) /* UPM B */
901#define M8xx_MEMC_BR_V (1<<0) /* Base/Option register are valid */
902
903#define M8xx_MEMC_OR_32K 0xffff8000 /* Address range */
904#define M8xx_MEMC_OR_64K 0xffff0000
905#define M8xx_MEMC_OR_128K 0xfffe0000
906#define M8xx_MEMC_OR_256K 0xfffc0000
907#define M8xx_MEMC_OR_512K 0xfff80000
908#define M8xx_MEMC_OR_1M 0xfff00000
909#define M8xx_MEMC_OR_2M 0xffe00000
910#define M8xx_MEMC_OR_4M 0xffc00000
911#define M8xx_MEMC_OR_8M 0xff800000
912#define M8xx_MEMC_OR_16M 0xff000000
913#define M8xx_MEMC_OR_32M 0xfe000000
914#define M8xx_MEMC_OR_64M 0xfc000000
915#define M8xx_MEMC_OR_128 0xf8000000
916#define M8xx_MEMC_OR_256M 0xf0000000
917#define M8xx_MEMC_OR_512M 0xe0000000
918#define M8xx_MEMC_OR_1G 0xc0000000
919#define M8xx_MEMC_OR_2G 0x80000000
920#define M8xx_MEMC_OR_4G 0x00000000
921#define M8xx_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
922#define M8xx_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
923#define M8xx_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */
924#define M8xx_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */
925#define M8xx_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */
926#define M8xx_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */
927#define M8xx_MEMC_OR_BI (1<<8) /* Burst inhibit */
928#define M8xx_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
929#define M8xx_MEMC_OR_SETA (1<<3) /* *TA generated externally */
930#define M8xx_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */
931#define M8xx_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */
932
933/*
934*************************************************************************
935* UPM Registers (MxMR) *
936*************************************************************************
937*/
938#define M8xx_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */
939#define M8xx_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */
940#define M8xx_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */
941#define M8xx_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */
942#define M8xx_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */
943#define M8xx_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */
944#define M8xx_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */
945#define M8xx_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */
946/*
947*************************************************************************
948* Memory Command Register (MCR) *
949*************************************************************************
950*/
951#define M8xx_MEMC_MCR_WRITE (0<<30) /* WRITE command */
952#define M8xx_MEMC_MCR_READ (1<<30) /* READ command */
953#define M8xx_MEMC_MCR_RUN (2<<30) /* RUN command */
954#define M8xx_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */
955#define M8xx_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */
956#define M8xx_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */
957#define M8xx_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */
958#define M8xx_MEMC_MCR_MAD(x) (x) /* Machine address */
959
960
961
962/*
963*************************************************************************
964* SI Mode Register (SIMODE) *
965*************************************************************************
966*/
967#define M8xx_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
968#define M8xx_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
969#define M8xx_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
970#define M8xx_SI_SMC2_BRG2 (1<<28)
971#define M8xx_SI_SMC2_BRG3 (2<<28)
972#define M8xx_SI_SMC2_BRG4 (3<<28)
973#define M8xx_SI_SMC2_CLK5 (0<<28)
974#define M8xx_SI_SMC2_CLK6 (1<<28)
975#define M8xx_SI_SMC2_CLK7 (2<<28)
976#define M8xx_SI_SMC2_CLK8 (3<<28)
977#define M8xx_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
978#define M8xx_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
979#define M8xx_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
980#define M8xx_SI_SMC1_BRG2 (1<<12)
981#define M8xx_SI_SMC1_BRG3 (2<<12)
982#define M8xx_SI_SMC1_BRG4 (3<<12)
983#define M8xx_SI_SMC1_CLK1 (0<<12)
984#define M8xx_SI_SMC1_CLK2 (1<<12)
985#define M8xx_SI_SMC1_CLK3 (2<<12)
986#define M8xx_SI_SMC1_CLK4 (3<<12)
987
988/*
989*************************************************************************
990* SDMA Configuration Register (SDCR) *
991*************************************************************************
992*/
993#define M8xx_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */
994#define M8xx_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */
995
996/*
997*************************************************************************
998* SDMA Status Register (SDSR) *
999*************************************************************************
1000*/
1001#define M8xx_SDSR_SBER (1<<7) /* SDMA Channel bus error */
1002#define M8xx_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */
1003#define M8xx_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */
1004
1005/*
1006*************************************************************************
1007* Baud (sic) Rate Generators *
1008*************************************************************************
1009*/
1010#define M8xx_BRG_RST (1<<17) /* Reset generator */
1011#define M8xx_BRG_EN (1<<16) /* Enable generator */
1012#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
1013#define M8xx_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
1014#define M8xx_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
1015#define M8xx_BRG_ATB (1<<13) /* Autobaud */
1016#define M8xx_BRG_115200 (21<<1) /* Assume 40 MHz clock */
1017#define M8xx_BRG_57600 (32<<1)
1018#define M8xx_BRG_38400 (64<<1)
1019#define M8xx_BRG_19200 (129<<1)
1020#define M8xx_BRG_9600 (259<<1)
1021#define M8xx_BRG_4800 (520<<1)
1022#define M8xx_BRG_2400 (1040<<1)
1023#define M8xx_BRG_1200 (2082<<1)
1024#define M8xx_BRG_600 ((259<<1) | 1)
1025#define M8xx_BRG_300 ((520<<1) | 1)
1026#define M8xx_BRG_150 ((1040<<1) | 1)
1027#define M8xx_BRG_75 ((2080<<1) | 1)
1028
1029#define M8xx_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */
1030#define M8xx_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */
1031#define M8xx_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */
1032#define M8xx_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */
1033#define M8xx_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */
1034#define M8xx_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */
1035#define M8xx_TGCR_STP1 (1<<1) /* Stop timer */
1036#define M8xx_TGCR_STP2 (1<<5) /* Stop timer */
1037#define M8xx_TGCR_STP3 (1<<9) /* Stop timer */
1038#define M8xx_TGCR_STP4 (1<<13) /* Stop timer */
1039#define M8xx_TGCR_RST1 (1<<0) /* Enable timer */
1040#define M8xx_TGCR_RST2 (1<<4) /* Enable timer */
1041#define M8xx_TGCR_RST3 (1<<8) /* Enable timer */
1042#define M8xx_TGCR_RST4 (1<<12) /* Enable timer */
1043#define M8xx_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */
1044#define M8xx_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */
1045
1046#define M8xx_TMR_PS(x) ((x)<<8) /* Timer prescaler */
1047#define M8xx_TMR_CE_RISE (1<<6) /* Capture on rising edge */
1048#define M8xx_TMR_CE_FALL (2<<6) /* Capture on falling edge */
1049#define M8xx_TMR_CE_ANY (3<<6) /* Capture on any edge */
1050#define M8xx_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */
1051#define M8xx_TMR_ORI (1<<4) /* Interrupt on reaching reference */
1052#define M8xx_TMR_RESTART (1<<3) /* Restart timer after reference */
1053#define M8xx_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */
1054#define M8xx_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */
1055#define M8xx_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */
1056#define M8xx_TMR_TGATE (1<<0) /* TGATE controls timer */
1057
1058#define M8xx_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */
1059#define M8xx_PISCR_PS (1<<7) /* PIT Interrupt state */
1060#define M8xx_PISCR_PIE (1<<2) /* PIT interrupt enable */
1061#define M8xx_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */
1062#define M8xx_PISCR_PTE (1<<0) /* PIT enable */
1063
1064#define M8xx_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
1065#define M8xx_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
1066#define M8xx_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
1067#define M8xx_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
1068#define M8xx_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
1069#define M8xx_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
1070#define M8xx_TBSCR_TBE (1<<0) /* enable TB and decrementer */
1071
1072#define M8xx_SIMASK_IRM0 (1<<31)
1073#define M8xx_SIMASK_LVM0 (1<<30)
1074#define M8xx_SIMASK_IRM1 (1<<29)
1075#define M8xx_SIMASK_LVM1 (1<<28)
1076#define M8xx_SIMASK_IRM2 (1<<27)
1077#define M8xx_SIMASK_LVM2 (1<<26)
1078#define M8xx_SIMASK_IRM3 (1<<25)
1079#define M8xx_SIMASK_LVM3 (1<<24)
1080#define M8xx_SIMASK_IRM4 (1<<23)
1081#define M8xx_SIMASK_LVM4 (1<<22)
1082#define M8xx_SIMASK_IRM5 (1<<21)
1083#define M8xx_SIMASK_LVM5 (1<<20)
1084#define M8xx_SIMASK_IRM6 (1<<19)
1085#define M8xx_SIMASK_LVM6 (1<<18)
1086#define M8xx_SIMASK_IRM7 (1<<17)
1087#define M8xx_SIMASK_LVM7 (1<<16)
1088
1089#define M8xx_SIUMCR_EARB (1<<31)
1090#define M8xx_SIUMCR_EARP0 (0<<28)
1091#define M8xx_SIUMCR_EARP1 (1<<28)
1092#define M8xx_SIUMCR_EARP2 (2<<28)
1093#define M8xx_SIUMCR_EARP3 (3<<28)
1094#define M8xx_SIUMCR_EARP4 (4<<28)
1095#define M8xx_SIUMCR_EARP5 (5<<28)
1096#define M8xx_SIUMCR_EARP6 (6<<28)
1097#define M8xx_SIUMCR_EARP7 (7<<28)
1098#define M8xx_SIUMCR_DSHW (1<<23)
1099#define M8xx_SIUMCR_DBGC0 (0<<21)
1100#define M8xx_SIUMCR_DBGC1 (1<<21)
1101#define M8xx_SIUMCR_DBGC2 (2<<21)
1102#define M8xx_SIUMCR_DBGC3 (3<<21)
1103#define M8xx_SIUMCR_DBPC0 (0<<19)
1104#define M8xx_SIUMCR_DBPC1 (1<<19)
1105#define M8xx_SIUMCR_DBPC2 (2<<19)
1106#define M8xx_SIUMCR_DBPC3 (3<<19)
1107#define M8xx_SIUMCR_FRC (1<<17)
1108#define M8xx_SIUMCR_DLK (1<<16)
1109#define M8xx_SIUMCR_PNCS (1<<15)
1110#define M8xx_SIUMCR_OPAR (1<<14)
1111#define M8xx_SIUMCR_DPC (1<<13)
1112#define M8xx_SIUMCR_MPRE (1<<12)
1113#define M8xx_SIUMCR_MLRC0 (0<<10)
1114#define M8xx_SIUMCR_MLRC1 (1<<10)
1115#define M8xx_SIUMCR_MLRC2 (2<<10)
1116#define M8xx_SIUMCR_MLRC3 (3<<10)
1117#define M8xx_SIUMCR_AEME (1<<9)
1118#define M8xx_SIUMCR_SEME (1<<8)
1119#define M8xx_SIUMCR_BSC (1<<7)
1120#define M8xx_SIUMCR_GB5E (1<<6)
1121#define M8xx_SIUMCR_B2DD (1<<5)
1122#define M8xx_SIUMCR_B3DD (1<<4)
1123
1124/*
1125 * Value to write to a key register to unlock the corresponding SIU register
1126 */
1127#define M8xx_UNLOCK_KEY 0x55CCAA33
1128
1129/*
1130*************************************************************************
1131* MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) *
1132*************************************************************************
1133*/
1134typedef struct m8xx_ {
1135
1136 /*
1137 * SIU Block
1138 */
1139 uint32_t siumcr;
1140 uint32_t sypcr;
1141#if defined(mpc860)
1142 uint32_t swt;
1143#elif defined(mpc821)
1144 uint32_t _pad70;
1145#endif
1146 uint16_t _pad0;
1147 uint16_t swsr;
1148 uint32_t sipend;
1149 uint32_t simask;
1150 uint32_t siel;
1151 uint32_t sivec;
1152 uint32_t tesr;
1153 uint32_t _pad1[3];
1154 uint32_t sdcr;
1155 uint8_t _pad2[0x80-0x34];
1156
1157 /*
1158 * PCMCIA Block
1159 */
1160 uint32_t pbr0;
1161 uint32_t por0;
1162 uint32_t pbr1;
1163 uint32_t por1;
1164 uint32_t pbr2;
1165 uint32_t por2;
1166 uint32_t pbr3;
1167 uint32_t por3;
1168 uint32_t pbr4;
1169 uint32_t por4;
1170 uint32_t pbr5;
1171 uint32_t por5;
1172 uint32_t pbr6;
1173 uint32_t por6;
1174 uint32_t pbr7;
1175 uint32_t por7;
1176 uint8_t _pad3[0xe0-0xc0];
1177 uint32_t pgcra;
1178 uint32_t pgcrb;
1179 uint32_t pscr;
1180 uint32_t _pad4;
1181 uint32_t pipr;
1182 uint32_t _pad5;
1183 uint32_t per;
1184 uint32_t _pad6;
1185
1186 /*
1187 * MEMC Block
1188 */
1189 m8xxMEMCRegisters_t memc[8];
1190 uint8_t _pad7[0x164-0x140];
1191 uint32_t mar;
1192 uint32_t mcr;
1193 uint32_t _pad8;
1194 uint32_t mamr;
1195 uint32_t mbmr;
1196 uint16_t mstat;
1197 uint16_t mptpr;
1198 uint32_t mdr;
1199 uint8_t _pad9[0x200-0x180];
1200
1201 /*
1202 * System integration timers
1203 */
1204 uint16_t tbscr;
1205 uint16_t _pad10;
1206 uint32_t tbreff0;
1207 uint32_t tbreff1;
1208 uint8_t _pad11[0x220-0x20c];
1209 uint16_t rtcsc;
1210 uint16_t _pad12;
1211 uint32_t rtc;
1212 uint32_t rtsec;
1213 uint32_t rtcal;
1214 uint32_t _pad13[4];
1215 uint16_t piscr;
1216 uint16_t _pad14;
1217 uint16_t pitc;
1218 uint16_t _pad_14_1;
1219 uint16_t pitr;
1220 uint16_t _pad_14_2;
1221 uint8_t _pad15[0x280-0x24c];
1222
1223
1224 /*
1225 * Clocks and Reset
1226 */
1227 uint32_t sccr;
1228 uint32_t plprcr;
1229 uint32_t rsr;
1230 uint8_t _pad16[0x300-0x28c];
1231
1232
1233 /*
1234 * System integration timers keys
1235 */
1236 uint32_t tbscrk;
1237 uint32_t tbreff0k;
1238 uint32_t tbreff1k;
1239 uint32_t tbk;
1240 uint32_t _pad17[4];
1241 uint32_t rtcsk;
1242 uint32_t rtck;
1243 uint32_t rtseck;
1244 uint32_t rtcalk;
1245 uint32_t _pad18[4];
1246 uint32_t piscrk;
1247 uint32_t pitck;
1248 uint8_t _pad19[0x380-0x348];
1249
1250 /*
1251 * Clocks and Reset Keys
1252 */
1253 uint32_t sccrk;
1254 uint32_t plprck;
1255 uint32_t rsrk;
1256 uint8_t _pad20[0x400-0x38c];
1257 uint8_t _pad21[0x800-0x400];
1258 uint8_t _pad22[0x860-0x800];
1259
1260
1261 /*
1262 * I2C
1263 */
1264 uint8_t i2mod;
1265 uint8_t _pad23[3];
1266 uint8_t i2add;
1267 uint8_t _pad24[3];
1268 uint8_t i2brg;
1269 uint8_t _pad25[3];
1270 uint8_t i2com;
1271 uint8_t _pad26[3];
1272 uint8_t i2cer;
1273 uint8_t _pad27[3];
1274 uint8_t i2cmr;
1275 uint8_t _pad28[0x900-0x875];
1276
1277 /*
1278 * DMA Block
1279 */
1280 uint32_t _pad29;
1281 uint32_t sdar;
1282 uint8_t sdsr;
1283 uint8_t _pad30[3];
1284 uint8_t sdmr;
1285 uint8_t _pad31[3];
1286 uint8_t idsr1;
1287 uint8_t _pad32[3];
1288 uint8_t idmr1;
1289 uint8_t _pad33[3];
1290 uint8_t idsr2;
1291 uint8_t _pad34[3];
1292 uint8_t idmr2;
1293 uint8_t _pad35[0x930-0x91d];
1294
1295 /*
1296 * CPM Interrupt Control Block
1297 */
1298 uint16_t civr;
1299 uint8_t _pad36[14];
1300 uint32_t cicr;
1301 uint32_t cipr;
1302 uint32_t cimr;
1303 uint32_t cisr;
1304
1305 /*
1306 * I/O Port Block
1307 */
1308 uint16_t padir;
1309 uint16_t papar;
1310 uint16_t paodr;
1311 uint16_t padat;
1312 uint8_t _pad37[8];
1313 uint16_t pcdir;
1314 uint16_t pcpar;
1315 uint16_t pcso;
1316 uint16_t pcdat;
1317 uint16_t pcint;
1318 uint8_t _pad39[6];
1319 uint16_t pddir;
1320 uint16_t pdpar;
1321 uint16_t _pad40;
1322 uint16_t pddat;
1323 uint8_t _pad41[8];
1324
1325 /*
1326 * CPM Timers Block
1327 */
1328 uint16_t tgcr;
1329 uint8_t _pad42[14];
1330 uint16_t tmr1;
1331 uint16_t tmr2;
1332 uint16_t trr1;
1333 uint16_t trr2;
1334 uint16_t tcr1;
1335 uint16_t tcr2;
1336 uint16_t tcn1;
1337 uint16_t tcn2;
1338 uint16_t tmr3;
1339 uint16_t tmr4;
1340 uint16_t trr3;
1341 uint16_t trr4;
1342 uint16_t tcr3;
1343 uint16_t tcr4;
1344 uint16_t tcn3;
1345 uint16_t tcn4;
1346 uint16_t ter1;
1347 uint16_t ter2;
1348 uint16_t ter3;
1349 uint16_t ter4;
1350 uint8_t _pad43[8];
1351
1352 /*
1353 * CPM Block
1354 */
1355 uint16_t cpcr;
1356 uint16_t _pad44;
1357 uint16_t rccr;
1358 uint8_t _pad45;
1359 uint8_t rmds;
1360 uint32_t rmdr;
1361 uint16_t rctr1;
1362 uint16_t rctr2;
1363 uint16_t rctr3;
1364 uint16_t rctr4;
1365 uint16_t _pad46;
1366 uint16_t rter;
1367 uint16_t _pad47;
1368 uint16_t rtmr;
1369 uint8_t _pad48[0x9f0-0x9dc];
1370
1371 /*
1372 * BRG Block
1373 */
1374 uint32_t brgc1;
1375 uint32_t brgc2;
1376 uint32_t brgc3;
1377 uint32_t brgc4;
1378
1379 /*
1380 * SCC Block
1381 */
1382 m8xxSCCRegisters_t scc1;
1383 m8xxSCCRegisters_t scc2;
1384#if defined(mpc860)
1385 m8xxSCCRegisters_t scc3;
1386 m8xxSCCRegisters_t scc4;
1387#elif defined(mpc821)
1388 uint8_t _pad72[0xa80-0xa40];
1389#endif
1390
1391 /*
1392 * SMC Block
1393 */
1394 m8xxSMCRegisters_t smc1;
1395 m8xxSMCRegisters_t smc2;
1396
1397 /*
1398 * SPI Block
1399 */
1400 uint16_t spmode;
1401 uint16_t _pad49[2];
1402 uint8_t spie;
1403 uint8_t _pad50;
1404 uint16_t _pad51;
1405 uint8_t spim;
1406 uint8_t _pad52[2];
1407 uint8_t spcom;
1408 uint16_t _pad53[2];
1409
1410 /*
1411 * PIP Block
1412 */
1413 uint16_t pipc;
1414 uint16_t _pad54;
1415 uint16_t ptpr;
1416 uint32_t pbdir;
1417 uint32_t pbpar;
1418 uint16_t _pad55;
1419 uint16_t pbodr;
1420 uint32_t pbdat;
1421 uint32_t _pad56[6];
1422
1423 /*
1424 * SI Block
1425 */
1426 uint32_t simode;
1427 uint8_t sigmr;
1428 uint8_t _pad57;
1429 uint8_t sistr;
1430 uint8_t sicmr;
1431 uint32_t _pad58;
1432 uint32_t sicr;
1433 uint16_t sirp[2];
1434 uint32_t _pad59[3];
1435 uint8_t _pad60[0xc00-0xb00];
1436 uint8_t siram[512];
1437#if defined(mpc860)
1438 /*
1439 * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC)
1440 */
1441 m8xxFECRegisters_t fec;
1442#elif defined(mpc821)
1443 uint8_t lcdram[512];
1444#endif
1445 uint8_t _pad62[0x2000-0x1000];
1446
1447 /*
1448 * Dual-port RAM
1449 */
1450 uint8_t dpram0[0x200]; /* BD/DATA/UCODE */
1451 uint8_t dpram1[0x200]; /* BD/DATA/UCODE */
1452 uint8_t dpram2[0x400]; /* BD/DATA/UCODE */
1453 uint8_t dpram3[0x600]; /* BD/DATA*/
1454 uint8_t dpram4[0x200]; /* BD/DATA/UCODE */
1455 uint8_t _pad63[0x3c00-0x3000];
1456
1457 /* When using SCC1 for ethernet, we lose the use of I2C since
1458 * their parameters would overlap. Motorola has a microcode
1459 * patch to move parameters around so that both can be used
1460 * together. It is available on their web site somewhere
1461 * under http://www.mot.com/mpc8xx. If ethernet is used on
1462 * one (or more) of the other SCCs, then other CPM features
1463 * will be unavailable:
1464 * SCC2 -> lose SPI
1465 * SCC3 -> lose SMC1
1466 * SCC4 -> lose SMC2
1467 * However, Ethernet only works on SCC1 on the 8xx.
1468 */
1469 m8xxSCCENparms_t scc1p;
1470 uint8_t _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)];
1471 m8xxMiscParms_t miscp;
1472 uint8_t _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)];
1473 m8xxIDMAparms_t idma1p;
1474 uint8_t _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)];
1475
1476 m8xxSCCparms_t scc2p;
1477 uint8_t _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)];
1478 m8xxSPIparms_t spip;
1479 uint8_t _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)];
1480 m8xxTimerParms_t tmp;
1481 uint8_t _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)];
1482 m8xxIDMAparms_t idma2p;
1483 uint8_t _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)];
1484
1485 m8xxSCCparms_t scc3p; /* Not available on MPC821 */
1486 uint8_t _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)];
1487 m8xxSMCparms_t smc1p;
1488 uint8_t _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)];
1489 m8xxDSPparms_t dsp1p;
1490 uint8_t _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)];
1491
1492 m8xxSCCparms_t scc4p; /* Not available on MPC821 */
1493 uint8_t _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)];
1494 m8xxSMCparms_t smc2p;
1495 uint8_t _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)];
1496 m8xxDSPparms_t dsp2p;
1497 uint8_t _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)];
1498} m8xx_t;
1499
1500extern volatile m8xx_t m8xx;
1501
1502#ifdef __cplusplus
1503}
1504#endif
1505
1506#endif /* ASM */
1507
1508#endif /* _MPC8XX_H */
fec
Definition 8xx_immap.h:334
m8xxBufferDescriptor_
Definition mpc8xx.h:676
m8xxDSPparms_
Definition mpc8xx.h:386
m8xxFECRegisters_
Definition mpc8xx.h:219
m8xxIDMABufferDescriptor_
Definition mpc8xx.h:732
m8xxIDMAparms_
Definition mpc8xx.h:361
m8xxMEMCRegisters_
Definition mpc8xx.h:178
m8xxMiscParms_
Definition mpc8xx.h:312
m8xxSCCENparms_
Definition mpc8xx.h:453
m8xxSCCRegisters_
Definition mpc8xx.h:186
m8xxSCCparms_
Definition mpc8xx.h:412
m8xxSMCRegisters_
Definition mpc8xx.h:204
m8xxSMCparms_
Definition mpc8xx.h:566
m8xxSPIparms_
Definition mpc8xx.h:626
m8xxTimerParms_
Definition mpc8xx.h:324
m8xx_
Definition mpc8xx.h:1134
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