clockdrv.c File Reference

#include <rtems.h>
#include <bsp/irq.h>
#include <bsp.h>
#include "../../../shared/dev/clock/clockimpl.h"

Macros
#define	CLOCK_VECTOR   TX4925_IRQ_TMR0
#define	TX4925_TIMER_INTERVAL_MODE   1
#define	TX4925_TIMER_PULSE_MODE   2
#define	TX4925_TIMER_MODE   TX4925_TIMER_INTERVAL_MODE
#define	TX4925_TIMER_INTERRUPT_FLAG   TIIS
#define	Clock_driver_support_initialize_hardware()
#define	Clock_driver_support_install_isr(_new)
#define	Clock_driver_support_at_tick(arg)
#define	Initialize_timer0_in_interval_mode()
#define	Initialize_timer0_in_pulse_mode()
#define	CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER

Detailed Description

Instantiate the clock driver shell.

Macro Definition Documentation

Clock_driver_support_at_tick

#define Clock_driver_support_at_tick

(

arg

)

Value:

do { \
  uint32_t interrupt_flag; \
  do { \
      int loop_count; \
      TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TISR, 0x0 );   \
          loop_count = 0; \
          do {   \
                \
              interrupt_flag = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TISR ) & TX4925_TIMER_INTERRUPT_FLAG; \
          } while (interrupt_flag && (++loop_count < 10));   \
  } while(interrupt_flag); \
} while(0)

Clock_driver_support_initialize_hardware

#define Clock_driver_support_initialize_hardware

(

void

)

Value:

Initialize_timer0_in_interval_mode()

Clock_driver_support_install_isr

#define Clock_driver_support_install_isr

(

_new

)

Value:

rtems_interrupt_handler_install( CLOCK_VECTOR, "clock", 0, _new, NULL )

Initialize_timer0_in_interval_mode

#define Initialize_timer0_in_interval_mode

(

)

Value:

do { \
  uint32_t temp; \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CCDR, 0x0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, TIMER_CLEAR_ENABLE_MASK );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRA, 0x30d40 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0xC0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DM0, 0x0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_LVL2, 0x1000000 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_MSK, 0x0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DEN, 0x1 );   \
  temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR );   \
  temp |= TIMER_INT_ENABLE_MASK; \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, temp ); \
} while(0)

Initialize_timer0_in_pulse_mode

#define Initialize_timer0_in_pulse_mode

(

)

Value:

do { \
  uint32_t temp; \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CCDR, 0x0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, FFI );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRA, 0x3e8 );   \
  \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRB, 0x30d40 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0xC1 );   \
\
    \
  temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_CFG_PCFG ); \
  temp = (temp & ~ SELCHI) | SELTMR0;   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_CFG_PCFG, temp ); \
\
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DM0, 0x0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_LVL2, 0x1000000 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_MSK, 0x0 );   \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DEN, 0x1 );   \
  temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR );   \
  temp |= TPIBE;    \
  TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, temp ); \
} while(0)