RTEMS
6.3
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bsps
m68k
gen68340
include
m68340.h
Go to the documentation of this file.
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/**********************************************************************
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* MC68340 C Header File *
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* *
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* Developed by : Motorola *
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* High Performance Embedded Systems Division *
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* Austin, TX *
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* Rectified by : Geoffroy Montel
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* g_montel@yahoo.com *
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* *
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**********************************************************************/
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typedef
volatile
unsigned
char
* portb;
/* 8-bit port */
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typedef
volatile
unsigned
short
* portw;
/* 16-bit port */
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typedef
volatile
unsigned
int
* portl;
/* 32-bit port */
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#define MBASE 0xEFFFF000
/* Module Base Address */
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/* not EFFFF000 due to a 68349
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hardware incompatibility */
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#define MBAR (*(portb) 0x0003FF00)
/* Module Base Addr Reg */
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#define MBAR1 (*(portb) 0x0003FF00)
/* Module Base Addr Reg 1 (MSW) */
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#define MBAR2 (*(portb) 0x0003FF02)
/* Module Base Addr Reg 2 (LSW) */
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/* System Integration Module */
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#define SIMMCR (*(portw) (MBASE+0x0000))
/* SIM Module Config Reg */
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#define SIMSYNCR (*(portw) (MBASE+0x0004))
/* SIM Clock Synth Cont Reg */
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#define SIMAVR (*(portb) (MBASE+0x0006))
/* SIM Autovector Reg */
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#define SIMRSR (*(portb) (MBASE+0x0007))
/* SIM Reset Status Reg */
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#define SIMPORTA (*(portb) (MBASE+0x0011))
/* SIM Port A Data Reg */
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#define SIMDDRA (*(portb) (MBASE+0x0013))
/* SIM Port A Data Dir Reg */
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#define SIMPPRA1 (*(portb) (MBASE+0x0015))
/* SIM Port A Pin Asm 1 Reg */
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#define SIMPPRA2 (*(portb) (MBASE+0x0017))
/* SIM Port A Pin Asm 2 Reg */
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#define SIMPORTB (*(portb) (MBASE+0x0019))
/* SIM Port B Data Reg */
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#define SIMPORTB1 (*(portb) (MBASE+0x001B))
/* SIM Port B Data Reg */
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#define SIMDDRB (*(portb) (MBASE+0x001D))
/* SIM Port B Data Dir Reg */
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#define SIMPPARB (*(portb) (MBASE+0x001F))
/* SIM Port B Pin Asm Reg */
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#define SIMSWIV (*(portb) (MBASE+0x0020))
/* SIM SW Interrupt Vector */
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#define SIMSYPCR (*(portb) (MBASE+0x0021))
/* SIM System Prot Cont Reg */
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#define SIMPICR (*(portw) (MBASE+0x0022))
/* SIM Period Intr Cont Reg */
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#define SIMPITR (*(portw) (MBASE+0x0024))
/* SIM Period Intr Tmg Reg */
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#define SIMSWSR (*(portb) (MBASE+0x0027))
/* SIM Software Service Reg */
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#define SIMCS0AM (*(portl) (MBASE+0x0040))
/* SIM Chp Sel 0 Addr Msk */
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#define SIMCS0AM1 (*(portw) (MBASE+0x0040))
/* SIM Chp Sel 0 Addr Msk 1 */
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#define SIMCS0AM2 (*(portw) (MBASE+0x0042))
/* SIM Chp Sel 0 Addr Msk 2 */
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#define SIMCS0BA (*(portl) (MBASE+0x0044))
/* SIM Chp Sel 0 Base Addr */
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#define SIMCS0BA1 (*(portw) (MBASE+0x0044))
/* SIM Chp Sel 0 Bas Addr 1 */
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#define SIMCS0BA2 (*(portw) (MBASE+0x0046))
/* SIM Chp Sel 0 Bas Addr 2 */
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#define SIMCS1AM (*(portl) (MBASE+0x0048))
/* SIM Chp Sel 1 Adress Msk */
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#define SIMCS1AM1 (*(portw) (MBASE+0x0048))
/* SIM Chp Sel 1 Addr Msk 1 */
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#define SIMCS1AM2 (*(portw) (MBASE+0x004A))
/* SIM Chp Sel 1 Addr Msk 2 */
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#define SIMCS1BA (*(portl) (MBASE+0x004C))
/* SIM Chp Sel 1 Base Addr */
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#define SIMCS1BA1 (*(portw) (MBASE+0x004C))
/* SIM Chp Sel 1 Bas Addr 1 */
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#define SIMCS1BA2 (*(portw) (MBASE+0x004E))
/* SIM Chp Sel 1 Bas Addr 2 */
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#define SIMCS2AM (*(portl) (MBASE+0x0050))
/* SIM Chp Sel 2 Addr Msk */
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#define SIMCS2AM1 (*(portw) (MBASE+0x0050))
/* SIM Chp Sel 2 Addr Msk 1 */
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#define SIMCS2AM2 (*(portw) (MBASE+0x0052))
/* SIM Chp Sel 2 Addr Msk 2 */
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#define SIMCS2BA (*(portl) (MBASE+0x0054))
/* SIM Chp Sel 2 Base Addr */
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#define SIMCS2BA1 (*(portw) (MBASE+0x0054))
/* SIM Chp Sel 2 Bas Addr 1 */
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#define SIMCS2BA2 (*(portw) (MBASE+0x0056))
/* SIM Chp Sel 2 Bas Addr 2 */
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#define SIMCS3AM (*(portl) (MBASE+0x0058))
/* SIM Chp Sel 3 Addr Msk */
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#define SIMCS3AM1 (*(portw) (MBASE+0x0058))
/* SIM Chp Sel 3 Addr Msk 1 */
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#define SIMCS3AM2 (*(portw) (MBASE+0x005A))
/* SIM Chp Sel 3 Addr Msk 2 */
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#define SIMCS3BA (*(portl) (MBASE+0x005C))
/* SIM Chp Sel 3 Base Addr */
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#define SIMCS3BA1 (*(portw) (MBASE+0x005C))
/* SIM Chp Sel 3 Bas Addr 1 */
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#define SIMCS3BA2 (*(portw) (MBASE+0x005E))
/* SIM Chp Sel 3 Bas Addr 2 */
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/* Dynamic Memory Access (DMA) Module */
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#define DMAMCR1 (*(portw) (MBASE+0x0780))
/* DMA Module Config Reg 1 */
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#define DMAINTR1 (*(portw) (MBASE+0x0784))
/* DMA Interrupt Reg 1 */
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#define DMACCR1 (*(portw) (MBASE+0x0788))
/* DMA Channel Cont Reg 1 */
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#define DMACSR1 (*(portb) (MBASE+0x078A))
/* DMA Channel Status Reg 1 */
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#define DMAFCR1 (*(portb) (MBASE+0x078B))
/* DMA Function Code Reg 1 */
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#define DMASAR1 (*(portl) (MBASE+0x078C))
/* DMA DMA Src Addr Reg 1 */
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#define DMADAR1 (*(portl) (MBASE+0x0790))
/* DMA Dest Addr Reg 1 */
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#define DMABTC1 (*(portb) (MBASE+0x079l))
/* DMA Byte Trans Cnt Reg 1 */
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#define DMAMCR2 (*(portw) (MBASE+0x07A0))
/* DMA Module Config Reg 2 */
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#define DMAINTR2 (*(portw) (MBASE+0x07A4))
/* DMA Interrupt Reg 2 */
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#define DMACCR2 (*(portw) (MBASE+0x07A8))
/* DMA Channel Cont Reg 2 */
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#define DMACSR2 (*(portb) (MBASE+0x07AA))
/* DMA Channel Status Reg 2 */
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#define DMAFCR2 (*(portb) (MBASE+0x07AB))
/* DMA Function Code Reg 1 */
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#define DMASAR2 (*(portl) (MBASE+0x07AC))
/* DMA Source Addr Reg 2 */
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#define DMADAR2 (*(portl) (MBASE+0x07B0))
/* DMA Dest Addr Reg 2 */
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#define DMABTC2 (*(portb) (MBASE+0x07B4))
/* DMA Byte Trans Cnt Reg 2 */
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/* Dual Serial Module */
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#define DUMCRH (*(portb) (MBASE+0x0700))
/* DUART Module Config Reg */
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#define DUMCRL (*(portb) (MBASE+0x0701))
/* DUART Module Config Reg */
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#define DUILR (*(portb) (MBASE+0x0704))
/* DUART Interrupt Level */
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#define DUIVR (*(portb) (MBASE+0x0705))
/* DUART Interrupt Vector */
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#define DUMR1A (*(portb) (MBASE+0x0710))
/* DUART Mode Reg 1A */
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#define DUSRA (*(portb) (MBASE+0x0711))
/* DUART Status Reg A */
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#define DUCSRA (*(portb) (MBASE+0x0711))
/* DUART Clock Sel Reg A */
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#define DUCRA (*(portb) (MBASE+0x0712))
/* DUART Command Reg A */
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#define DURBA (*(portb) (MBASE+0x0713))
/* DUART Receiver Buffer A */
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#define DUTBA (*(portb) (MBASE+0x0713))
/* DUART Transmitter Buff A */
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#define DUIPCR (*(portb) (MBASE+0x0714))
/* DUART Input Port Chg Reg */
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#define DUACR (*(portb) (MBASE+0x0714))
/* DUART Auxiliary Cont Reg */
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#define DUISR (*(portb) (MBASE+0x0715))
/* DUART Interrupt Stat Reg */
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#define DUIER (*(portb) (MBASE+0x0715))
/* DUART Interrupt Enb Reg */
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#define DUMR1B (*(portb) (MBASE+0x0718))
/* DUART Mode Reg 1B */
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#define DUSRB (*(portb) (MBASE+0x0719))
/* DUART Status Reg B */
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#define DUCSRB (*(portb) (MBASE+0x0719))
/* DUART Clock Sel Reg B */
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#define DUCRB (*(portb) (MBASE+0x071A))
/* DUART Command Reg B */
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#define DURBB (*(portb) (MBASE+0x071B))
/* DUART Receiver Buffer B */
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#define DUTBB (*(portb) (MBASE+0x071B))
/* DUART Transmitter Buff B */
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#define DUIP (*(portb) (MBASE+0x071D))
/* DUART Input Port Reg */
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#define DUOPCR (*(portb) (MBASE+0x071D))
/* DUART Outp Port Cnt Reg */
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#define DUOPBS (*(portb) (MBASE+0x071E))
/* DUART Outp Port Bit Set */
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#define DUOPBR (*(portb) (MBASE+0x071F))
/* DUART Outp Port Bit Rst */
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#define DUMR2A (*(portb) (MBASE+0x0720))
/* DUART Mode Reg 2A */
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#define DUMR2B (*(portb) (MBASE+0x0721))
/* DUART Mode Reg 2B */
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/* Dual Timer Module */
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#define TMCR1 (*(portw) (MBASE+0x0600))
/* Timer Module Config Reg 1 */
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#define TIR1 (*(portw) (MBASE+0x0604))
/* Timer Interrupt Reg 1 */
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#define TCR1 (*(portw) (MBASE+0x0606))
/* Timer Control Reg 1 */
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#define TSR1 (*(portw) (MBASE+0x0608))
/* Timer Status Reg 1 */
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#define TCNTR1 (*(portw) (MBASE+0x060A))
/* Timer Counter Reg 1 */
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#define WPREL11 (*(portw) (MBASE+0x060C))
/* Timer Preload 1 Reg 1 */
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#define WPREL21 (*(portw) (MBASE+0x060E))
/* Timer Preload 2 Reg 1 */
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#define TCOM1 (*(portw) (MBASE+0x0610))
/* Timer Compare Reg 1 */
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#define TMCR2 (*(portw) (MBASE+0x0640))
/* Timer Module Config Reg 2 */
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#define TIR2 (*(portw) (MBASE+0x0644))
/* Timer Interrupt Reg 2 */
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#define TCR2 (*(portw) (MBASE+0x0646))
/* Timer Control Reg 2 */
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#define TSR2 (*(portw) (MBASE+0x0648))
/* Timer Status Reg 2 */
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#define TCNTR2 (*(portw) (MBASE+0x064A))
/* Timer Counter Reg 2 */
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#define WPREL12 (*(portw) (MBASE+0x064C))
/* Timer Preload 1 Reg 2 */
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#define WPREL22 (*(portw) (MBASE+0x064E))
/* Timer Preload 2 Reg 2 */
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#define TCOM2 (*(portw) (MBASE+0x0650))
/* Timer Compare Reg 2 */
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