hwinit-ls3137-hdk.c File Reference

This source file contains parts of the system initialization. More...

#include <bsp/tms570.h>
#include <bsp/tms570_hwinit.h>
#include <bsp/tms570-pinmux.h>

Macros
#define	TMS570_PINMMR_INIT_LIST(per_pin_action, common_arg)

Enumerations
enum	tms570_system_clock_source {   TMS570_SYS_CLK_SRC_OSC = 0U , TMS570_SYS_CLK_SRC_PLL1 = 1U , TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U , TMS570_SYS_CLK_SRC_LPO_LOW = 4U ,   TMS570_SYS_CLK_SRC_LPO_HIGH = 5U , TMS570_SYS_CLK_SRC_PLL2 = 6U , TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U , TMS570_SYS_CLK_SRC_VCLK = 9U }

Functions
void	tms570_pinmux_init (void)
	setups pin multiplexer according to precomputed registers values (HCG:muxInit)
void	tms570_emif_sdram_init (void)
	Initialize the External Memory InterFace (EMIF) peripheral.
void	tms570_pll_init (void)
	Setup all system PLLs (HCG:setupPLL).
void	tms570_map_clock_init (void)
	Setup chip clocks including to wait for PLLs locks (HCG:mapClocks).

Detailed Description

This source file contains parts of the system initialization.

Enumeration Type Documentation

tms570_system_clock_source

enum tms570_system_clock_source

Enumerator
TMS570_SYS_CLK_SRC_OSC	Alias for oscillator clock Source
TMS570_SYS_CLK_SRC_PLL1	Alias for Pll1 clock Source
TMS570_SYS_CLK_SRC_EXTERNAL1	Alias for external clock Source
TMS570_SYS_CLK_SRC_LPO_LOW	Alias for low power oscillator low clock Source
TMS570_SYS_CLK_SRC_LPO_HIGH	Alias for low power oscillator high clock Source
TMS570_SYS_CLK_SRC_PLL2	Alias for Pll2 clock Source
TMS570_SYS_CLK_SRC_EXTERNAL2	Alias for external 2 clock Source
TMS570_SYS_CLK_SRC_VCLK	Alias for synchronous VCLK1 clock Source

Function Documentation

tms570_map_clock_init()

void tms570_map_clock_init

(

void

)

Setup chip clocks including to wait for PLLs locks (HCG:mapClocks).

Initialize the tms570 Global Clock Manager (GCM) registers which sub-divide the input clock source (generally PLL) into the various peripheral clocks (VCLK1-3, etc).

Initialize Clock Tree:

• Disable / Enable clock domain

• Wait for until clocks are locked

• Map device clock domains to desired sources and configure top-level dividers

• All clock domains are working off the default clock sources until now

• The below assignments can be easily modified using the HALCoGen GUI

• Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup

• Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3

• Setup RTICLK1 and RTICLK2 clocks

• Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2

Initialize Clock Tree:

• Disable / Enable clock domain

• Setup RTICLK1 and RTICLK2 clocks

• Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2

• Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3

tms570_pinmux_init()

void tms570_pinmux_init

(

void

)

setups pin multiplexer according to precomputed registers values (HCG:muxInit)

Initialize the tms570 PINMUX peripheral. This maps signals to pin terminals.

• set ECLK pins functional mode

• set ECLK pins default output value

• set ECLK pins output direction

• set ECLK pins open drain enable

• set ECLK pins pullup/pulldown enable

• set ECLK pins pullup/pulldown select

• Setup ECLK

tms570_pll_init()

void tms570_pll_init

(

void

)

Setup all system PLLs (HCG:setupPLL).

Initialize PLLs source divider/multipliers.

Setup all system PLLs (HCG:setupPLL).

Initialize PLLs source divider/multipliers.

• Configure PLL control registers

Initialize Pll1:

Initialize Pll2:

• Enable PLL(s) to start up or Lock
• Setup pll control register 1:
• Disable reset on oscillator slip (ROS)
• Enable bypass on pll slip TODO: desired: switches to OSC when PLL slip detected
• setup Pll output clock divider to max before Lock
• Disable reset on oscillator fail
• Setup reference clock divider
• Setup Pll multiplier
• PLL1: 16MHz OSC in -> 300MHz PLL1 out

• Setup pll control register 2
• Setup spreading rate
• Setup bandwidth adjustment
• Setup internal Pll output divider
• Setup spreading amount

• Setup pll2 control register :
• setup Pll output clock divider to max before Lock
• Setup reference clock divider
• Setup internal Pll output divider
• Setup Pll multiplier