|
|
#define | GRSPWROUTER_RTRCFG_SP_SHIFT 27 |
|
#define | GRSPWROUTER_RTRCFG_SP_MASK 0xf8000000U |
| #define | GRSPWROUTER_RTRCFG_SP_GET(_reg) |
| #define | GRSPWROUTER_RTRCFG_SP_SET(_reg, _val) |
| #define | GRSPWROUTER_RTRCFG_SP(_val) |
|
#define | GRSPWROUTER_RTRCFG_AP_SHIFT 22 |
|
#define | GRSPWROUTER_RTRCFG_AP_MASK 0x7c00000U |
| #define | GRSPWROUTER_RTRCFG_AP_GET(_reg) |
| #define | GRSPWROUTER_RTRCFG_AP_SET(_reg, _val) |
| #define | GRSPWROUTER_RTRCFG_AP(_val) |
|
#define | GRSPWROUTER_RTRCFG_FP_SHIFT 17 |
|
#define | GRSPWROUTER_RTRCFG_FP_MASK 0x3e0000U |
| #define | GRSPWROUTER_RTRCFG_FP_GET(_reg) |
| #define | GRSPWROUTER_RTRCFG_FP_SET(_reg, _val) |
| #define | GRSPWROUTER_RTRCFG_FP(_val) |
|
#define | GRSPWROUTER_RTRCFG_R 0x10000U |
|
#define | GRSPWROUTER_RTRCFG_R 0x20U |
|
#define | GRSPWROUTER_RTRCFG_SR 0x8000U |
|
#define | GRSPWROUTER_RTRCFG_PE 0x4000U |
|
#define | GRSPWROUTER_RTRCFG_IC 0x2000U |
|
#define | GRSPWROUTER_RTRCFG_IS 0x1000U |
|
#define | GRSPWROUTER_RTRCFG_IP 0x800U |
|
#define | GRSPWROUTER_RTRCFG_AI 0x400U |
|
#define | GRSPWROUTER_RTRCFG_AT 0x200U |
|
#define | GRSPWROUTER_RTRCFG_IE 0x100U |
|
#define | GRSPWROUTER_RTRCFG_RE 0x80U |
|
#define | GRSPWROUTER_RTRCFG_EE 0x40U |
|
#define | GRSPWROUTER_RTRCFG_SA 0x10U |
|
#define | GRSPWROUTER_RTRCFG_TF 0x8U |
|
#define | GRSPWROUTER_RTRCFG_RM 0x4U |
|
#define | GRSPWROUTER_RTRCFG_TA 0x2U |
|
#define | GRSPWROUTER_RTRCFG_PP 0x1U |
This group contains register bit definitions.