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RTEMS 6.3
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This group contains register bit definitions. More...
Macros | |
| #define | SPWTDP_CONF3_STM_SHIFT 16 |
| #define | SPWTDP_CONF3_STM_MASK 0x3f0000U |
| #define | SPWTDP_CONF3_STM_GET(_reg) |
| #define | SPWTDP_CONF3_STM_SET(_reg, _val) |
| #define | SPWTDP_CONF3_STM(_val) |
| #define | SPWTDP_CONF3_DI64R 0x2000U |
| #define | SPWTDP_CONF3_DI64T 0x1000U |
| #define | SPWTDP_CONF3_DI64 0x800U |
| #define | SPWTDP_CONF3_DI 0x400U |
| #define | SPWTDP_CONF3_INRX_SHIFT 5 |
| #define | SPWTDP_CONF3_INRX_MASK 0x3e0U |
| #define | SPWTDP_CONF3_INRX_GET(_reg) |
| #define | SPWTDP_CONF3_INRX_SET(_reg, _val) |
| #define | SPWTDP_CONF3_INRX(_val) |
| #define | SPWTDP_CONF3_INTX_SHIFT 0 |
| #define | SPWTDP_CONF3_INTX_MASK 0x1fU |
| #define | SPWTDP_CONF3_INTX_GET(_reg) |
| #define | SPWTDP_CONF3_INTX_SET(_reg, _val) |
| #define | SPWTDP_CONF3_INTX(_val) |
This group contains register bit definitions.
| #define SPWTDP_CONF3_INRX | ( | _val | ) |
| #define SPWTDP_CONF3_INRX_GET | ( | _reg | ) |
| #define SPWTDP_CONF3_INRX_SET | ( | _reg, | |
| _val ) |
| #define SPWTDP_CONF3_INTX | ( | _val | ) |
| #define SPWTDP_CONF3_INTX_GET | ( | _reg | ) |
| #define SPWTDP_CONF3_INTX_SET | ( | _reg, | |
| _val ) |
| #define SPWTDP_CONF3_STM | ( | _val | ) |
| #define SPWTDP_CONF3_STM_GET | ( | _reg | ) |
| #define SPWTDP_CONF3_STM_SET | ( | _reg, | |
| _val ) |