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RTEMS 6.3
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This group contains register bit definitions. More...
Macros | |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT 24 |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK 0xff000000U |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_0_GET(_reg) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_0_SET(_reg, _val) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_0(_val) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT 16 |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK 0xff0000U |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_1_GET(_reg) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_1_SET(_reg, _val) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_1(_val) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT 8 |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK 0xff00U |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_2_GET(_reg) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_2_SET(_reg, _val) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_2(_val) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT 0 |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK 0xffU |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_3_GET(_reg) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_3_SET(_reg, _val) |
| #define | IRQAMP_IRQMAP_IRQMAP_4_N_3(_val) |
This group contains register bit definitions.
| #define IRQAMP_IRQMAP_IRQMAP_4_N_0 | ( | _val | ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_0_GET | ( | _reg | ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_0_SET | ( | _reg, | |
| _val ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_1 | ( | _val | ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_1_GET | ( | _reg | ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_1_SET | ( | _reg, | |
| _val ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_2 | ( | _val | ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_2_GET | ( | _reg | ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_2_SET | ( | _reg, | |
| _val ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_3 | ( | _val | ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_3_GET | ( | _reg | ) |
| #define IRQAMP_IRQMAP_IRQMAP_4_N_3_SET | ( | _reg, | |
| _val ) |