RTEMS 6.3
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Group control register 0 - 7 (GRPCTRL)

This group contains register bit definitions. More...

Macros

#define GRIOMMU_GRPCTRL_BASE_31_4_SHIFT   4
#define GRIOMMU_GRPCTRL_BASE_31_4_MASK   0xfffffff0U
#define GRIOMMU_GRPCTRL_BASE_31_4_GET(_reg)
#define GRIOMMU_GRPCTRL_BASE_31_4_SET(_reg, _val)
#define GRIOMMU_GRPCTRL_BASE_31_4(_val)
#define GRIOMMU_GRPCTRL_P   0x2U
#define GRIOMMU_GRPCTRL_AG   0x1U

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

◆ GRIOMMU_GRPCTRL_BASE_31_4

#define GRIOMMU_GRPCTRL_BASE_31_4 ( _val)
Value:
( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \
GRIOMMU_GRPCTRL_BASE_31_4_MASK )

◆ GRIOMMU_GRPCTRL_BASE_31_4_GET

#define GRIOMMU_GRPCTRL_BASE_31_4_GET ( _reg)
Value:
( ( ( _reg ) & GRIOMMU_GRPCTRL_BASE_31_4_MASK ) >> \
GRIOMMU_GRPCTRL_BASE_31_4_SHIFT )

◆ GRIOMMU_GRPCTRL_BASE_31_4_SET

#define GRIOMMU_GRPCTRL_BASE_31_4_SET ( _reg,
_val )
Value:
( ( ( _reg ) & ~GRIOMMU_GRPCTRL_BASE_31_4_MASK ) | \
( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \
GRIOMMU_GRPCTRL_BASE_31_4_MASK ) )