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RTEMS 6.3
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This group contains register bit definitions. More...
Macros | |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT 24 |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_0_GET(_reg) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_0_SET(_reg, _val) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_0(_val) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16 |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_1_GET(_reg) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_1_SET(_reg, _val) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_1(_val) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT 8 |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_2_GET(_reg) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_2_SET(_reg, _val) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_2(_val) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT 0 |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_3_GET(_reg) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_3_SET(_reg, _val) |
| #define | GRGPIO_IRQMAPR_IRQMAP_I_3(_val) |
This group contains register bit definitions.
| #define GRGPIO_IRQMAPR_IRQMAP_I_0 | ( | _val | ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_0_GET | ( | _reg | ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_0_SET | ( | _reg, | |
| _val ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_1 | ( | _val | ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_1_GET | ( | _reg | ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_1_SET | ( | _reg, | |
| _val ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_2 | ( | _val | ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_2_GET | ( | _reg | ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_2_SET | ( | _reg, | |
| _val ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_3 | ( | _val | ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_3_GET | ( | _reg | ) |
| #define GRGPIO_IRQMAPR_IRQMAP_I_3_SET | ( | _reg, | |
| _val ) |