![]() |
RTEMS 6.3
|
This group contains register bit definitions. More...
Macros | |
| #define | GR1553B_RTSW_BITW_SHIFT 16 |
| #define | GR1553B_RTSW_BITW_MASK 0xffff0000U |
| #define | GR1553B_RTSW_BITW_GET(_reg) |
| #define | GR1553B_RTSW_BITW_SET(_reg, _val) |
| #define | GR1553B_RTSW_BITW(_val) |
| #define | GR1553B_RTSW_VECW_SHIFT 0 |
| #define | GR1553B_RTSW_VECW_MASK 0xffffU |
| #define | GR1553B_RTSW_VECW_GET(_reg) |
| #define | GR1553B_RTSW_VECW_SET(_reg, _val) |
| #define | GR1553B_RTSW_VECW(_val) |
This group contains register bit definitions.
| #define GR1553B_RTSW_BITW | ( | _val | ) |
| #define GR1553B_RTSW_BITW_GET | ( | _reg | ) |
| #define GR1553B_RTSW_BITW_SET | ( | _reg, | |
| _val ) |
| #define GR1553B_RTSW_VECW | ( | _val | ) |
| #define GR1553B_RTSW_VECW_GET | ( | _reg | ) |
| #define GR1553B_RTSW_VECW_SET | ( | _reg, | |
| _val ) |