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RTEMS 6.3
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This group contains register bit definitions. More...
Macros | |
| #define | GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT 27 |
| #define | GR740_IOPLL_PLLNEWCFG_SWTAG_MASK 0x18000000U |
| #define | GR740_IOPLL_PLLNEWCFG_SWTAG_GET(_reg) |
| #define | GR740_IOPLL_PLLNEWCFG_SWTAG_SET(_reg, _val) |
| #define | GR740_IOPLL_PLLNEWCFG_SWTAG(_val) |
| #define | GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT 18 |
| #define | GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK 0x7fc0000U |
| #define | GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_GET(_reg) |
| #define | GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SET(_reg, _val) |
| #define | GR740_IOPLL_PLLNEWCFG_SPWPLLCFG(_val) |
| #define | GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT 9 |
| #define | GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK 0x3fe00U |
| #define | GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_GET(_reg) |
| #define | GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SET(_reg, _val) |
| #define | GR740_IOPLL_PLLNEWCFG_MEMPLLCFG(_val) |
| #define | GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT 0 |
| #define | GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK 0x1ffU |
| #define | GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_GET(_reg) |
| #define | GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SET(_reg, _val) |
| #define | GR740_IOPLL_PLLNEWCFG_SYSPLLCFG(_val) |
This group contains register bit definitions.
| #define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG | ( | _val | ) |
| #define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_GET | ( | _reg | ) |
| #define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SET | ( | _reg, | |
| _val ) |
| #define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG | ( | _val | ) |
| #define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_GET | ( | _reg | ) |
| #define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SET | ( | _reg, | |
| _val ) |
| #define GR740_IOPLL_PLLNEWCFG_SWTAG | ( | _val | ) |
| #define GR740_IOPLL_PLLNEWCFG_SWTAG_GET | ( | _reg | ) |
| #define GR740_IOPLL_PLLNEWCFG_SWTAG_SET | ( | _reg, | |
| _val ) |
| #define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG | ( | _val | ) |
| #define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_GET | ( | _reg | ) |
| #define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SET | ( | _reg, | |
| _val ) |