RTEMS 6.3
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Macros

#define RCC_LPTIM345CLKSOURCE_SRDPCLK4   (0x00000000U)
#define RCC_LPTIM345CLKSOURCE_PCLK4   RCC_LPTIM345CLKSOURCE_SRDPCLK4
#define RCC_LPTIM345CLKSOURCE_D3PCLK1   RCC_LPTIM345CLKSOURCE_SRDPCLK4
#define RCC_LPTIM345CLKSOURCE_PLL2   RCC_SRDCCIPR_LPTIM3SEL_0
#define RCC_LPTIM345CLKSOURCE_PLL3   RCC_SRDCCIPR_LPTIM3SEL_1
#define RCC_LPTIM345CLKSOURCE_LSE   (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
#define RCC_LPTIM345CLKSOURCE_LSI   RCC_SRDCCIPR_LPTIM3SEL_2
#define RCC_LPTIM345CLKSOURCE_CLKP   (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

Detailed Description