RTEMS 6.3
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Macros
RCC Private macros to check input parameters
STM32H7xx_HAL_Driver | Board Support Packages » ARM » STM32H7 » RCCEx » RCCEx Private Macros | Board Support Packages » ARM » STM32H7

Macros

#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE)
#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE)
#define IS_RCC_USART16CLKSOURCE(SOURCE)
#define IS_RCC_USART16910CLKSOURCE   IS_RCC_USART16CLKSOURCE
#define IS_RCC_USART234578CLKSOURCE(SOURCE)
#define IS_RCC_USART1CLKSOURCE(SOURCE)
#define IS_RCC_USART2CLKSOURCE(SOURCE)
#define IS_RCC_USART3CLKSOURCE(SOURCE)
#define IS_RCC_UART4CLKSOURCE(SOURCE)
#define IS_RCC_UART5CLKSOURCE(SOURCE)
#define IS_RCC_USART6CLKSOURCE(SOURCE)
#define IS_RCC_UART7CLKSOURCE(SOURCE)
#define IS_RCC_UART8CLKSOURCE(SOURCE)
#define IS_RCC_LPUART1CLKSOURCE(SOURCE)
#define IS_RCC_I2C123CLKSOURCE(SOURCE)
#define IS_RCC_I2C1CLKSOURCE(SOURCE)
#define IS_RCC_I2C2CLKSOURCE(SOURCE)
#define IS_RCC_I2C3CLKSOURCE(SOURCE)
#define IS_RCC_I2C4CLKSOURCE(SOURCE)
#define IS_RCC_RNGCLKSOURCE(SOURCE)
#define IS_RCC_USBCLKSOURCE(SOURCE)
#define IS_RCC_SAI1CLK(__SOURCE__)
#define IS_RCC_SPI123CLK(__SOURCE__)
#define IS_RCC_SPI1CLK(__SOURCE__)
#define IS_RCC_SPI2CLK(__SOURCE__)
#define IS_RCC_SPI3CLK(__SOURCE__)
#define IS_RCC_SPI45CLK(__SOURCE__)
#define IS_RCC_SPI4CLK(__SOURCE__)
#define IS_RCC_SPI5CLK(__SOURCE__)
#define IS_RCC_SPI6CLK(__SOURCE__)
#define IS_RCC_PLL3M_VALUE(VALUE)
#define IS_RCC_PLL3N_VALUE(VALUE)
#define IS_RCC_PLL3P_VALUE(VALUE)
#define IS_RCC_PLL3Q_VALUE(VALUE)
#define IS_RCC_PLL3R_VALUE(VALUE)
#define IS_RCC_PLL2M_VALUE(VALUE)
#define IS_RCC_PLL2N_VALUE(VALUE)
#define IS_RCC_PLL2P_VALUE(VALUE)
#define IS_RCC_PLL2Q_VALUE(VALUE)
#define IS_RCC_PLL2R_VALUE(VALUE)
#define IS_RCC_PLL2RGE_VALUE(VALUE)
#define IS_RCC_PLL3RGE_VALUE(VALUE)
#define IS_RCC_PLL2VCO_VALUE(VALUE)
#define IS_RCC_PLL3VCO_VALUE(VALUE)
#define IS_RCC_LPTIM1CLK(SOURCE)
#define IS_RCC_LPTIM2CLK(SOURCE)
#define IS_RCC_LPTIM345CLK(SOURCE)
#define IS_RCC_LPTIM3CLK(SOURCE)
#define IS_RCC_FMCCLK(__SOURCE__)
#define IS_RCC_SDMMC(__SOURCE__)
#define IS_RCC_ADCCLKSOURCE(SOURCE)
#define IS_RCC_SWPMI1CLKSOURCE(SOURCE)
#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)
#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)
#define IS_RCC_CECCLKSOURCE(SOURCE)
#define IS_RCC_CLKPSOURCE(SOURCE)
#define IS_RCC_TIMPRES(VALUE)
#define IS_RCC_SCOPE_WWDG(WWDG)
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define IS_RCC_CRS_SYNC_DIV(__DIV__)
#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define IS_RCC_CRS_RELOADVALUE(__VALUE__)
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)
#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__)
#define IS_RCC_CRS_FREQERRORDIR(__DIR__)

Detailed Description

Macro Definition Documentation

◆ IS_RCC_ADCCLKSOURCE

#define IS_RCC_ADCCLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
((SOURCE) == RCC_ADCCLKSOURCE_CLKP))

◆ IS_RCC_CECCLKSOURCE

#define IS_RCC_CECCLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
((SOURCE) == RCC_CECCLKSOURCE_CSI))

◆ IS_RCC_CLKPSOURCE

#define IS_RCC_CLKPSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_CLKPSOURCE_HSI) || \
((SOURCE) == RCC_CLKPSOURCE_CSI) || \
((SOURCE) == RCC_CLKPSOURCE_HSE))

◆ IS_RCC_CRS_ERRORLIMIT

#define IS_RCC_CRS_ERRORLIMIT ( __VALUE__)
Value:
(((__VALUE__) <= 0xFFU))

◆ IS_RCC_CRS_FREQERRORDIR

#define IS_RCC_CRS_FREQERRORDIR ( __DIR__)
Value:
(((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
RCC_CRS_FREQERRORDIR_UP
#define RCC_CRS_FREQERRORDIR_UP
Definition stm32h7xx_hal_rcc_ex.h:1798
RCC_CRS_FREQERRORDIR_DOWN
#define RCC_CRS_FREQERRORDIR_DOWN
Definition stm32h7xx_hal_rcc_ex.h:1799

◆ IS_RCC_CRS_HSI48CALIBRATION

#define IS_RCC_CRS_HSI48CALIBRATION ( __VALUE__)
Value:
(((__VALUE__) <= 0x3FU))

◆ IS_RCC_CRS_RELOADVALUE

#define IS_RCC_CRS_RELOADVALUE ( __VALUE__)
Value:
(((__VALUE__) <= 0xFFFFU))

◆ IS_RCC_CRS_SYNC_DIV

#define IS_RCC_CRS_SYNC_DIV ( __DIV__)
Value:
(((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
RCC_CRS_SYNC_DIV128
#define RCC_CRS_SYNC_DIV128
Definition stm32h7xx_hal_rcc_ex.h:1749
RCC_CRS_SYNC_DIV32
#define RCC_CRS_SYNC_DIV32
Definition stm32h7xx_hal_rcc_ex.h:1747
RCC_CRS_SYNC_DIV2
#define RCC_CRS_SYNC_DIV2
Definition stm32h7xx_hal_rcc_ex.h:1743
RCC_CRS_SYNC_DIV1
#define RCC_CRS_SYNC_DIV1
Definition stm32h7xx_hal_rcc_ex.h:1742
RCC_CRS_SYNC_DIV16
#define RCC_CRS_SYNC_DIV16
Definition stm32h7xx_hal_rcc_ex.h:1746
RCC_CRS_SYNC_DIV4
#define RCC_CRS_SYNC_DIV4
Definition stm32h7xx_hal_rcc_ex.h:1744
RCC_CRS_SYNC_DIV8
#define RCC_CRS_SYNC_DIV8
Definition stm32h7xx_hal_rcc_ex.h:1745
RCC_CRS_SYNC_DIV64
#define RCC_CRS_SYNC_DIV64
Definition stm32h7xx_hal_rcc_ex.h:1748

◆ IS_RCC_CRS_SYNC_POLARITY

#define IS_RCC_CRS_SYNC_POLARITY ( __POLARITY__)
Value:
(((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
RCC_CRS_SYNC_POLARITY_RISING
#define RCC_CRS_SYNC_POLARITY_RISING
Definition stm32h7xx_hal_rcc_ex.h:1758
RCC_CRS_SYNC_POLARITY_FALLING
#define RCC_CRS_SYNC_POLARITY_FALLING
Definition stm32h7xx_hal_rcc_ex.h:1759

◆ IS_RCC_CRS_SYNC_SOURCE

#define IS_RCC_CRS_SYNC_SOURCE ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
RCC_CRS_SYNC_SOURCE_USB2
#define RCC_CRS_SYNC_SOURCE_USB2
Definition stm32h7xx_hal_rcc_ex.h:1731
RCC_CRS_SYNC_SOURCE_USB1
#define RCC_CRS_SYNC_SOURCE_USB1
Definition stm32h7xx_hal_rcc_ex.h:1730
RCC_CRS_SYNC_SOURCE_PIN
#define RCC_CRS_SYNC_SOURCE_PIN
Definition stm32h7xx_hal_rcc_ex.h:1728
RCC_CRS_SYNC_SOURCE_LSE
#define RCC_CRS_SYNC_SOURCE_LSE
Definition stm32h7xx_hal_rcc_ex.h:1729

◆ IS_RCC_DFSDM1CLKSOURCE

#define IS_RCC_DFSDM1CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))

◆ IS_RCC_FMCCLK

#define IS_RCC_FMCCLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \
((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))

◆ IS_RCC_I2C123CLKSOURCE

#define IS_RCC_I2C123CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \
((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \
((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_I2C123CLKSOURCE_CSI))

◆ IS_RCC_I2C1CLKSOURCE

#define IS_RCC_I2C1CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \
((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_I2C1CLKSOURCE_CSI))

◆ IS_RCC_I2C2CLKSOURCE

#define IS_RCC_I2C2CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \
((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_I2C2CLKSOURCE_CSI))

◆ IS_RCC_I2C3CLKSOURCE

#define IS_RCC_I2C3CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \
((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

◆ IS_RCC_I2C4CLKSOURCE

#define IS_RCC_I2C4CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \
((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \
((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
((SOURCE) == RCC_I2C4CLKSOURCE_CSI))

◆ IS_RCC_LPTIM1CLK

#define IS_RCC_LPTIM1CLK ( SOURCE)
Value:
(((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \
((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \
((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \
((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))

◆ IS_RCC_LPTIM2CLK

#define IS_RCC_LPTIM2CLK ( SOURCE)
Value:
(((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \
((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \
((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \
((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \
((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))

◆ IS_RCC_LPTIM345CLK

#define IS_RCC_LPTIM345CLK ( SOURCE)
Value:
(((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \
((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \
((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \
((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \
((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))

◆ IS_RCC_LPTIM3CLK

#define IS_RCC_LPTIM3CLK ( SOURCE)
Value:
(((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \
((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \
((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \
((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \
((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \
((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))

◆ IS_RCC_LPUART1CLKSOURCE

#define IS_RCC_LPUART1CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \
((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \
((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \
((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \
((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))

◆ IS_RCC_PLL2CLOCKOUT_VALUE

#define IS_RCC_PLL2CLOCKOUT_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL2_DIVP) || \
((VALUE) == RCC_PLL2_DIVQ) || \
((VALUE) == RCC_PLL2_DIVR))

◆ IS_RCC_PLL2M_VALUE

#define IS_RCC_PLL2M_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 63U))

◆ IS_RCC_PLL2N_VALUE

#define IS_RCC_PLL2N_VALUE ( VALUE)
Value:
((4U <= (VALUE)) && ((VALUE) <= 512U))

◆ IS_RCC_PLL2P_VALUE

#define IS_RCC_PLL2P_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLL2Q_VALUE

#define IS_RCC_PLL2Q_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLL2R_VALUE

#define IS_RCC_PLL2R_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLL2RGE_VALUE

#define IS_RCC_PLL2RGE_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL2VCIRANGE_0) || \
((VALUE) == RCC_PLL2VCIRANGE_1) || \
((VALUE) == RCC_PLL2VCIRANGE_2) || \
((VALUE) == RCC_PLL2VCIRANGE_3))
RCC_PLL2VCIRANGE_3
#define RCC_PLL2VCIRANGE_3
Definition stm32h7xx_hal_rcc_ex.h:502
RCC_PLL2VCIRANGE_2
#define RCC_PLL2VCIRANGE_2
Definition stm32h7xx_hal_rcc_ex.h:501
RCC_PLL2VCIRANGE_1
#define RCC_PLL2VCIRANGE_1
Definition stm32h7xx_hal_rcc_ex.h:500
RCC_PLL2VCIRANGE_0
#define RCC_PLL2VCIRANGE_0
Definition stm32h7xx_hal_rcc_ex.h:499

◆ IS_RCC_PLL2VCO_VALUE

#define IS_RCC_PLL2VCO_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL2VCOWIDE) || \
((VALUE) == RCC_PLL2VCOMEDIUM))

◆ IS_RCC_PLL3CLOCKOUT_VALUE

#define IS_RCC_PLL3CLOCKOUT_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL3_DIVP) || \
((VALUE) == RCC_PLL3_DIVQ) || \
((VALUE) == RCC_PLL3_DIVR))

◆ IS_RCC_PLL3M_VALUE

#define IS_RCC_PLL3M_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 63U))

◆ IS_RCC_PLL3N_VALUE

#define IS_RCC_PLL3N_VALUE ( VALUE)
Value:
((4U <= (VALUE)) && ((VALUE) <= 512U))

◆ IS_RCC_PLL3P_VALUE

#define IS_RCC_PLL3P_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLL3Q_VALUE

#define IS_RCC_PLL3Q_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLL3R_VALUE

#define IS_RCC_PLL3R_VALUE ( VALUE)
Value:
((1U <= (VALUE)) && ((VALUE) <= 128U))

◆ IS_RCC_PLL3RGE_VALUE

#define IS_RCC_PLL3RGE_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL3VCIRANGE_0) || \
((VALUE) == RCC_PLL3VCIRANGE_1) || \
((VALUE) == RCC_PLL3VCIRANGE_2) || \
((VALUE) == RCC_PLL3VCIRANGE_3))
RCC_PLL3VCIRANGE_0
#define RCC_PLL3VCIRANGE_0
Definition stm32h7xx_hal_rcc_ex.h:524
RCC_PLL3VCIRANGE_1
#define RCC_PLL3VCIRANGE_1
Definition stm32h7xx_hal_rcc_ex.h:525
RCC_PLL3VCIRANGE_2
#define RCC_PLL3VCIRANGE_2
Definition stm32h7xx_hal_rcc_ex.h:526
RCC_PLL3VCIRANGE_3
#define RCC_PLL3VCIRANGE_3
Definition stm32h7xx_hal_rcc_ex.h:527

◆ IS_RCC_PLL3VCO_VALUE

#define IS_RCC_PLL3VCO_VALUE ( VALUE)
Value:
(((VALUE) == RCC_PLL3VCOWIDE) || \
((VALUE) == RCC_PLL3VCOMEDIUM))

◆ IS_RCC_RNGCLKSOURCE

#define IS_RCC_RNGCLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \
((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \
((SOURCE) == RCC_RNGCLKSOURCE_LSI))

◆ IS_RCC_SAI1CLK

#define IS_RCC_SAI1CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))

◆ IS_RCC_SCOPE_WWDG

#define IS_RCC_SCOPE_WWDG ( WWDG)
Value:
((WWDG) == RCC_WWDG1)

◆ IS_RCC_SDMMC

#define IS_RCC_SDMMC ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))

◆ IS_RCC_SPDIFRXCLKSOURCE

#define IS_RCC_SPDIFRXCLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \
((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))

◆ IS_RCC_SPI123CLK

#define IS_RCC_SPI123CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))

◆ IS_RCC_SPI1CLK

#define IS_RCC_SPI1CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))

◆ IS_RCC_SPI2CLK

#define IS_RCC_SPI2CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))

◆ IS_RCC_SPI3CLK

#define IS_RCC_SPI3CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))

◆ IS_RCC_SPI45CLK

#define IS_RCC_SPI45CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || \
((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \
((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))

◆ IS_RCC_SPI4CLK

#define IS_RCC_SPI4CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || \
((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \
((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))

◆ IS_RCC_SPI5CLK

#define IS_RCC_SPI5CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \
((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \
((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))

◆ IS_RCC_SPI6CLK

#define IS_RCC_SPI6CLK ( __SOURCE__)
Value:
(((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \
((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \
((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))

◆ IS_RCC_SWPMI1CLKSOURCE

#define IS_RCC_SWPMI1CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))

◆ IS_RCC_TIMPRES

#define IS_RCC_TIMPRES ( VALUE)
Value:
(((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
((VALUE) == RCC_TIMPRES_ACTIVATED))

◆ IS_RCC_UART4CLKSOURCE

#define IS_RCC_UART4CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \
((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \
((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \
((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
((SOURCE) == RCC_UART4CLKSOURCE_HSI))

◆ IS_RCC_UART5CLKSOURCE

#define IS_RCC_UART5CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \
((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \
((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \
((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
((SOURCE) == RCC_UART5CLKSOURCE_HSI))

◆ IS_RCC_UART7CLKSOURCE

#define IS_RCC_UART7CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \
((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \
((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \
((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
((SOURCE) == RCC_UART7CLKSOURCE_HSI))

◆ IS_RCC_UART8CLKSOURCE

#define IS_RCC_UART8CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \
((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \
((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \
((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
((SOURCE) == RCC_UART8CLKSOURCE_HSI))

◆ IS_RCC_USART16CLKSOURCE

#define IS_RCC_USART16CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \
((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \
((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \
((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \
((SOURCE) == RCC_USART16CLKSOURCE_HSI))

◆ IS_RCC_USART1CLKSOURCE

#define IS_RCC_USART1CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \
((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \
((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \
((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
((SOURCE) == RCC_USART1CLKSOURCE_HSI))

◆ IS_RCC_USART234578CLKSOURCE

#define IS_RCC_USART234578CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \
((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \
((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \
((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \
((SOURCE) == RCC_USART234578CLKSOURCE_HSI))

◆ IS_RCC_USART2CLKSOURCE

#define IS_RCC_USART2CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \
((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \
((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \
((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
((SOURCE) == RCC_USART2CLKSOURCE_HSI))

◆ IS_RCC_USART3CLKSOURCE

#define IS_RCC_USART3CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \
((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \
((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \
((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
((SOURCE) == RCC_USART3CLKSOURCE_HSI))

◆ IS_RCC_USART6CLKSOURCE

#define IS_RCC_USART6CLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \
((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \
((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \
((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
((SOURCE) == RCC_USART6CLKSOURCE_HSI))

◆ IS_RCC_USBCLKSOURCE

#define IS_RCC_USBCLKSOURCE ( SOURCE)
Value:
(((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
((SOURCE) == RCC_USBCLKSOURCE_HSI48))
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