RTEMS 6.3
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OSC_RC_400M Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » OSC_RC_400M Peripheral Access Layer

CTRL0 - Control Register 0

#define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK   (0x3F000000U)
#define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT   (24U)
#define OSC_RC_400M_CTRL0_REF_CLK_DIV(x)
#define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK   (0x3F000000U)
#define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT   (24U)
#define OSC_RC_400M_CTRL0_REF_CLK_DIV(x)

CTRL1 - Control Register 1

#define OSC_RC_400M_CTRL1_HYST_MINUS_MASK   (0xFU)
#define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT   (0U)
#define OSC_RC_400M_CTRL1_HYST_MINUS(x)
#define OSC_RC_400M_CTRL1_HYST_PLUS_MASK   (0xF00U)
#define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT   (8U)
#define OSC_RC_400M_CTRL1_HYST_PLUS(x)
#define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK   (0xFFFF0000U)
#define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT   (16U)
#define OSC_RC_400M_CTRL1_TARGET_COUNT(x)
#define OSC_RC_400M_CTRL1_HYST_MINUS_MASK   (0xFU)
#define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT   (0U)
#define OSC_RC_400M_CTRL1_HYST_MINUS(x)
#define OSC_RC_400M_CTRL1_HYST_PLUS_MASK   (0xF00U)
#define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT   (8U)
#define OSC_RC_400M_CTRL1_HYST_PLUS(x)
#define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK   (0xFFFF0000U)
#define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT   (16U)
#define OSC_RC_400M_CTRL1_TARGET_COUNT(x)

CTRL2 - Control Register 2

#define OSC_RC_400M_CTRL2_TUNE_BYP_MASK   (0x400U)
#define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT   (10U)
#define OSC_RC_400M_CTRL2_TUNE_BYP(x)
#define OSC_RC_400M_CTRL2_TUNE_EN_MASK   (0x1000U)
#define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT   (12U)
#define OSC_RC_400M_CTRL2_TUNE_EN(x)
#define OSC_RC_400M_CTRL2_TUNE_START_MASK   (0x4000U)
#define OSC_RC_400M_CTRL2_TUNE_START_SHIFT   (14U)
#define OSC_RC_400M_CTRL2_TUNE_START(x)
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT   (24U)
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x)
#define OSC_RC_400M_CTRL2_TUNE_BYP_MASK   (0x400U)
#define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT   (10U)
#define OSC_RC_400M_CTRL2_TUNE_BYP(x)
#define OSC_RC_400M_CTRL2_TUNE_EN_MASK   (0x1000U)
#define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT   (12U)
#define OSC_RC_400M_CTRL2_TUNE_EN(x)
#define OSC_RC_400M_CTRL2_TUNE_START_MASK   (0x4000U)
#define OSC_RC_400M_CTRL2_TUNE_START_SHIFT   (14U)
#define OSC_RC_400M_CTRL2_TUNE_START(x)
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT   (24U)
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x)

CTRL3 - Control Register 3

#define OSC_RC_400M_CTRL3_CLR_ERR_MASK   (0x1U)
#define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT   (0U)
#define OSC_RC_400M_CTRL3_CLR_ERR(x)
#define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK   (0x100U)
#define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT   (8U)
#define OSC_RC_400M_CTRL3_EN_1M_CLK(x)
#define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK   (0x400U)
#define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT   (10U)
#define OSC_RC_400M_CTRL3_MUX_1M_CLK(x)
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK   (0xFFFF0000U)
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT   (16U)
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x)
#define OSC_RC_400M_CTRL3_CLR_ERR_MASK   (0x1U)
#define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT   (0U)
#define OSC_RC_400M_CTRL3_CLR_ERR(x)
#define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK   (0x100U)
#define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT   (8U)
#define OSC_RC_400M_CTRL3_EN_1M_CLK(x)
#define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK   (0x400U)
#define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT   (10U)
#define OSC_RC_400M_CTRL3_MUX_1M_CLK(x)
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK   (0xFFFF0000U)
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT   (16U)
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x)

STAT0 - Status Register 0

#define OSC_RC_400M_STAT0_CLK1M_ERR_MASK   (0x1U)
#define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT   (0U)
#define OSC_RC_400M_STAT0_CLK1M_ERR(x)
#define OSC_RC_400M_STAT0_CLK1M_ERR_MASK   (0x1U)
#define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT   (0U)
#define OSC_RC_400M_STAT0_CLK1M_ERR(x)

STAT1 - Status Register 1

#define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK   (0xFFFF0000U)
#define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT   (16U)
#define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x)
#define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK   (0xFFFF0000U)
#define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT   (16U)
#define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x)

STAT2 - Status Register 2

#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT   (24U)
#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x)
#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK   (0xFF000000U)
#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT   (24U)
#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x)

Detailed Description

Macro Definition Documentation

◆ OSC_RC_400M_CTRL0_REF_CLK_DIV [1/2]

#define OSC_RC_400M_CTRL0_REF_CLK_DIV ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK)

REF_CLK_DIV - Divide value for ref_clk to generate slow_clk (used inside this IP)

◆ OSC_RC_400M_CTRL0_REF_CLK_DIV [2/2]

#define OSC_RC_400M_CTRL0_REF_CLK_DIV ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK)

REF_CLK_DIV - Divide value for ref_clk to generate slow_clk (used inside this IP)

◆ OSC_RC_400M_CTRL1_HYST_MINUS [1/2]

#define OSC_RC_400M_CTRL1_HYST_MINUS ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK)

HYST_MINUS - Negative hysteresis value for the tuned clock

◆ OSC_RC_400M_CTRL1_HYST_MINUS [2/2]

#define OSC_RC_400M_CTRL1_HYST_MINUS ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK)

HYST_MINUS - Negative hysteresis value for the tuned clock

◆ OSC_RC_400M_CTRL1_HYST_PLUS [1/2]

#define OSC_RC_400M_CTRL1_HYST_PLUS ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK)

HYST_PLUS - Positive hysteresis value for the tuned clock

◆ OSC_RC_400M_CTRL1_HYST_PLUS [2/2]

#define OSC_RC_400M_CTRL1_HYST_PLUS ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK)

HYST_PLUS - Positive hysteresis value for the tuned clock

◆ OSC_RC_400M_CTRL1_TARGET_COUNT [1/2]

#define OSC_RC_400M_CTRL1_TARGET_COUNT ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK)

TARGET_COUNT - Target count for the fast clock

◆ OSC_RC_400M_CTRL1_TARGET_COUNT [2/2]

#define OSC_RC_400M_CTRL1_TARGET_COUNT ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK)

TARGET_COUNT - Target count for the fast clock

◆ OSC_RC_400M_CTRL2_OSC_TUNE_VAL [1/2]

#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK)

OSC_TUNE_VAL - Program the oscillator frequency

◆ OSC_RC_400M_CTRL2_OSC_TUNE_VAL [2/2]

#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK)

OSC_TUNE_VAL - Program the oscillator frequency

◆ OSC_RC_400M_CTRL2_TUNE_BYP [1/2]

#define OSC_RC_400M_CTRL2_TUNE_BYP ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK)

TUNE_BYP - Bypass the tuning logic 0b0..Use the output of tuning logic to run the oscillator 0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator

◆ OSC_RC_400M_CTRL2_TUNE_BYP [2/2]

#define OSC_RC_400M_CTRL2_TUNE_BYP ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK)

TUNE_BYP - Bypass the tuning logic 0b0..Use the output of tuning logic to run the oscillator 0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator

◆ OSC_RC_400M_CTRL2_TUNE_EN [1/2]

#define OSC_RC_400M_CTRL2_TUNE_EN ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK)

TUNE_EN - Freeze/Unfreeze the tuning value 0b0..Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value 0b1..Unfreezes and continues the tuning operation

◆ OSC_RC_400M_CTRL2_TUNE_EN [2/2]

#define OSC_RC_400M_CTRL2_TUNE_EN ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK)

TUNE_EN - Freeze/Unfreeze the tuning value 0b0..Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value 0b1..Unfreezes and continues the tuning operation

◆ OSC_RC_400M_CTRL2_TUNE_START [1/2]

#define OSC_RC_400M_CTRL2_TUNE_START ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK)

TUNE_START - Start/Stop tuning 0b0..Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL 0b1..Start tuning

◆ OSC_RC_400M_CTRL2_TUNE_START [2/2]

#define OSC_RC_400M_CTRL2_TUNE_START ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK)

TUNE_START - Start/Stop tuning 0b0..Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL 0b1..Start tuning

◆ OSC_RC_400M_CTRL3_CLR_ERR [1/2]

#define OSC_RC_400M_CTRL3_CLR_ERR ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK)

CLR_ERR - Clear the error flag CLK1M_ERR 0b0..No effect 0b1..Clears the error flag CLK1M_ERR in status register STAT0

◆ OSC_RC_400M_CTRL3_CLR_ERR [2/2]

#define OSC_RC_400M_CTRL3_CLR_ERR ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK)

CLR_ERR - Clear the error flag CLK1M_ERR 0b0..No effect 0b1..Clears the error flag CLK1M_ERR in status register STAT0

◆ OSC_RC_400M_CTRL3_COUNT_1M_CLK [1/2]

#define OSC_RC_400M_CTRL3_COUNT_1M_CLK ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK)

COUNT_1M_CLK - Count for the locked clk_1m_out

◆ OSC_RC_400M_CTRL3_COUNT_1M_CLK [2/2]

#define OSC_RC_400M_CTRL3_COUNT_1M_CLK ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK)

COUNT_1M_CLK - Count for the locked clk_1m_out

◆ OSC_RC_400M_CTRL3_EN_1M_CLK [1/2]

#define OSC_RC_400M_CTRL3_EN_1M_CLK ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK)

EN_1M_CLK - Enable 1MHz output Clock 0b0..Enable the output (clk_1m_out) 0b1..Disable the output (clk_1m_out)

◆ OSC_RC_400M_CTRL3_EN_1M_CLK [2/2]

#define OSC_RC_400M_CTRL3_EN_1M_CLK ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK)

EN_1M_CLK - Enable 1MHz output Clock 0b0..Enable the output (clk_1m_out) 0b1..Disable the output (clk_1m_out)

◆ OSC_RC_400M_CTRL3_MUX_1M_CLK [1/2]

#define OSC_RC_400M_CTRL3_MUX_1M_CLK ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK)

MUX_1M_CLK - Select free/locked 1MHz output 0b0..Select free-running 1MHz to be put out on clk_1m_out 0b1..Select locked 1MHz to be put out on clk_1m_out

◆ OSC_RC_400M_CTRL3_MUX_1M_CLK [2/2]

#define OSC_RC_400M_CTRL3_MUX_1M_CLK ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK)

MUX_1M_CLK - Select free/locked 1MHz output 0b0..Select free-running 1MHz to be put out on clk_1m_out 0b1..Select locked 1MHz to be put out on clk_1m_out

◆ OSC_RC_400M_STAT0_CLK1M_ERR [1/2]

#define OSC_RC_400M_STAT0_CLK1M_ERR ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK)

CLK1M_ERR - Error flag for clk_1m_locked 0b0..No effect 0b1..The count value has been reached within one divided ref_clk period

◆ OSC_RC_400M_STAT0_CLK1M_ERR [2/2]

#define OSC_RC_400M_STAT0_CLK1M_ERR ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK)

CLK1M_ERR - Error flag for clk_1m_locked 0b0..No effect 0b1..The count value has been reached within one divided ref_clk period

◆ OSC_RC_400M_STAT1_CURR_COUNT_VAL [1/2]

#define OSC_RC_400M_STAT1_CURR_COUNT_VAL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK)

CURR_COUNT_VAL - Current count for the fast clock

◆ OSC_RC_400M_STAT1_CURR_COUNT_VAL [2/2]

#define OSC_RC_400M_STAT1_CURR_COUNT_VAL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK)

CURR_COUNT_VAL - Current count for the fast clock

◆ OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL [1/2]

#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK)

CURR_OSC_TUNE_VAL - Current tuning value used by oscillator

◆ OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL [2/2]

#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK)

CURR_OSC_TUNE_VAL - Current tuning value used by oscillator

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