RTEMS 6.3
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LMEM Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » LMEM Peripheral Access Layer

PCCCR - PC bus Cache control register

#define LMEM_PCCCR_ENCACHE_MASK   (0x1U)
#define LMEM_PCCCR_ENCACHE_SHIFT   (0U)
#define LMEM_PCCCR_ENCACHE(x)
#define LMEM_PCCCR_ENWRBUF_MASK   (0x2U)
#define LMEM_PCCCR_ENWRBUF_SHIFT   (1U)
#define LMEM_PCCCR_ENWRBUF(x)
#define LMEM_PCCCR_PCCR2_MASK   (0x4U)
#define LMEM_PCCCR_PCCR2_SHIFT   (2U)
#define LMEM_PCCCR_PCCR2(x)
#define LMEM_PCCCR_PCCR3_MASK   (0x8U)
#define LMEM_PCCCR_PCCR3_SHIFT   (3U)
#define LMEM_PCCCR_PCCR3(x)
#define LMEM_PCCCR_INVW0_MASK   (0x1000000U)
#define LMEM_PCCCR_INVW0_SHIFT   (24U)
#define LMEM_PCCCR_INVW0(x)
#define LMEM_PCCCR_PUSHW0_MASK   (0x2000000U)
#define LMEM_PCCCR_PUSHW0_SHIFT   (25U)
#define LMEM_PCCCR_PUSHW0(x)
#define LMEM_PCCCR_INVW1_MASK   (0x4000000U)
#define LMEM_PCCCR_INVW1_SHIFT   (26U)
#define LMEM_PCCCR_INVW1(x)
#define LMEM_PCCCR_PUSHW1_MASK   (0x8000000U)
#define LMEM_PCCCR_PUSHW1_SHIFT   (27U)
#define LMEM_PCCCR_PUSHW1(x)
#define LMEM_PCCCR_GO_MASK   (0x80000000U)
#define LMEM_PCCCR_GO_SHIFT   (31U)
#define LMEM_PCCCR_GO(x)

PCCLCR - PC bus Cache line control register

#define LMEM_PCCLCR_LGO_MASK   (0x1U)
#define LMEM_PCCLCR_LGO_SHIFT   (0U)
#define LMEM_PCCLCR_LGO(x)
#define LMEM_PCCLCR_CACHEADDR_MASK   (0x3FFCU)
#define LMEM_PCCLCR_CACHEADDR_SHIFT   (2U)
#define LMEM_PCCLCR_CACHEADDR(x)
#define LMEM_PCCLCR_WSEL_MASK   (0x4000U)
#define LMEM_PCCLCR_WSEL_SHIFT   (14U)
#define LMEM_PCCLCR_WSEL(x)
#define LMEM_PCCLCR_TDSEL_MASK   (0x10000U)
#define LMEM_PCCLCR_TDSEL_SHIFT   (16U)
#define LMEM_PCCLCR_TDSEL(x)
#define LMEM_PCCLCR_LCIVB_MASK   (0x100000U)
#define LMEM_PCCLCR_LCIVB_SHIFT   (20U)
#define LMEM_PCCLCR_LCIVB(x)
#define LMEM_PCCLCR_LCIMB_MASK   (0x200000U)
#define LMEM_PCCLCR_LCIMB_SHIFT   (21U)
#define LMEM_PCCLCR_LCIMB(x)
#define LMEM_PCCLCR_LCWAY_MASK   (0x400000U)
#define LMEM_PCCLCR_LCWAY_SHIFT   (22U)
#define LMEM_PCCLCR_LCWAY(x)
#define LMEM_PCCLCR_LCMD_MASK   (0x3000000U)
#define LMEM_PCCLCR_LCMD_SHIFT   (24U)
#define LMEM_PCCLCR_LCMD(x)
#define LMEM_PCCLCR_LADSEL_MASK   (0x4000000U)
#define LMEM_PCCLCR_LADSEL_SHIFT   (26U)
#define LMEM_PCCLCR_LADSEL(x)
#define LMEM_PCCLCR_LACC_MASK   (0x8000000U)
#define LMEM_PCCLCR_LACC_SHIFT   (27U)
#define LMEM_PCCLCR_LACC(x)

PCCSAR - PC bus Cache search address register

#define LMEM_PCCSAR_LGO_MASK   (0x1U)
#define LMEM_PCCSAR_LGO_SHIFT   (0U)
#define LMEM_PCCSAR_LGO(x)
#define LMEM_PCCSAR_PHYADDR_MASK   (0xFFFFFFFEU)
#define LMEM_PCCSAR_PHYADDR_SHIFT   (1U)
#define LMEM_PCCSAR_PHYADDR(x)

PCCCVR - PC bus Cache read/write value register

#define LMEM_PCCCVR_DATA_MASK   (0xFFFFFFFFU)
#define LMEM_PCCCVR_DATA_SHIFT   (0U)
#define LMEM_PCCCVR_DATA(x)

PSCCR - PS bus Cache control register

#define LMEM_PSCCR_ENCACHE_MASK   (0x1U)
#define LMEM_PSCCR_ENCACHE_SHIFT   (0U)
#define LMEM_PSCCR_ENCACHE(x)
#define LMEM_PSCCR_ENWRBUF_MASK   (0x2U)
#define LMEM_PSCCR_ENWRBUF_SHIFT   (1U)
#define LMEM_PSCCR_ENWRBUF(x)
#define LMEM_PSCCR_PSCR2_MASK   (0x4U)
#define LMEM_PSCCR_PSCR2_SHIFT   (2U)
#define LMEM_PSCCR_PSCR2(x)
#define LMEM_PSCCR_PSCR3_MASK   (0x8U)
#define LMEM_PSCCR_PSCR3_SHIFT   (3U)
#define LMEM_PSCCR_PSCR3(x)
#define LMEM_PSCCR_INVW0_MASK   (0x1000000U)
#define LMEM_PSCCR_INVW0_SHIFT   (24U)
#define LMEM_PSCCR_INVW0(x)
#define LMEM_PSCCR_PUSHW0_MASK   (0x2000000U)
#define LMEM_PSCCR_PUSHW0_SHIFT   (25U)
#define LMEM_PSCCR_PUSHW0(x)
#define LMEM_PSCCR_INVW1_MASK   (0x4000000U)
#define LMEM_PSCCR_INVW1_SHIFT   (26U)
#define LMEM_PSCCR_INVW1(x)
#define LMEM_PSCCR_PUSHW1_MASK   (0x8000000U)
#define LMEM_PSCCR_PUSHW1_SHIFT   (27U)
#define LMEM_PSCCR_PUSHW1(x)
#define LMEM_PSCCR_GO_MASK   (0x80000000U)
#define LMEM_PSCCR_GO_SHIFT   (31U)
#define LMEM_PSCCR_GO(x)

PSCLCR - PS bus Cache line control register

#define LMEM_PSCLCR_LGO_MASK   (0x1U)
#define LMEM_PSCLCR_LGO_SHIFT   (0U)
#define LMEM_PSCLCR_LGO(x)
#define LMEM_PSCLCR_CACHEADDR_MASK   (0x3FFCU)
#define LMEM_PSCLCR_CACHEADDR_SHIFT   (2U)
#define LMEM_PSCLCR_CACHEADDR(x)
#define LMEM_PSCLCR_WSEL_MASK   (0x4000U)
#define LMEM_PSCLCR_WSEL_SHIFT   (14U)
#define LMEM_PSCLCR_WSEL(x)
#define LMEM_PSCLCR_TDSEL_MASK   (0x10000U)
#define LMEM_PSCLCR_TDSEL_SHIFT   (16U)
#define LMEM_PSCLCR_TDSEL(x)
#define LMEM_PSCLCR_LCIVB_MASK   (0x100000U)
#define LMEM_PSCLCR_LCIVB_SHIFT   (20U)
#define LMEM_PSCLCR_LCIVB(x)
#define LMEM_PSCLCR_LCIMB_MASK   (0x200000U)
#define LMEM_PSCLCR_LCIMB_SHIFT   (21U)
#define LMEM_PSCLCR_LCIMB(x)
#define LMEM_PSCLCR_LCWAY_MASK   (0x400000U)
#define LMEM_PSCLCR_LCWAY_SHIFT   (22U)
#define LMEM_PSCLCR_LCWAY(x)
#define LMEM_PSCLCR_LCMD_MASK   (0x3000000U)
#define LMEM_PSCLCR_LCMD_SHIFT   (24U)
#define LMEM_PSCLCR_LCMD(x)
#define LMEM_PSCLCR_LADSEL_MASK   (0x4000000U)
#define LMEM_PSCLCR_LADSEL_SHIFT   (26U)
#define LMEM_PSCLCR_LADSEL(x)
#define LMEM_PSCLCR_LACC_MASK   (0x8000000U)
#define LMEM_PSCLCR_LACC_SHIFT   (27U)
#define LMEM_PSCLCR_LACC(x)

PSCSAR - PS bus Cache search address register

#define LMEM_PSCSAR_LGO_MASK   (0x1U)
#define LMEM_PSCSAR_LGO_SHIFT   (0U)
#define LMEM_PSCSAR_LGO(x)
#define LMEM_PSCSAR_PHYADDR_MASK   (0xFFFFFFFEU)
#define LMEM_PSCSAR_PHYADDR_SHIFT   (1U)
#define LMEM_PSCSAR_PHYADDR(x)

PSCCVR - PS bus Cache read/write value register

#define LMEM_PSCCVR_DATA_MASK   (0xFFFFFFFFU)
#define LMEM_PSCCVR_DATA_SHIFT   (0U)
#define LMEM_PSCCVR_DATA(x)

Detailed Description

Macro Definition Documentation

◆ LMEM_PCCCR_ENCACHE

#define LMEM_PCCCR_ENCACHE ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)

ENCACHE - Cache enable 0b0..Cache disabled 0b1..Cache enabled

◆ LMEM_PCCCR_ENWRBUF

#define LMEM_PCCCR_ENWRBUF ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)

ENWRBUF - Enable Write Buffer 0b0..Write buffer disabled 0b1..Write buffer enabled

◆ LMEM_PCCCR_GO

#define LMEM_PCCCR_GO ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)

GO - Initiate Cache Command 0b0..Write: no effect. Read: no cache command active. 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.

◆ LMEM_PCCCR_INVW0

#define LMEM_PCCCR_INVW0 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)

INVW0 - Invalidate Way 0 0b0..No operation 0b1..When setting the GO bit, invalidate all lines in way 0.

◆ LMEM_PCCCR_INVW1

#define LMEM_PCCCR_INVW1 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)

INVW1 - Invalidate Way 1 0b0..No operation 0b1..When setting the GO bit, invalidate all lines in way 1

◆ LMEM_PCCCR_PCCR2

#define LMEM_PCCCR_PCCR2 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)

PCCR2 - Forces all cacheable spaces to write through 0b0..Does NOT force all cacheable spaces to write through 0b1..Forces all cacheable spaces to write through

◆ LMEM_PCCCR_PCCR3

#define LMEM_PCCCR_PCCR3 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)

PCCR3 - Forces no allocation on cache misses 0b0..Allocation on cache misses 0b1..Forces no allocation on cache misses (must also have PCCR2 asserted)

◆ LMEM_PCCCR_PUSHW0

#define LMEM_PCCCR_PUSHW0 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)

PUSHW0 - Push Way 0 0b0..No operation 0b1..When setting the GO bit, push all modified lines in way 0

◆ LMEM_PCCCR_PUSHW1

#define LMEM_PCCCR_PUSHW1 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)

PUSHW1 - Push Way 1 0b0..No operation 0b1..When setting the GO bit, push all modified lines in way 1

◆ LMEM_PCCCVR_DATA

#define LMEM_PCCCVR_DATA ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)

DATA - Cache read/write Data

◆ LMEM_PCCLCR_CACHEADDR

#define LMEM_PCCLCR_CACHEADDR ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)

CACHEADDR - Cache address

◆ LMEM_PCCLCR_LACC

#define LMEM_PCCLCR_LACC ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)

LACC - Line access type 0b0..Read 0b1..Write

◆ LMEM_PCCLCR_LADSEL

#define LMEM_PCCLCR_LADSEL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)

LADSEL - Line Address Select 0b0..Cache address 0b1..Physical address

◆ LMEM_PCCLCR_LCIMB

#define LMEM_PCCLCR_LCIMB ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)

LCIMB - Line Command Initial Modified Bit

◆ LMEM_PCCLCR_LCIVB

#define LMEM_PCCLCR_LCIVB ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)

LCIVB - Line Command Initial Valid Bit

◆ LMEM_PCCLCR_LCMD

#define LMEM_PCCLCR_LCMD ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)

LCMD - Line Command 0b00..Search and read or write 0b01..Invalidate 0b10..Push 0b11..Clear

◆ LMEM_PCCLCR_LCWAY

#define LMEM_PCCLCR_LCWAY ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)

LCWAY - Line Command Way

◆ LMEM_PCCLCR_LGO

#define LMEM_PCCLCR_LGO ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)

LGO - Initiate Cache Line Command 0b0..Write: no effect. Read: no line command active. 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.

◆ LMEM_PCCLCR_TDSEL

#define LMEM_PCCLCR_TDSEL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)

TDSEL - Tag/Data Select 0b0..Data 0b1..Tag

◆ LMEM_PCCLCR_WSEL

#define LMEM_PCCLCR_WSEL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)

WSEL - Way select 0b0..Way 0 0b1..Way 1

◆ LMEM_PCCSAR_LGO

#define LMEM_PCCSAR_LGO ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)

LGO - Initiate Cache Line Command 0b0..Write: no effect. Read: no line command active. 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.

◆ LMEM_PCCSAR_PHYADDR

#define LMEM_PCCSAR_PHYADDR ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)

PHYADDR - Physical Address

◆ LMEM_PSCCR_ENCACHE

#define LMEM_PSCCR_ENCACHE ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK)

ENCACHE - Cache enable 0b0..Cache disabled 0b1..Cache enabled

◆ LMEM_PSCCR_ENWRBUF

#define LMEM_PSCCR_ENWRBUF ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK)

ENWRBUF - Enable Write Buffer 0b0..Write buffer disabled 0b1..Write buffer enabled

◆ LMEM_PSCCR_GO

#define LMEM_PSCCR_GO ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK)

GO - Initiate Cache Command 0b0..Write: no effect. Read: no cache command active. 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.

◆ LMEM_PSCCR_INVW0

#define LMEM_PSCCR_INVW0 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK)

INVW0 - Invalidate Way 0 0b0..No operation 0b1..When setting the GO bit, invalidate all lines in way 0.

◆ LMEM_PSCCR_INVW1

#define LMEM_PSCCR_INVW1 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK)

INVW1 - Invalidate Way 1 0b0..No operation 0b1..When setting the GO bit, invalidate all lines in way 1

◆ LMEM_PSCCR_PSCR2

#define LMEM_PSCCR_PSCR2 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PSCR2_SHIFT)) & LMEM_PSCCR_PSCR2_MASK)

PSCR2 - Forces all cacheable spaces to write through 0b0..Does NOT force all cacheable spaces to write through 0b1..Forces all cacheable spaces to write through

◆ LMEM_PSCCR_PSCR3

#define LMEM_PSCCR_PSCR3 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PSCR3_SHIFT)) & LMEM_PSCCR_PSCR3_MASK)

PSCR3 - Forces no allocation on cache misses 0b0..Allocation on cache misses 0b1..Forces no allocation on cache misses (must also have PSCR2 asserted)

◆ LMEM_PSCCR_PUSHW0

#define LMEM_PSCCR_PUSHW0 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK)

PUSHW0 - Push Way 0 0b0..No operation 0b1..When setting the GO bit, push all modified lines in way 0

◆ LMEM_PSCCR_PUSHW1

#define LMEM_PSCCR_PUSHW1 ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK)

PUSHW1 - Push Way 1 0b0..No operation 0b1..When setting the GO bit, push all modified lines in way 1

◆ LMEM_PSCCVR_DATA

#define LMEM_PSCCVR_DATA ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK)

DATA - Cache read/write Data

◆ LMEM_PSCLCR_CACHEADDR

#define LMEM_PSCLCR_CACHEADDR ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK)

CACHEADDR - Cache address

◆ LMEM_PSCLCR_LACC

#define LMEM_PSCLCR_LACC ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK)

LACC - Line access type 0b0..Read 0b1..Write

◆ LMEM_PSCLCR_LADSEL

#define LMEM_PSCLCR_LADSEL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK)

LADSEL - Line Address Select 0b0..Cache address 0b1..Physical address

◆ LMEM_PSCLCR_LCIMB

#define LMEM_PSCLCR_LCIMB ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK)

LCIMB - Line Command Initial Modified Bit

◆ LMEM_PSCLCR_LCIVB

#define LMEM_PSCLCR_LCIVB ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK)

LCIVB - Line Command Initial Valid Bit

◆ LMEM_PSCLCR_LCMD

#define LMEM_PSCLCR_LCMD ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK)

LCMD - Line Command 0b00..Search and read or write 0b01..Invalidate 0b10..Push 0b11..Clear

◆ LMEM_PSCLCR_LCWAY

#define LMEM_PSCLCR_LCWAY ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK)

LCWAY - Line Command Way

◆ LMEM_PSCLCR_LGO

#define LMEM_PSCLCR_LGO ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK)

LGO - Initiate Cache Line Command 0b0..Write: no effect. Read: no line command active. 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.

◆ LMEM_PSCLCR_TDSEL

#define LMEM_PSCLCR_TDSEL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK)

TDSEL - Tag/Data Select 0b0..Data 0b1..Tag

◆ LMEM_PSCLCR_WSEL

#define LMEM_PSCLCR_WSEL ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK)

WSEL - Way select 0b0..Way 0 0b1..Way 1

◆ LMEM_PSCSAR_LGO

#define LMEM_PSCSAR_LGO ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK)

LGO - Initiate Cache Line Command 0b0..Write: no effect. Read: no line command active. 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.

◆ LMEM_PSCSAR_PHYADDR

#define LMEM_PSCSAR_PHYADDR ( x)
Value:
(((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK)

PHYADDR - Physical Address

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