RTEMS 6.3
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Topics | Macros
FMC_LL Private Macros
Board Support Packages » ARM » STM32H7 | STM32H7xx_HAL_Driver » FMC_LL

Topics

 FMC NAND Interrupt
 macros to handle NAND interrupts
 FMC NAND Macros
 macros to handle NAND device enable/disable
 FMC NOR/SRAM Macros
 macros to handle NOR device enable/disable and read/write operations
 FMC SDRAM Interrupt
 macros to handle SDRAM interrupts

Macros

#define IS_FMC_NORSRAM_BANK(__BANK__)
#define IS_FMC_MUX(__MUX__)
#define IS_FMC_MEMORY(__MEMORY__)
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__)
#define IS_FMC_PAGESIZE(__SIZE__)
#define IS_FMC_WRITE_FIFO(__FIFO__)
#define IS_FMC_ACCESS_MODE(__MODE__)
#define IS_FMC_BURSTMODE(__STATE__)
#define IS_FMC_WAIT_POLARITY(__POLARITY__)
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__)
#define IS_FMC_WRITE_OPERATION(__OPERATION__)
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__)
#define IS_FMC_EXTENDED_MODE(__MODE__)
#define IS_FMC_ASYNWAIT(__STATE__)
#define IS_FMC_DATA_LATENCY(__LATENCY__)
#define IS_FMC_WRITE_BURST(__BURST__)
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__)
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__)
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__)
#define IS_FMC_DATASETUP_TIME(__TIME__)
#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__)
#define IS_FMC_TURNAROUND_TIME(__TIME__)
#define IS_FMC_CLK_DIV(__DIV__)
#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__)
#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__)
#define IS_FMC_NAND_BANK(__BANK__)
#define IS_FMC_WAIT_FEATURE(__FEATURE__)
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__)
#define IS_FMC_ECC_STATE(__STATE__)
#define IS_FMC_ECCPAGE_SIZE(__SIZE__)
#define IS_FMC_TCLR_TIME(__TIME__)
#define IS_FMC_TAR_TIME(__TIME__)
#define IS_FMC_SETUP_TIME(__TIME__)
#define IS_FMC_WAIT_TIME(__TIME__)
#define IS_FMC_HOLD_TIME(__TIME__)
#define IS_FMC_HIZ_TIME(__TIME__)
#define IS_FMC_NAND_DEVICE(__INSTANCE__)
#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__)
#define IS_FMC_WRITE_PROTECTION(__WRITE__)
#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__)
#define IS_FMC_READ_BURST(__RBURST__)
#define IS_FMC_READPIPE_DELAY(__DELAY__)
#define IS_FMC_COMMAND_MODE(__COMMAND__)
#define IS_FMC_COMMAND_TARGET(__TARGET__)
#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__)
#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__)
#define IS_FMC_SELFREFRESH_TIME(__TIME__)
#define IS_FMC_ROWCYCLE_DELAY(__DELAY__)
#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__)
#define IS_FMC_RP_DELAY(__DELAY__)
#define IS_FMC_RCD_DELAY(__DELAY__)
#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__)
#define IS_FMC_MODE_REGISTER(__CONTENT__)
#define IS_FMC_REFRESH_RATE(__RATE__)
#define IS_FMC_SDRAM_DEVICE(__INSTANCE__)
#define IS_FMC_SDRAM_BANK(__BANK__)
#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__)
#define IS_FMC_ROWBITS_NUMBER(__ROW__)
#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__)
#define IS_FMC_CAS_LATENCY(__LATENCY__)
#define __FMC_ENABLE()
 Enable the FMC Peripheral.
#define __FMC_DISABLE()
 Disable the FMC Peripheral.

Detailed Description

Macro Definition Documentation

◆ __FMC_DISABLE

#define __FMC_DISABLE ( )
Value:
(FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
FMC_BCR1_FMCEN
#define FMC_BCR1_FMCEN
Definition stm32h723xx.h:11296

Disable the FMC Peripheral.

Return values
None

◆ __FMC_ENABLE

#define __FMC_ENABLE ( )
Value:
(FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)

Enable the FMC Peripheral.

Return values
None

◆ IS_FMC_ACCESS_MODE

#define IS_FMC_ACCESS_MODE ( __MODE__)
Value:
(((__MODE__) == FMC_ACCESS_MODE_A) || \
((__MODE__) == FMC_ACCESS_MODE_B) || \
((__MODE__) == FMC_ACCESS_MODE_C) || \
((__MODE__) == FMC_ACCESS_MODE_D))

◆ IS_FMC_ADDRESS_HOLD_TIME

#define IS_FMC_ADDRESS_HOLD_TIME ( __TIME__)
Value:
(((__TIME__) > 0U) && ((__TIME__) <= 15U))

◆ IS_FMC_ADDRESS_SETUP_TIME

#define IS_FMC_ADDRESS_SETUP_TIME ( __TIME__)
Value:
((__TIME__) <= 15U)

◆ IS_FMC_ASYNWAIT

#define IS_FMC_ASYNWAIT ( __STATE__)
Value:
(((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))

◆ IS_FMC_AUTOREFRESH_NUMBER

#define IS_FMC_AUTOREFRESH_NUMBER ( __NUMBER__)
Value:
(((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))

◆ IS_FMC_BURSTMODE

#define IS_FMC_BURSTMODE ( __STATE__)
Value:
(((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))

◆ IS_FMC_CAS_LATENCY

#define IS_FMC_CAS_LATENCY ( __LATENCY__)
Value:
(((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \
((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))

◆ IS_FMC_CLK_DIV

#define IS_FMC_CLK_DIV ( __DIV__)
Value:
(((__DIV__) > 1U) && ((__DIV__) <= 16U))

◆ IS_FMC_COLUMNBITS_NUMBER

#define IS_FMC_COLUMNBITS_NUMBER ( __COLUMN__)
Value:
(((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))

◆ IS_FMC_COMMAND_MODE

#define IS_FMC_COMMAND_MODE ( __COMMAND__)
Value:
(((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))

◆ IS_FMC_COMMAND_TARGET

#define IS_FMC_COMMAND_TARGET ( __TARGET__)
Value:
(((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))

◆ IS_FMC_CONTINOUS_CLOCK

#define IS_FMC_CONTINOUS_CLOCK ( __CCLOCK__)
Value:
(((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))

◆ IS_FMC_DATA_LATENCY

#define IS_FMC_DATA_LATENCY ( __LATENCY__)
Value:
(((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))

◆ IS_FMC_DATAHOLD_DURATION

#define IS_FMC_DATAHOLD_DURATION ( __DATAHOLD__)
Value:
((__DATAHOLD__) <= 3U)

◆ IS_FMC_DATASETUP_TIME

#define IS_FMC_DATASETUP_TIME ( __TIME__)
Value:
(((__TIME__) > 0U) && ((__TIME__) <= 255U))

◆ IS_FMC_ECC_STATE

#define IS_FMC_ECC_STATE ( __STATE__)
Value:
(((__STATE__) == FMC_NAND_ECC_DISABLE) || \
((__STATE__) == FMC_NAND_ECC_ENABLE))

◆ IS_FMC_ECCPAGE_SIZE

#define IS_FMC_ECCPAGE_SIZE ( __SIZE__)
Value:
(((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))

◆ IS_FMC_EXITSELFREFRESH_DELAY

#define IS_FMC_EXITSELFREFRESH_DELAY ( __DELAY__)
Value:
(((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

◆ IS_FMC_EXTENDED_MODE

#define IS_FMC_EXTENDED_MODE ( __MODE__)
Value:
(((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FMC_EXTENDED_MODE_ENABLE))

◆ IS_FMC_HIZ_TIME

#define IS_FMC_HIZ_TIME ( __TIME__)
Value:
((__TIME__) <= 254U)

◆ IS_FMC_HOLD_TIME

#define IS_FMC_HOLD_TIME ( __TIME__)
Value:
((__TIME__) <= 254U)

◆ IS_FMC_INTERNALBANK_NUMBER

#define IS_FMC_INTERNALBANK_NUMBER ( __NUMBER__)
Value:
(((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))

◆ IS_FMC_LOADTOACTIVE_DELAY

#define IS_FMC_LOADTOACTIVE_DELAY ( __DELAY__)
Value:
(((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

◆ IS_FMC_MEMORY

#define IS_FMC_MEMORY ( __MEMORY__)
Value:
(((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
((__MEMORY__) == FMC_MEMORY_TYPE_NOR))

◆ IS_FMC_MODE_REGISTER

#define IS_FMC_MODE_REGISTER ( __CONTENT__)
Value:
((__CONTENT__) <= 8191U)

◆ IS_FMC_MUX

#define IS_FMC_MUX ( __MUX__)
Value:
(((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))

◆ IS_FMC_NAND_BANK

#define IS_FMC_NAND_BANK ( __BANK__)
Value:
((__BANK__) == FMC_NAND_BANK3)

◆ IS_FMC_NAND_DEVICE

#define IS_FMC_NAND_DEVICE ( __INSTANCE__)
Value:
((__INSTANCE__) == FMC_NAND_DEVICE)

◆ IS_FMC_NAND_MEMORY_WIDTH

#define IS_FMC_NAND_MEMORY_WIDTH ( __WIDTH__)
Value:
(((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))

◆ IS_FMC_NORSRAM_BANK

#define IS_FMC_NORSRAM_BANK ( __BANK__)
Value:
(((__BANK__) == FMC_NORSRAM_BANK1) || \
((__BANK__) == FMC_NORSRAM_BANK2) || \
((__BANK__) == FMC_NORSRAM_BANK3) || \
((__BANK__) == FMC_NORSRAM_BANK4))

◆ IS_FMC_NORSRAM_DEVICE

#define IS_FMC_NORSRAM_DEVICE ( __INSTANCE__)
Value:
((__INSTANCE__) == FMC_NORSRAM_DEVICE)

◆ IS_FMC_NORSRAM_EXTENDED_DEVICE

#define IS_FMC_NORSRAM_EXTENDED_DEVICE ( __INSTANCE__)
Value:
((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)

◆ IS_FMC_NORSRAM_MEMORY_WIDTH

#define IS_FMC_NORSRAM_MEMORY_WIDTH ( __WIDTH__)
Value:
(((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))

◆ IS_FMC_PAGESIZE

#define IS_FMC_PAGESIZE ( __SIZE__)
Value:
(((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
((__SIZE__) == FMC_PAGE_SIZE_128) || \
((__SIZE__) == FMC_PAGE_SIZE_256) || \
((__SIZE__) == FMC_PAGE_SIZE_512) || \
((__SIZE__) == FMC_PAGE_SIZE_1024))

◆ IS_FMC_RCD_DELAY

#define IS_FMC_RCD_DELAY ( __DELAY__)
Value:
(((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

◆ IS_FMC_READ_BURST

#define IS_FMC_READ_BURST ( __RBURST__)
Value:
(((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))

◆ IS_FMC_READPIPE_DELAY

#define IS_FMC_READPIPE_DELAY ( __DELAY__)
Value:
(((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))

◆ IS_FMC_REFRESH_RATE

#define IS_FMC_REFRESH_RATE ( __RATE__)
Value:
((__RATE__) <= 8191U)

◆ IS_FMC_ROWBITS_NUMBER

#define IS_FMC_ROWBITS_NUMBER ( __ROW__)
Value:
(((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \
((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))

◆ IS_FMC_ROWCYCLE_DELAY

#define IS_FMC_ROWCYCLE_DELAY ( __DELAY__)
Value:
(((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

◆ IS_FMC_RP_DELAY

#define IS_FMC_RP_DELAY ( __DELAY__)
Value:
(((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

◆ IS_FMC_SDCLOCK_PERIOD

#define IS_FMC_SDCLOCK_PERIOD ( __PERIOD__)
Value:
(((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))

◆ IS_FMC_SDMEMORY_WIDTH

#define IS_FMC_SDMEMORY_WIDTH ( __WIDTH__)
Value:
(((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))

◆ IS_FMC_SDRAM_BANK

#define IS_FMC_SDRAM_BANK ( __BANK__)
Value:
(((__BANK__) == FMC_SDRAM_BANK1) || \
((__BANK__) == FMC_SDRAM_BANK2))

◆ IS_FMC_SDRAM_DEVICE

#define IS_FMC_SDRAM_DEVICE ( __INSTANCE__)
Value:
((__INSTANCE__) == FMC_SDRAM_DEVICE)

◆ IS_FMC_SELFREFRESH_TIME

#define IS_FMC_SELFREFRESH_TIME ( __TIME__)
Value:
(((__TIME__) > 0U) && ((__TIME__) <= 16U))

◆ IS_FMC_SETUP_TIME

#define IS_FMC_SETUP_TIME ( __TIME__)
Value:
((__TIME__) <= 254U)

◆ IS_FMC_TAR_TIME

#define IS_FMC_TAR_TIME ( __TIME__)
Value:
((__TIME__) <= 255U)

◆ IS_FMC_TCLR_TIME

#define IS_FMC_TCLR_TIME ( __TIME__)
Value:
((__TIME__) <= 255U)

◆ IS_FMC_TURNAROUND_TIME

#define IS_FMC_TURNAROUND_TIME ( __TIME__)
Value:
((__TIME__) <= 15U)

◆ IS_FMC_WAIT_FEATURE

#define IS_FMC_WAIT_FEATURE ( __FEATURE__)
Value:
(((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))

◆ IS_FMC_WAIT_POLARITY

#define IS_FMC_WAIT_POLARITY ( __POLARITY__)
Value:
(((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))

◆ IS_FMC_WAIT_SIGNAL_ACTIVE

#define IS_FMC_WAIT_SIGNAL_ACTIVE ( __ACTIVE__)
Value:
(((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))

◆ IS_FMC_WAIT_TIME

#define IS_FMC_WAIT_TIME ( __TIME__)
Value:
((__TIME__) <= 254U)

◆ IS_FMC_WAITE_SIGNAL

#define IS_FMC_WAITE_SIGNAL ( __SIGNAL__)
Value:
(((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))

◆ IS_FMC_WRITE_BURST

#define IS_FMC_WRITE_BURST ( __BURST__)
Value:
(((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FMC_WRITE_BURST_ENABLE))

◆ IS_FMC_WRITE_FIFO

#define IS_FMC_WRITE_FIFO ( __FIFO__)
Value:
(((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
((__FIFO__) == FMC_WRITE_FIFO_ENABLE))

◆ IS_FMC_WRITE_OPERATION

#define IS_FMC_WRITE_OPERATION ( __OPERATION__)
Value:
(((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))

◆ IS_FMC_WRITE_PROTECTION

#define IS_FMC_WRITE_PROTECTION ( __WRITE__)
Value:
(((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))

◆ IS_FMC_WRITE_RECOVERY_TIME

#define IS_FMC_WRITE_RECOVERY_TIME ( __TIME__)
Value:
(((__TIME__) > 0U) && ((__TIME__) <= 16U))
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