ENC Register Masks

Macros
#define	EWM_CTRL_EWMEN_MASK   (0x1U)
#define	EWM_CTRL_EWMEN_SHIFT   (0U)
#define	EWM_CTRL_EWMEN(x)
#define	EWM_CTRL_ASSIN_MASK   (0x2U)
#define	EWM_CTRL_ASSIN_SHIFT   (1U)
#define	EWM_CTRL_ASSIN(x)
#define	EWM_CTRL_INEN_MASK   (0x4U)
#define	EWM_CTRL_INEN_SHIFT   (2U)
#define	EWM_CTRL_INEN(x)
#define	EWM_CTRL_INTEN_MASK   (0x8U)
#define	EWM_CTRL_INTEN_SHIFT   (3U)
#define	EWM_CTRL_INTEN(x)
#define	EWM_CTRL_EWMEN_MASK   (0x1U)
#define	EWM_CTRL_EWMEN_SHIFT   (0U)
#define	EWM_CTRL_EWMEN(x)
#define	EWM_CTRL_ASSIN_MASK   (0x2U)
#define	EWM_CTRL_ASSIN_SHIFT   (1U)
#define	EWM_CTRL_ASSIN(x)
#define	EWM_CTRL_INEN_MASK   (0x4U)
#define	EWM_CTRL_INEN_SHIFT   (2U)
#define	EWM_CTRL_INEN(x)
#define	EWM_CTRL_INTEN_MASK   (0x8U)
#define	EWM_CTRL_INTEN_SHIFT   (3U)
#define	EWM_CTRL_INTEN(x)
#define	PWM_CTRL_DBLEN_MASK   (0x1U)
#define	PWM_CTRL_DBLEN_SHIFT   (0U)
#define	PWM_CTRL_DBLEN(x)
#define	PWM_CTRL_DBLX_MASK   (0x2U)
#define	PWM_CTRL_DBLX_SHIFT   (1U)
#define	PWM_CTRL_DBLX(x)
#define	PWM_CTRL_LDMOD_MASK   (0x4U)
#define	PWM_CTRL_LDMOD_SHIFT   (2U)
#define	PWM_CTRL_LDMOD(x)
#define	PWM_CTRL_SPLIT_MASK   (0x8U)
#define	PWM_CTRL_SPLIT_SHIFT   (3U)
#define	PWM_CTRL_SPLIT(x)
#define	PWM_CTRL_PRSC_MASK   (0x70U)
#define	PWM_CTRL_PRSC_SHIFT   (4U)
#define	PWM_CTRL_PRSC(x)
#define	PWM_CTRL_COMPMODE_MASK   (0x80U)
#define	PWM_CTRL_COMPMODE_SHIFT   (7U)
#define	PWM_CTRL_COMPMODE(x)
#define	PWM_CTRL_DT_MASK   (0x300U)
#define	PWM_CTRL_DT_SHIFT   (8U)
#define	PWM_CTRL_DT(x)
#define	PWM_CTRL_FULL_MASK   (0x400U)
#define	PWM_CTRL_FULL_SHIFT   (10U)
#define	PWM_CTRL_FULL(x)
#define	PWM_CTRL_HALF_MASK   (0x800U)
#define	PWM_CTRL_HALF_SHIFT   (11U)
#define	PWM_CTRL_HALF(x)
#define	PWM_CTRL_LDFQ_MASK   (0xF000U)
#define	PWM_CTRL_LDFQ_SHIFT   (12U)
#define	PWM_CTRL_LDFQ(x)
#define	PWM_CTRL_DBLEN_MASK   (0x1U)
#define	PWM_CTRL_DBLEN_SHIFT   (0U)
#define	PWM_CTRL_DBLEN(x)
#define	PWM_CTRL_DBLX_MASK   (0x2U)
#define	PWM_CTRL_DBLX_SHIFT   (1U)
#define	PWM_CTRL_DBLX(x)
#define	PWM_CTRL_LDMOD_MASK   (0x4U)
#define	PWM_CTRL_LDMOD_SHIFT   (2U)
#define	PWM_CTRL_LDMOD(x)
#define	PWM_CTRL_SPLIT_MASK   (0x8U)
#define	PWM_CTRL_SPLIT_SHIFT   (3U)
#define	PWM_CTRL_SPLIT(x)
#define	PWM_CTRL_PRSC_MASK   (0x70U)
#define	PWM_CTRL_PRSC_SHIFT   (4U)
#define	PWM_CTRL_PRSC(x)
#define	PWM_CTRL_COMPMODE_MASK   (0x80U)
#define	PWM_CTRL_COMPMODE_SHIFT   (7U)
#define	PWM_CTRL_COMPMODE(x)
#define	PWM_CTRL_DT_MASK   (0x300U)
#define	PWM_CTRL_DT_SHIFT   (8U)
#define	PWM_CTRL_DT(x)
#define	PWM_CTRL_FULL_MASK   (0x400U)
#define	PWM_CTRL_FULL_SHIFT   (10U)
#define	PWM_CTRL_FULL(x)
#define	PWM_CTRL_HALF_MASK   (0x800U)
#define	PWM_CTRL_HALF_SHIFT   (11U)
#define	PWM_CTRL_HALF(x)
#define	PWM_CTRL_LDFQ_MASK   (0xF000U)
#define	PWM_CTRL_LDFQ_SHIFT   (12U)
#define	PWM_CTRL_LDFQ(x)

CTRL - Control Register
#define	ENC_CTRL_CMPIE_MASK   (0x1U)
#define	ENC_CTRL_CMPIE_SHIFT   (0U)
#define	ENC_CTRL_CMPIE(x)
#define	ENC_CTRL_CMPIRQ_MASK   (0x2U)
#define	ENC_CTRL_CMPIRQ_SHIFT   (1U)
#define	ENC_CTRL_CMPIRQ(x)
#define	ENC_CTRL_WDE_MASK   (0x4U)
#define	ENC_CTRL_WDE_SHIFT   (2U)
#define	ENC_CTRL_WDE(x)
#define	ENC_CTRL_DIE_MASK   (0x8U)
#define	ENC_CTRL_DIE_SHIFT   (3U)
#define	ENC_CTRL_DIE(x)
#define	ENC_CTRL_DIRQ_MASK   (0x10U)
#define	ENC_CTRL_DIRQ_SHIFT   (4U)
#define	ENC_CTRL_DIRQ(x)
#define	ENC_CTRL_XNE_MASK   (0x20U)
#define	ENC_CTRL_XNE_SHIFT   (5U)
#define	ENC_CTRL_XNE(x)
#define	ENC_CTRL_XIP_MASK   (0x40U)
#define	ENC_CTRL_XIP_SHIFT   (6U)
#define	ENC_CTRL_XIP(x)
#define	ENC_CTRL_XIE_MASK   (0x80U)
#define	ENC_CTRL_XIE_SHIFT   (7U)
#define	ENC_CTRL_XIE(x)
#define	ENC_CTRL_XIRQ_MASK   (0x100U)
#define	ENC_CTRL_XIRQ_SHIFT   (8U)
#define	ENC_CTRL_XIRQ(x)
#define	ENC_CTRL_PH1_MASK   (0x200U)
#define	ENC_CTRL_PH1_SHIFT   (9U)
#define	ENC_CTRL_PH1(x)
#define	ENC_CTRL_REV_MASK   (0x400U)
#define	ENC_CTRL_REV_SHIFT   (10U)
#define	ENC_CTRL_REV(x)
#define	ENC_CTRL_SWIP_MASK   (0x800U)
#define	ENC_CTRL_SWIP_SHIFT   (11U)
#define	ENC_CTRL_SWIP(x)
#define	ENC_CTRL_HNE_MASK   (0x1000U)
#define	ENC_CTRL_HNE_SHIFT   (12U)
#define	ENC_CTRL_HNE(x)
#define	ENC_CTRL_HIP_MASK   (0x2000U)
#define	ENC_CTRL_HIP_SHIFT   (13U)
#define	ENC_CTRL_HIP(x)
#define	ENC_CTRL_HIE_MASK   (0x4000U)
#define	ENC_CTRL_HIE_SHIFT   (14U)
#define	ENC_CTRL_HIE(x)
#define	ENC_CTRL_HIRQ_MASK   (0x8000U)
#define	ENC_CTRL_HIRQ_SHIFT   (15U)
#define	ENC_CTRL_HIRQ(x)
#define	ENC_CTRL_CMPIE_MASK   (0x1U)
#define	ENC_CTRL_CMPIE_SHIFT   (0U)
#define	ENC_CTRL_CMPIE(x)
#define	ENC_CTRL_CMPIRQ_MASK   (0x2U)
#define	ENC_CTRL_CMPIRQ_SHIFT   (1U)
#define	ENC_CTRL_CMPIRQ(x)
#define	ENC_CTRL_WDE_MASK   (0x4U)
#define	ENC_CTRL_WDE_SHIFT   (2U)
#define	ENC_CTRL_WDE(x)
#define	ENC_CTRL_DIE_MASK   (0x8U)
#define	ENC_CTRL_DIE_SHIFT   (3U)
#define	ENC_CTRL_DIE(x)
#define	ENC_CTRL_DIRQ_MASK   (0x10U)
#define	ENC_CTRL_DIRQ_SHIFT   (4U)
#define	ENC_CTRL_DIRQ(x)
#define	ENC_CTRL_XNE_MASK   (0x20U)
#define	ENC_CTRL_XNE_SHIFT   (5U)
#define	ENC_CTRL_XNE(x)
#define	ENC_CTRL_XIP_MASK   (0x40U)
#define	ENC_CTRL_XIP_SHIFT   (6U)
#define	ENC_CTRL_XIP(x)
#define	ENC_CTRL_XIE_MASK   (0x80U)
#define	ENC_CTRL_XIE_SHIFT   (7U)
#define	ENC_CTRL_XIE(x)
#define	ENC_CTRL_XIRQ_MASK   (0x100U)
#define	ENC_CTRL_XIRQ_SHIFT   (8U)
#define	ENC_CTRL_XIRQ(x)
#define	ENC_CTRL_PH1_MASK   (0x200U)
#define	ENC_CTRL_PH1_SHIFT   (9U)
#define	ENC_CTRL_PH1(x)
#define	ENC_CTRL_REV_MASK   (0x400U)
#define	ENC_CTRL_REV_SHIFT   (10U)
#define	ENC_CTRL_REV(x)
#define	ENC_CTRL_SWIP_MASK   (0x800U)
#define	ENC_CTRL_SWIP_SHIFT   (11U)
#define	ENC_CTRL_SWIP(x)
#define	ENC_CTRL_HNE_MASK   (0x1000U)
#define	ENC_CTRL_HNE_SHIFT   (12U)
#define	ENC_CTRL_HNE(x)
#define	ENC_CTRL_HIP_MASK   (0x2000U)
#define	ENC_CTRL_HIP_SHIFT   (13U)
#define	ENC_CTRL_HIP(x)
#define	ENC_CTRL_HIE_MASK   (0x4000U)
#define	ENC_CTRL_HIE_SHIFT   (14U)
#define	ENC_CTRL_HIE(x)
#define	ENC_CTRL_HIRQ_MASK   (0x8000U)
#define	ENC_CTRL_HIRQ_SHIFT   (15U)
#define	ENC_CTRL_HIRQ(x)
#define	ENC_CTRL_CMPIE_MASK   (0x1U)
#define	ENC_CTRL_CMPIE_SHIFT   (0U)
#define	ENC_CTRL_CMPIE(x)
#define	ENC_CTRL_CMPIRQ_MASK   (0x2U)
#define	ENC_CTRL_CMPIRQ_SHIFT   (1U)
#define	ENC_CTRL_CMPIRQ(x)
#define	ENC_CTRL_WDE_MASK   (0x4U)
#define	ENC_CTRL_WDE_SHIFT   (2U)
#define	ENC_CTRL_WDE(x)
#define	ENC_CTRL_DIE_MASK   (0x8U)
#define	ENC_CTRL_DIE_SHIFT   (3U)
#define	ENC_CTRL_DIE(x)
#define	ENC_CTRL_DIRQ_MASK   (0x10U)
#define	ENC_CTRL_DIRQ_SHIFT   (4U)
#define	ENC_CTRL_DIRQ(x)
#define	ENC_CTRL_XNE_MASK   (0x20U)
#define	ENC_CTRL_XNE_SHIFT   (5U)
#define	ENC_CTRL_XNE(x)
#define	ENC_CTRL_XIP_MASK   (0x40U)
#define	ENC_CTRL_XIP_SHIFT   (6U)
#define	ENC_CTRL_XIP(x)
#define	ENC_CTRL_XIE_MASK   (0x80U)
#define	ENC_CTRL_XIE_SHIFT   (7U)
#define	ENC_CTRL_XIE(x)
#define	ENC_CTRL_XIRQ_MASK   (0x100U)
#define	ENC_CTRL_XIRQ_SHIFT   (8U)
#define	ENC_CTRL_XIRQ(x)
#define	ENC_CTRL_PH1_MASK   (0x200U)
#define	ENC_CTRL_PH1_SHIFT   (9U)
#define	ENC_CTRL_PH1(x)
#define	ENC_CTRL_REV_MASK   (0x400U)
#define	ENC_CTRL_REV_SHIFT   (10U)
#define	ENC_CTRL_REV(x)
#define	ENC_CTRL_SWIP_MASK   (0x800U)
#define	ENC_CTRL_SWIP_SHIFT   (11U)
#define	ENC_CTRL_SWIP(x)
#define	ENC_CTRL_HNE_MASK   (0x1000U)
#define	ENC_CTRL_HNE_SHIFT   (12U)
#define	ENC_CTRL_HNE(x)
#define	ENC_CTRL_HIP_MASK   (0x2000U)
#define	ENC_CTRL_HIP_SHIFT   (13U)
#define	ENC_CTRL_HIP(x)
#define	ENC_CTRL_HIE_MASK   (0x4000U)
#define	ENC_CTRL_HIE_SHIFT   (14U)
#define	ENC_CTRL_HIE(x)
#define	ENC_CTRL_HIRQ_MASK   (0x8000U)
#define	ENC_CTRL_HIRQ_SHIFT   (15U)
#define	ENC_CTRL_HIRQ(x)
#define	EWM_CTRL_EWMEN_MASK   (0x1U)
#define	EWM_CTRL_EWMEN_SHIFT   (0U)
#define	EWM_CTRL_EWMEN(x)
#define	EWM_CTRL_ASSIN_MASK   (0x2U)
#define	EWM_CTRL_ASSIN_SHIFT   (1U)
#define	EWM_CTRL_ASSIN(x)
#define	EWM_CTRL_INEN_MASK   (0x4U)
#define	EWM_CTRL_INEN_SHIFT   (2U)
#define	EWM_CTRL_INEN(x)
#define	EWM_CTRL_INTEN_MASK   (0x8U)
#define	EWM_CTRL_INTEN_SHIFT   (3U)
#define	EWM_CTRL_INTEN(x)
#define	PWM_CTRL_DBLEN_MASK   (0x1U)
#define	PWM_CTRL_DBLEN_SHIFT   (0U)
#define	PWM_CTRL_DBLEN(x)
#define	PWM_CTRL_DBLX_MASK   (0x2U)
#define	PWM_CTRL_DBLX_SHIFT   (1U)
#define	PWM_CTRL_DBLX(x)
#define	PWM_CTRL_LDMOD_MASK   (0x4U)
#define	PWM_CTRL_LDMOD_SHIFT   (2U)
#define	PWM_CTRL_LDMOD(x)
#define	PWM_CTRL_SPLIT_MASK   (0x8U)
#define	PWM_CTRL_SPLIT_SHIFT   (3U)
#define	PWM_CTRL_SPLIT(x)
#define	PWM_CTRL_PRSC_MASK   (0x70U)
#define	PWM_CTRL_PRSC_SHIFT   (4U)
#define	PWM_CTRL_PRSC(x)
#define	PWM_CTRL_COMPMODE_MASK   (0x80U)
#define	PWM_CTRL_COMPMODE_SHIFT   (7U)
#define	PWM_CTRL_COMPMODE(x)
#define	PWM_CTRL_DT_MASK   (0x300U)
#define	PWM_CTRL_DT_SHIFT   (8U)
#define	PWM_CTRL_DT(x)
#define	PWM_CTRL_FULL_MASK   (0x400U)
#define	PWM_CTRL_FULL_SHIFT   (10U)
#define	PWM_CTRL_FULL(x)
#define	PWM_CTRL_HALF_MASK   (0x800U)
#define	PWM_CTRL_HALF_SHIFT   (11U)
#define	PWM_CTRL_HALF(x)
#define	PWM_CTRL_LDFQ_MASK   (0xF000U)
#define	PWM_CTRL_LDFQ_SHIFT   (12U)
#define	PWM_CTRL_LDFQ(x)

FILT - Input Filter Register
#define	ENC_FILT_FILT_PER_MASK   (0xFFU)
#define	ENC_FILT_FILT_PER_SHIFT   (0U)
#define	ENC_FILT_FILT_PER(x)
#define	ENC_FILT_FILT_CNT_MASK   (0x700U)
#define	ENC_FILT_FILT_CNT_SHIFT   (8U)
#define	ENC_FILT_FILT_CNT(x)
#define	ENC_FILT_FILT_PER_MASK   (0xFFU)
#define	ENC_FILT_FILT_PER_SHIFT   (0U)
#define	ENC_FILT_FILT_PER(x)
#define	ENC_FILT_FILT_CNT_MASK   (0x700U)
#define	ENC_FILT_FILT_CNT_SHIFT   (8U)
#define	ENC_FILT_FILT_CNT(x)
#define	ENC_FILT_FILT_PRSC_MASK   (0xE000U)
#define	ENC_FILT_FILT_PRSC_SHIFT   (13U)
#define	ENC_FILT_FILT_PRSC(x)
#define	ENC_FILT_FILT_PER_MASK   (0xFFU)
#define	ENC_FILT_FILT_PER_SHIFT   (0U)
#define	ENC_FILT_FILT_PER(x)
#define	ENC_FILT_FILT_CNT_MASK   (0x700U)
#define	ENC_FILT_FILT_CNT_SHIFT   (8U)
#define	ENC_FILT_FILT_CNT(x)
#define	ENC_FILT_FILT_PRSC_MASK   (0xE000U)
#define	ENC_FILT_FILT_PRSC_SHIFT   (13U)
#define	ENC_FILT_FILT_PRSC(x)

WTR - Watchdog Timeout Register
#define	ENC_WTR_WDOG_MASK   (0xFFFFU)
#define	ENC_WTR_WDOG_SHIFT   (0U)
#define	ENC_WTR_WDOG(x)
#define	ENC_WTR_WDOG_MASK   (0xFFFFU)
#define	ENC_WTR_WDOG_SHIFT   (0U)
#define	ENC_WTR_WDOG(x)
#define	ENC_WTR_WDOG_MASK   (0xFFFFU)
#define	ENC_WTR_WDOG_SHIFT   (0U)
#define	ENC_WTR_WDOG(x)

POSD - Position Difference Counter Register
#define	ENC_POSD_POSD_MASK   (0xFFFFU)
#define	ENC_POSD_POSD_SHIFT   (0U)
#define	ENC_POSD_POSD(x)
#define	ENC_POSD_POSD_MASK   (0xFFFFU)
#define	ENC_POSD_POSD_SHIFT   (0U)
#define	ENC_POSD_POSD(x)
#define	ENC_POSD_POSD_MASK   (0xFFFFU)
#define	ENC_POSD_POSD_SHIFT   (0U)
#define	ENC_POSD_POSD(x)

POSDH - Position Difference Hold Register
#define	ENC_POSDH_POSDH_MASK   (0xFFFFU)
#define	ENC_POSDH_POSDH_SHIFT   (0U)
#define	ENC_POSDH_POSDH(x)
#define	ENC_POSDH_POSDH_MASK   (0xFFFFU)
#define	ENC_POSDH_POSDH_SHIFT   (0U)
#define	ENC_POSDH_POSDH(x)
#define	ENC_POSDH_POSDH_MASK   (0xFFFFU)
#define	ENC_POSDH_POSDH_SHIFT   (0U)
#define	ENC_POSDH_POSDH(x)

REV - Revolution Counter Register
#define	ENC_REV_REV_MASK   (0xFFFFU)
#define	ENC_REV_REV_SHIFT   (0U)
#define	ENC_REV_REV(x)
#define	ENC_REV_REV_MASK   (0xFFFFU)
#define	ENC_REV_REV_SHIFT   (0U)
#define	ENC_REV_REV(x)
#define	ENC_REV_REV_MASK   (0xFFFFU)
#define	ENC_REV_REV_SHIFT   (0U)
#define	ENC_REV_REV(x)

REVH - Revolution Hold Register
#define	ENC_REVH_REVH_MASK   (0xFFFFU)
#define	ENC_REVH_REVH_SHIFT   (0U)
#define	ENC_REVH_REVH(x)
#define	ENC_REVH_REVH_MASK   (0xFFFFU)
#define	ENC_REVH_REVH_SHIFT   (0U)
#define	ENC_REVH_REVH(x)
#define	ENC_REVH_REVH_MASK   (0xFFFFU)
#define	ENC_REVH_REVH_SHIFT   (0U)
#define	ENC_REVH_REVH(x)

UPOS - Upper Position Counter Register
#define	ENC_UPOS_POS_MASK   (0xFFFFU)
#define	ENC_UPOS_POS_SHIFT   (0U)
#define	ENC_UPOS_POS(x)
#define	ENC_UPOS_POS_MASK   (0xFFFFU)
#define	ENC_UPOS_POS_SHIFT   (0U)
#define	ENC_UPOS_POS(x)
#define	ENC_UPOS_POS_MASK   (0xFFFFU)
#define	ENC_UPOS_POS_SHIFT   (0U)
#define	ENC_UPOS_POS(x)

LPOS - Lower Position Counter Register
#define	ENC_LPOS_POS_MASK   (0xFFFFU)
#define	ENC_LPOS_POS_SHIFT   (0U)
#define	ENC_LPOS_POS(x)
#define	ENC_LPOS_POS_MASK   (0xFFFFU)
#define	ENC_LPOS_POS_SHIFT   (0U)
#define	ENC_LPOS_POS(x)
#define	ENC_LPOS_POS_MASK   (0xFFFFU)
#define	ENC_LPOS_POS_SHIFT   (0U)
#define	ENC_LPOS_POS(x)

UPOSH - Upper Position Hold Register
#define	ENC_UPOSH_POSH_MASK   (0xFFFFU)
#define	ENC_UPOSH_POSH_SHIFT   (0U)
#define	ENC_UPOSH_POSH(x)
#define	ENC_UPOSH_POSH_MASK   (0xFFFFU)
#define	ENC_UPOSH_POSH_SHIFT   (0U)
#define	ENC_UPOSH_POSH(x)
#define	ENC_UPOSH_POSH_MASK   (0xFFFFU)
#define	ENC_UPOSH_POSH_SHIFT   (0U)
#define	ENC_UPOSH_POSH(x)

LPOSH - Lower Position Hold Register
#define	ENC_LPOSH_POSH_MASK   (0xFFFFU)
#define	ENC_LPOSH_POSH_SHIFT   (0U)
#define	ENC_LPOSH_POSH(x)
#define	ENC_LPOSH_POSH_MASK   (0xFFFFU)
#define	ENC_LPOSH_POSH_SHIFT   (0U)
#define	ENC_LPOSH_POSH(x)
#define	ENC_LPOSH_POSH_MASK   (0xFFFFU)
#define	ENC_LPOSH_POSH_SHIFT   (0U)
#define	ENC_LPOSH_POSH(x)

UINIT - Upper Initialization Register
#define	ENC_UINIT_INIT_MASK   (0xFFFFU)
#define	ENC_UINIT_INIT_SHIFT   (0U)
#define	ENC_UINIT_INIT(x)
#define	ENC_UINIT_INIT_MASK   (0xFFFFU)
#define	ENC_UINIT_INIT_SHIFT   (0U)
#define	ENC_UINIT_INIT(x)
#define	ENC_UINIT_INIT_MASK   (0xFFFFU)
#define	ENC_UINIT_INIT_SHIFT   (0U)
#define	ENC_UINIT_INIT(x)

LINIT - Lower Initialization Register
#define	ENC_LINIT_INIT_MASK   (0xFFFFU)
#define	ENC_LINIT_INIT_SHIFT   (0U)
#define	ENC_LINIT_INIT(x)
#define	ENC_LINIT_INIT_MASK   (0xFFFFU)
#define	ENC_LINIT_INIT_SHIFT   (0U)
#define	ENC_LINIT_INIT(x)
#define	ENC_LINIT_INIT_MASK   (0xFFFFU)
#define	ENC_LINIT_INIT_SHIFT   (0U)
#define	ENC_LINIT_INIT(x)

IMR - Input Monitor Register
#define	ENC_IMR_HOME_MASK   (0x1U)
#define	ENC_IMR_HOME_SHIFT   (0U)
#define	ENC_IMR_HOME(x)
#define	ENC_IMR_INDEX_MASK   (0x2U)
#define	ENC_IMR_INDEX_SHIFT   (1U)
#define	ENC_IMR_INDEX(x)
#define	ENC_IMR_PHB_MASK   (0x4U)
#define	ENC_IMR_PHB_SHIFT   (2U)
#define	ENC_IMR_PHB(x)
#define	ENC_IMR_PHA_MASK   (0x8U)
#define	ENC_IMR_PHA_SHIFT   (3U)
#define	ENC_IMR_PHA(x)
#define	ENC_IMR_FHOM_MASK   (0x10U)
#define	ENC_IMR_FHOM_SHIFT   (4U)
#define	ENC_IMR_FHOM(x)
#define	ENC_IMR_FIND_MASK   (0x20U)
#define	ENC_IMR_FIND_SHIFT   (5U)
#define	ENC_IMR_FIND(x)
#define	ENC_IMR_FPHB_MASK   (0x40U)
#define	ENC_IMR_FPHB_SHIFT   (6U)
#define	ENC_IMR_FPHB(x)
#define	ENC_IMR_FPHA_MASK   (0x80U)
#define	ENC_IMR_FPHA_SHIFT   (7U)
#define	ENC_IMR_FPHA(x)
#define	ENC_IMR_HOME_MASK   (0x1U)
#define	ENC_IMR_HOME_SHIFT   (0U)
#define	ENC_IMR_HOME(x)
#define	ENC_IMR_INDEX_MASK   (0x2U)
#define	ENC_IMR_INDEX_SHIFT   (1U)
#define	ENC_IMR_INDEX(x)
#define	ENC_IMR_PHB_MASK   (0x4U)
#define	ENC_IMR_PHB_SHIFT   (2U)
#define	ENC_IMR_PHB(x)
#define	ENC_IMR_PHA_MASK   (0x8U)
#define	ENC_IMR_PHA_SHIFT   (3U)
#define	ENC_IMR_PHA(x)
#define	ENC_IMR_FHOM_MASK   (0x10U)
#define	ENC_IMR_FHOM_SHIFT   (4U)
#define	ENC_IMR_FHOM(x)
#define	ENC_IMR_FIND_MASK   (0x20U)
#define	ENC_IMR_FIND_SHIFT   (5U)
#define	ENC_IMR_FIND(x)
#define	ENC_IMR_FPHB_MASK   (0x40U)
#define	ENC_IMR_FPHB_SHIFT   (6U)
#define	ENC_IMR_FPHB(x)
#define	ENC_IMR_FPHA_MASK   (0x80U)
#define	ENC_IMR_FPHA_SHIFT   (7U)
#define	ENC_IMR_FPHA(x)
#define	ENC_IMR_HOME_MASK   (0x1U)
#define	ENC_IMR_HOME_SHIFT   (0U)
#define	ENC_IMR_HOME(x)
#define	ENC_IMR_INDEX_MASK   (0x2U)
#define	ENC_IMR_INDEX_SHIFT   (1U)
#define	ENC_IMR_INDEX(x)
#define	ENC_IMR_PHB_MASK   (0x4U)
#define	ENC_IMR_PHB_SHIFT   (2U)
#define	ENC_IMR_PHB(x)
#define	ENC_IMR_PHA_MASK   (0x8U)
#define	ENC_IMR_PHA_SHIFT   (3U)
#define	ENC_IMR_PHA(x)
#define	ENC_IMR_FHOM_MASK   (0x10U)
#define	ENC_IMR_FHOM_SHIFT   (4U)
#define	ENC_IMR_FHOM(x)
#define	ENC_IMR_FIND_MASK   (0x20U)
#define	ENC_IMR_FIND_SHIFT   (5U)
#define	ENC_IMR_FIND(x)
#define	ENC_IMR_FPHB_MASK   (0x40U)
#define	ENC_IMR_FPHB_SHIFT   (6U)
#define	ENC_IMR_FPHB(x)
#define	ENC_IMR_FPHA_MASK   (0x80U)
#define	ENC_IMR_FPHA_SHIFT   (7U)
#define	ENC_IMR_FPHA(x)

TST - Test Register
#define	ENC_TST_TEST_COUNT_MASK   (0xFFU)
#define	ENC_TST_TEST_COUNT_SHIFT   (0U)
#define	ENC_TST_TEST_COUNT(x)
#define	ENC_TST_TEST_PERIOD_MASK   (0x1F00U)
#define	ENC_TST_TEST_PERIOD_SHIFT   (8U)
#define	ENC_TST_TEST_PERIOD(x)
#define	ENC_TST_QDN_MASK   (0x2000U)
#define	ENC_TST_QDN_SHIFT   (13U)
#define	ENC_TST_QDN(x)
#define	ENC_TST_TCE_MASK   (0x4000U)
#define	ENC_TST_TCE_SHIFT   (14U)
#define	ENC_TST_TCE(x)
#define	ENC_TST_TEN_MASK   (0x8000U)
#define	ENC_TST_TEN_SHIFT   (15U)
#define	ENC_TST_TEN(x)
#define	ENC_TST_TEST_COUNT_MASK   (0xFFU)
#define	ENC_TST_TEST_COUNT_SHIFT   (0U)
#define	ENC_TST_TEST_COUNT(x)
#define	ENC_TST_TEST_PERIOD_MASK   (0x1F00U)
#define	ENC_TST_TEST_PERIOD_SHIFT   (8U)
#define	ENC_TST_TEST_PERIOD(x)
#define	ENC_TST_QDN_MASK   (0x2000U)
#define	ENC_TST_QDN_SHIFT   (13U)
#define	ENC_TST_QDN(x)
#define	ENC_TST_TCE_MASK   (0x4000U)
#define	ENC_TST_TCE_SHIFT   (14U)
#define	ENC_TST_TCE(x)
#define	ENC_TST_TEN_MASK   (0x8000U)
#define	ENC_TST_TEN_SHIFT   (15U)
#define	ENC_TST_TEN(x)
#define	ENC_TST_TEST_COUNT_MASK   (0xFFU)
#define	ENC_TST_TEST_COUNT_SHIFT   (0U)
#define	ENC_TST_TEST_COUNT(x)
#define	ENC_TST_TEST_PERIOD_MASK   (0x1F00U)
#define	ENC_TST_TEST_PERIOD_SHIFT   (8U)
#define	ENC_TST_TEST_PERIOD(x)
#define	ENC_TST_QDN_MASK   (0x2000U)
#define	ENC_TST_QDN_SHIFT   (13U)
#define	ENC_TST_QDN(x)
#define	ENC_TST_TCE_MASK   (0x4000U)
#define	ENC_TST_TCE_SHIFT   (14U)
#define	ENC_TST_TCE(x)
#define	ENC_TST_TEN_MASK   (0x8000U)
#define	ENC_TST_TEN_SHIFT   (15U)
#define	ENC_TST_TEN(x)

CTRL2 - Control 2 register
#define	ENC_CTRL2_UPDHLD_MASK   (0x1U)
#define	ENC_CTRL2_UPDHLD_SHIFT   (0U)
#define	ENC_CTRL2_UPDHLD(x)
#define	ENC_CTRL2_UPDPOS_MASK   (0x2U)
#define	ENC_CTRL2_UPDPOS_SHIFT   (1U)
#define	ENC_CTRL2_UPDPOS(x)
#define	ENC_CTRL2_MOD_MASK   (0x4U)
#define	ENC_CTRL2_MOD_SHIFT   (2U)
#define	ENC_CTRL2_MOD(x)
#define	ENC_CTRL2_DIR_MASK   (0x8U)
#define	ENC_CTRL2_DIR_SHIFT   (3U)
#define	ENC_CTRL2_DIR(x)
#define	ENC_CTRL2_RUIE_MASK   (0x10U)
#define	ENC_CTRL2_RUIE_SHIFT   (4U)
#define	ENC_CTRL2_RUIE(x)
#define	ENC_CTRL2_RUIRQ_MASK   (0x20U)
#define	ENC_CTRL2_RUIRQ_SHIFT   (5U)
#define	ENC_CTRL2_RUIRQ(x)
#define	ENC_CTRL2_ROIE_MASK   (0x40U)
#define	ENC_CTRL2_ROIE_SHIFT   (6U)
#define	ENC_CTRL2_ROIE(x)
#define	ENC_CTRL2_ROIRQ_MASK   (0x80U)
#define	ENC_CTRL2_ROIRQ_SHIFT   (7U)
#define	ENC_CTRL2_ROIRQ(x)
#define	ENC_CTRL2_REVMOD_MASK   (0x100U)
#define	ENC_CTRL2_REVMOD_SHIFT   (8U)
#define	ENC_CTRL2_REVMOD(x)
#define	ENC_CTRL2_OUTCTL_MASK   (0x200U)
#define	ENC_CTRL2_OUTCTL_SHIFT   (9U)
#define	ENC_CTRL2_OUTCTL(x)
#define	ENC_CTRL2_UPDHLD_MASK   (0x1U)
#define	ENC_CTRL2_UPDHLD_SHIFT   (0U)
#define	ENC_CTRL2_UPDHLD(x)
#define	ENC_CTRL2_UPDPOS_MASK   (0x2U)
#define	ENC_CTRL2_UPDPOS_SHIFT   (1U)
#define	ENC_CTRL2_UPDPOS(x)
#define	ENC_CTRL2_MOD_MASK   (0x4U)
#define	ENC_CTRL2_MOD_SHIFT   (2U)
#define	ENC_CTRL2_MOD(x)
#define	ENC_CTRL2_DIR_MASK   (0x8U)
#define	ENC_CTRL2_DIR_SHIFT   (3U)
#define	ENC_CTRL2_DIR(x)
#define	ENC_CTRL2_RUIE_MASK   (0x10U)
#define	ENC_CTRL2_RUIE_SHIFT   (4U)
#define	ENC_CTRL2_RUIE(x)
#define	ENC_CTRL2_RUIRQ_MASK   (0x20U)
#define	ENC_CTRL2_RUIRQ_SHIFT   (5U)
#define	ENC_CTRL2_RUIRQ(x)
#define	ENC_CTRL2_ROIE_MASK   (0x40U)
#define	ENC_CTRL2_ROIE_SHIFT   (6U)
#define	ENC_CTRL2_ROIE(x)
#define	ENC_CTRL2_ROIRQ_MASK   (0x80U)
#define	ENC_CTRL2_ROIRQ_SHIFT   (7U)
#define	ENC_CTRL2_ROIRQ(x)
#define	ENC_CTRL2_REVMOD_MASK   (0x100U)
#define	ENC_CTRL2_REVMOD_SHIFT   (8U)
#define	ENC_CTRL2_REVMOD(x)
#define	ENC_CTRL2_OUTCTL_MASK   (0x200U)
#define	ENC_CTRL2_OUTCTL_SHIFT   (9U)
#define	ENC_CTRL2_OUTCTL(x)
#define	ENC_CTRL2_SABIE_MASK   (0x400U)
#define	ENC_CTRL2_SABIE_SHIFT   (10U)
#define	ENC_CTRL2_SABIE(x)
#define	ENC_CTRL2_SABIRQ_MASK   (0x800U)
#define	ENC_CTRL2_SABIRQ_SHIFT   (11U)
#define	ENC_CTRL2_SABIRQ(x)
#define	ENC_CTRL2_UPDHLD_MASK   (0x1U)
#define	ENC_CTRL2_UPDHLD_SHIFT   (0U)
#define	ENC_CTRL2_UPDHLD(x)
#define	ENC_CTRL2_UPDPOS_MASK   (0x2U)
#define	ENC_CTRL2_UPDPOS_SHIFT   (1U)
#define	ENC_CTRL2_UPDPOS(x)
#define	ENC_CTRL2_MOD_MASK   (0x4U)
#define	ENC_CTRL2_MOD_SHIFT   (2U)
#define	ENC_CTRL2_MOD(x)
#define	ENC_CTRL2_DIR_MASK   (0x8U)
#define	ENC_CTRL2_DIR_SHIFT   (3U)
#define	ENC_CTRL2_DIR(x)
#define	ENC_CTRL2_RUIE_MASK   (0x10U)
#define	ENC_CTRL2_RUIE_SHIFT   (4U)
#define	ENC_CTRL2_RUIE(x)
#define	ENC_CTRL2_RUIRQ_MASK   (0x20U)
#define	ENC_CTRL2_RUIRQ_SHIFT   (5U)
#define	ENC_CTRL2_RUIRQ(x)
#define	ENC_CTRL2_ROIE_MASK   (0x40U)
#define	ENC_CTRL2_ROIE_SHIFT   (6U)
#define	ENC_CTRL2_ROIE(x)
#define	ENC_CTRL2_ROIRQ_MASK   (0x80U)
#define	ENC_CTRL2_ROIRQ_SHIFT   (7U)
#define	ENC_CTRL2_ROIRQ(x)
#define	ENC_CTRL2_REVMOD_MASK   (0x100U)
#define	ENC_CTRL2_REVMOD_SHIFT   (8U)
#define	ENC_CTRL2_REVMOD(x)
#define	ENC_CTRL2_OUTCTL_MASK   (0x200U)
#define	ENC_CTRL2_OUTCTL_SHIFT   (9U)
#define	ENC_CTRL2_OUTCTL(x)
#define	ENC_CTRL2_SABIE_MASK   (0x400U)
#define	ENC_CTRL2_SABIE_SHIFT   (10U)
#define	ENC_CTRL2_SABIE(x)
#define	ENC_CTRL2_SABIRQ_MASK   (0x800U)
#define	ENC_CTRL2_SABIRQ_SHIFT   (11U)
#define	ENC_CTRL2_SABIRQ(x)

UMOD - Upper Modulus Register
#define	ENC_UMOD_MOD_MASK   (0xFFFFU)
#define	ENC_UMOD_MOD_SHIFT   (0U)
#define	ENC_UMOD_MOD(x)
#define	ENC_UMOD_MOD_MASK   (0xFFFFU)
#define	ENC_UMOD_MOD_SHIFT   (0U)
#define	ENC_UMOD_MOD(x)
#define	ENC_UMOD_MOD_MASK   (0xFFFFU)
#define	ENC_UMOD_MOD_SHIFT   (0U)
#define	ENC_UMOD_MOD(x)

LMOD - Lower Modulus Register
#define	ENC_LMOD_MOD_MASK   (0xFFFFU)
#define	ENC_LMOD_MOD_SHIFT   (0U)
#define	ENC_LMOD_MOD(x)
#define	ENC_LMOD_MOD_MASK   (0xFFFFU)
#define	ENC_LMOD_MOD_SHIFT   (0U)
#define	ENC_LMOD_MOD(x)
#define	ENC_LMOD_MOD_MASK   (0xFFFFU)
#define	ENC_LMOD_MOD_SHIFT   (0U)
#define	ENC_LMOD_MOD(x)

UCOMP - Upper Position Compare Register
#define	ENC_UCOMP_COMP_MASK   (0xFFFFU)
#define	ENC_UCOMP_COMP_SHIFT   (0U)
#define	ENC_UCOMP_COMP(x)
#define	ENC_UCOMP_COMP_MASK   (0xFFFFU)
#define	ENC_UCOMP_COMP_SHIFT   (0U)
#define	ENC_UCOMP_COMP(x)
#define	ENC_UCOMP_COMP_MASK   (0xFFFFU)
#define	ENC_UCOMP_COMP_SHIFT   (0U)
#define	ENC_UCOMP_COMP(x)

LCOMP - Lower Position Compare Register
#define	ENC_LCOMP_COMP_MASK   (0xFFFFU)
#define	ENC_LCOMP_COMP_SHIFT   (0U)
#define	ENC_LCOMP_COMP(x)
#define	ENC_LCOMP_COMP_MASK   (0xFFFFU)
#define	ENC_LCOMP_COMP_SHIFT   (0U)
#define	ENC_LCOMP_COMP(x)
#define	ENC_LCOMP_COMP_MASK   (0xFFFFU)
#define	ENC_LCOMP_COMP_SHIFT   (0U)
#define	ENC_LCOMP_COMP(x)

LASTEDGE - Last Edge Time Register
#define	ENC_LASTEDGE_LASTEDGE_MASK   (0xFFFFU)
#define	ENC_LASTEDGE_LASTEDGE_SHIFT   (0U)
#define	ENC_LASTEDGE_LASTEDGE(x)
#define	ENC_LASTEDGE_LASTEDGE_MASK   (0xFFFFU)
#define	ENC_LASTEDGE_LASTEDGE_SHIFT   (0U)
#define	ENC_LASTEDGE_LASTEDGE(x)

LASTEDGEH - Last Edge Time Hold Register
#define	ENC_LASTEDGEH_LASTEDGEH_MASK   (0xFFFFU)
#define	ENC_LASTEDGEH_LASTEDGEH_SHIFT   (0U)
#define	ENC_LASTEDGEH_LASTEDGEH(x)
#define	ENC_LASTEDGEH_LASTEDGEH_MASK   (0xFFFFU)
#define	ENC_LASTEDGEH_LASTEDGEH_SHIFT   (0U)
#define	ENC_LASTEDGEH_LASTEDGEH(x)

POSDPER - Position Difference Period Counter Register
#define	ENC_POSDPER_POSDPER_MASK   (0xFFFFU)
#define	ENC_POSDPER_POSDPER_SHIFT   (0U)
#define	ENC_POSDPER_POSDPER(x)
#define	ENC_POSDPER_POSDPER_MASK   (0xFFFFU)
#define	ENC_POSDPER_POSDPER_SHIFT   (0U)
#define	ENC_POSDPER_POSDPER(x)

POSDPERBFR - Position Difference Period Buffer Register
#define	ENC_POSDPERBFR_POSDPERBFR_MASK   (0xFFFFU)
#define	ENC_POSDPERBFR_POSDPERBFR_SHIFT   (0U)
#define	ENC_POSDPERBFR_POSDPERBFR(x)
#define	ENC_POSDPERBFR_POSDPERBFR_MASK   (0xFFFFU)
#define	ENC_POSDPERBFR_POSDPERBFR_SHIFT   (0U)
#define	ENC_POSDPERBFR_POSDPERBFR(x)

POSDPERH - Position Difference Period Hold Register
#define	ENC_POSDPERH_POSDPERH_MASK   (0xFFFFU)
#define	ENC_POSDPERH_POSDPERH_SHIFT   (0U)
#define	ENC_POSDPERH_POSDPERH(x)
#define	ENC_POSDPERH_POSDPERH_MASK   (0xFFFFU)
#define	ENC_POSDPERH_POSDPERH_SHIFT   (0U)
#define	ENC_POSDPERH_POSDPERH(x)

CTRL3 - Control 3 Register
#define	ENC_CTRL3_PMEN_MASK   (0x1U)
#define	ENC_CTRL3_PMEN_SHIFT   (0U)
#define	ENC_CTRL3_PMEN(x)
#define	ENC_CTRL3_PRSC_MASK   (0xF0U)
#define	ENC_CTRL3_PRSC_SHIFT   (4U)
#define	ENC_CTRL3_PRSC(x)
#define	ENC_CTRL3_PMEN_MASK   (0x1U)
#define	ENC_CTRL3_PMEN_SHIFT   (0U)
#define	ENC_CTRL3_PMEN(x)
#define	ENC_CTRL3_PRSC_MASK   (0xF0U)
#define	ENC_CTRL3_PRSC_SHIFT   (4U)
#define	ENC_CTRL3_PRSC(x)

Detailed Description

Macro Definition Documentation

ENC_CTRL2_DIR [1/3]

#define ENC_CTRL2_DIR

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

ENC_CTRL2_DIR [2/3]

#define ENC_CTRL2_DIR

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

ENC_CTRL2_DIR [3/3]

#define ENC_CTRL2_DIR

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

ENC_CTRL2_MOD [1/3]

#define ENC_CTRL2_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

ENC_CTRL2_MOD [2/3]

#define ENC_CTRL2_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

ENC_CTRL2_MOD [3/3]

#define ENC_CTRL2_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

ENC_CTRL2_OUTCTL [1/3]

#define ENC_CTRL2_OUTCTL

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read

ENC_CTRL2_OUTCTL [2/3]

#define ENC_CTRL2_OUTCTL

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read

ENC_CTRL2_OUTCTL [3/3]

#define ENC_CTRL2_OUTCTL

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read

ENC_CTRL2_REVMOD [1/3]

#define ENC_CTRL2_REVMOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)

ENC_CTRL2_REVMOD [2/3]

#define ENC_CTRL2_REVMOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)

ENC_CTRL2_REVMOD [3/3]

#define ENC_CTRL2_REVMOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)

ENC_CTRL2_ROIE [1/3]

#define ENC_CTRL2_ROIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL2_ROIE [2/3]

#define ENC_CTRL2_ROIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL2_ROIE [3/3]

#define ENC_CTRL2_ROIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL2_ROIRQ [1/3]

#define ENC_CTRL2_ROIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

ENC_CTRL2_ROIRQ [2/3]

#define ENC_CTRL2_ROIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

ENC_CTRL2_ROIRQ [3/3]

#define ENC_CTRL2_ROIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

ENC_CTRL2_RUIE [1/3]

#define ENC_CTRL2_RUIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL2_RUIE [2/3]

#define ENC_CTRL2_RUIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL2_RUIE [3/3]

#define ENC_CTRL2_RUIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL2_RUIRQ [1/3]

#define ENC_CTRL2_RUIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

ENC_CTRL2_RUIRQ [2/3]

#define ENC_CTRL2_RUIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

ENC_CTRL2_RUIRQ [3/3]

#define ENC_CTRL2_RUIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

ENC_CTRL2_SABIE [1/2]

#define ENC_CTRL2_SABIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL2_SABIE [2/2]

#define ENC_CTRL2_SABIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL2_SABIRQ [1/2]

#define ENC_CTRL2_SABIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request 0b0..No simultaneous change of PHASEA and PHASEB has occurred 0b1..A simultaneous change of PHASEA and PHASEB has occurred

ENC_CTRL2_SABIRQ [2/2]

#define ENC_CTRL2_SABIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request 0b0..No simultaneous change of PHASEA and PHASEB has occurred 0b1..A simultaneous change of PHASEA and PHASEB has occurred

ENC_CTRL2_UPDHLD [1/3]

#define ENC_CTRL2_UPDHLD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal

ENC_CTRL2_UPDHLD [2/3]

#define ENC_CTRL2_UPDHLD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal

ENC_CTRL2_UPDHLD [3/3]

#define ENC_CTRL2_UPDHLD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal

ENC_CTRL2_UPDPOS [1/3]

#define ENC_CTRL2_UPDPOS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER

ENC_CTRL2_UPDPOS [2/3]

#define ENC_CTRL2_UPDPOS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER

ENC_CTRL2_UPDPOS [3/3]

#define ENC_CTRL2_UPDPOS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER

ENC_CTRL3_PMEN [1/2]

#define ENC_CTRL3_PMEN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK)

PMEN - Period measurement function enable 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read. 0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read.

ENC_CTRL3_PMEN [2/2]

#define ENC_CTRL3_PMEN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK)

PMEN - Period measurement function enable 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read. 0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read.

ENC_CTRL3_PRSC [1/2]

#define ENC_CTRL3_PRSC

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK)

PRSC - Prescaler

ENC_CTRL3_PRSC [2/2]

#define ENC_CTRL3_PRSC

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK)

PRSC - Prescaler

ENC_CTRL_CMPIE [1/3]

#define ENC_CTRL_CMPIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

CMPIE - Compare Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_CMPIE [2/3]

#define ENC_CTRL_CMPIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

CMPIE - Compare Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_CMPIE [3/3]

#define ENC_CTRL_CMPIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

CMPIE - Compare Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_CMPIRQ [1/3]

#define ENC_CTRL_CMPIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

CMPIRQ - Compare Interrupt Request 0b0..No match has occurred (the counter does not match the COMP value) 0b1..COMP match has occurred (the counter matches the COMP value)

ENC_CTRL_CMPIRQ [2/3]

#define ENC_CTRL_CMPIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

CMPIRQ - Compare Interrupt Request 0b0..No match has occurred (the counter does not match the COMP value) 0b1..COMP match has occurred (the counter matches the COMP value)

ENC_CTRL_CMPIRQ [3/3]

#define ENC_CTRL_CMPIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

CMPIRQ - Compare Interrupt Request 0b0..No match has occurred (the counter does not match the COMP value) 0b1..COMP match has occurred (the counter matches the COMP value)

ENC_CTRL_DIE [1/3]

#define ENC_CTRL_DIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

DIE - Watchdog Timeout Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_DIE [2/3]

#define ENC_CTRL_DIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

DIE - Watchdog Timeout Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_DIE [3/3]

#define ENC_CTRL_DIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

DIE - Watchdog Timeout Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_DIRQ [1/3]

#define ENC_CTRL_DIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

DIRQ - Watchdog Timeout Interrupt Request 0b0..No Watchdog timeout interrupt has occurred 0b1..Watchdog timeout interrupt has occurred

ENC_CTRL_DIRQ [2/3]

#define ENC_CTRL_DIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

DIRQ - Watchdog Timeout Interrupt Request 0b0..No Watchdog timeout interrupt has occurred 0b1..Watchdog timeout interrupt has occurred

ENC_CTRL_DIRQ [3/3]

#define ENC_CTRL_DIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

DIRQ - Watchdog Timeout Interrupt Request 0b0..No Watchdog timeout interrupt has occurred 0b1..Watchdog timeout interrupt has occurred

ENC_CTRL_HIE [1/3]

#define ENC_CTRL_HIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

HIE - HOME Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_HIE [2/3]

#define ENC_CTRL_HIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

HIE - HOME Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_HIE [3/3]

#define ENC_CTRL_HIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

HIE - HOME Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_HIP [1/3]

#define ENC_CTRL_HIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

HIP - Enable HOME to Initialize Position Counters UPOS and LPOS 0b0..No action 0b1..HOME signal initializes the position counter

ENC_CTRL_HIP [2/3]

#define ENC_CTRL_HIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

HIP - Enable HOME to Initialize Position Counters UPOS and LPOS 0b0..No action 0b1..HOME signal initializes the position counter

ENC_CTRL_HIP [3/3]

#define ENC_CTRL_HIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

HIP - Enable HOME to Initialize Position Counters UPOS and LPOS 0b0..No action 0b1..HOME signal initializes the position counter

ENC_CTRL_HIRQ [1/3]

#define ENC_CTRL_HIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)

HIRQ - HOME Signal Transition Interrupt Request 0b0..No transition on the HOME signal has occurred 0b1..A transition on the HOME signal has occurred

ENC_CTRL_HIRQ [2/3]

#define ENC_CTRL_HIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)

HIRQ - HOME Signal Transition Interrupt Request 0b0..No transition on the HOME signal has occurred 0b1..A transition on the HOME signal has occurred

ENC_CTRL_HIRQ [3/3]

#define ENC_CTRL_HIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)

HIRQ - HOME Signal Transition Interrupt Request 0b0..No transition on the HOME signal has occurred 0b1..A transition on the HOME signal has occurred

ENC_CTRL_HNE [1/3]

#define ENC_CTRL_HNE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

HNE - Use Negative Edge of HOME Input 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS

ENC_CTRL_HNE [2/3]

#define ENC_CTRL_HNE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

HNE - Use Negative Edge of HOME Input 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS

ENC_CTRL_HNE [3/3]

#define ENC_CTRL_HNE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

HNE - Use Negative Edge of HOME Input 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS

ENC_CTRL_PH1 [1/3]

#define ENC_CTRL_PH1

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

PH1 - Enable Signal Phase Count Mode 0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down

ENC_CTRL_PH1 [2/3]

#define ENC_CTRL_PH1

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

PH1 - Enable Signal Phase Count Mode 0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down

ENC_CTRL_PH1 [3/3]

#define ENC_CTRL_PH1

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

PH1 - Enable Signal Phase Count Mode 0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down

ENC_CTRL_REV [1/3]

#define ENC_CTRL_REV

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

REV - Enable Reverse Direction Counting 0b0..Count normally 0b1..Count in the reverse direction

ENC_CTRL_REV [2/3]

#define ENC_CTRL_REV

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

REV - Enable Reverse Direction Counting 0b0..Count normally 0b1..Count in the reverse direction

ENC_CTRL_REV [3/3]

#define ENC_CTRL_REV

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

REV - Enable Reverse Direction Counting 0b0..Count normally 0b1..Count in the reverse direction

ENC_CTRL_SWIP [1/3]

#define ENC_CTRL_SWIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)

ENC_CTRL_SWIP [2/3]

#define ENC_CTRL_SWIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)

ENC_CTRL_SWIP [3/3]

#define ENC_CTRL_SWIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)

ENC_CTRL_WDE [1/3]

#define ENC_CTRL_WDE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

WDE - Watchdog Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_WDE [2/3]

#define ENC_CTRL_WDE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

WDE - Watchdog Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_WDE [3/3]

#define ENC_CTRL_WDE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

WDE - Watchdog Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_XIE [1/3]

#define ENC_CTRL_XIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

XIE - INDEX Pulse Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_XIE [2/3]

#define ENC_CTRL_XIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

XIE - INDEX Pulse Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_XIE [3/3]

#define ENC_CTRL_XIE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

XIE - INDEX Pulse Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_XIP [1/3]

#define ENC_CTRL_XIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS 0b0..INDEX pulse does not initialize the position counter 0b1..INDEX pulse initializes the position counter

ENC_CTRL_XIP [2/3]

#define ENC_CTRL_XIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS 0b0..INDEX pulse does not initialize the position counter 0b1..INDEX pulse initializes the position counter

ENC_CTRL_XIP [3/3]

#define ENC_CTRL_XIP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS 0b0..INDEX pulse does not initialize the position counter 0b1..INDEX pulse initializes the position counter

ENC_CTRL_XIRQ [1/3]

#define ENC_CTRL_XIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

XIRQ - INDEX Pulse Interrupt Request 0b0..INDEX pulse has not occurred 0b1..INDEX pulse has occurred

ENC_CTRL_XIRQ [2/3]

#define ENC_CTRL_XIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

XIRQ - INDEX Pulse Interrupt Request 0b0..INDEX pulse has not occurred 0b1..INDEX pulse has occurred

ENC_CTRL_XIRQ [3/3]

#define ENC_CTRL_XIRQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

XIRQ - INDEX Pulse Interrupt Request 0b0..INDEX pulse has not occurred 0b1..INDEX pulse has occurred

ENC_CTRL_XNE [1/3]

#define ENC_CTRL_XNE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

XNE - Use Negative Edge of INDEX Pulse 0b0..Use positive edge of INDEX pulse 0b1..Use negative edge of INDEX pulse

ENC_CTRL_XNE [2/3]

#define ENC_CTRL_XNE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

XNE - Use Negative Edge of INDEX Pulse 0b0..Use positive edge of INDEX pulse 0b1..Use negative edge of INDEX pulse

ENC_CTRL_XNE [3/3]

#define ENC_CTRL_XNE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

XNE - Use Negative Edge of INDEX Pulse 0b0..Use positive edge of INDEX pulse 0b1..Use negative edge of INDEX pulse

ENC_FILT_FILT_CNT [1/3]

#define ENC_FILT_FILT_CNT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)

FILT_CNT - Input Filter Sample Count

ENC_FILT_FILT_CNT [2/3]

#define ENC_FILT_FILT_CNT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)

FILT_CNT - Input Filter Sample Count

ENC_FILT_FILT_CNT [3/3]

#define ENC_FILT_FILT_CNT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)

FILT_CNT - Input Filter Sample Count

ENC_FILT_FILT_PER [1/3]

#define ENC_FILT_FILT_PER

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)

FILT_PER - Input Filter Sample Period

ENC_FILT_FILT_PER [2/3]

#define ENC_FILT_FILT_PER

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)

FILT_PER - Input Filter Sample Period

ENC_FILT_FILT_PER [3/3]

#define ENC_FILT_FILT_PER

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)

FILT_PER - Input Filter Sample Period

ENC_FILT_FILT_PRSC [1/2]

#define ENC_FILT_FILT_PRSC

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK)

FILT_PRSC - prescaler divide IPbus clock to FILT clk

ENC_FILT_FILT_PRSC [2/2]

#define ENC_FILT_FILT_PRSC

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK)

FILT_PRSC - prescaler divide IPbus clock to FILT clk

ENC_IMR_FHOM [1/3]

#define ENC_IMR_FHOM

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)

FHOM - FHOM

ENC_IMR_FHOM [2/3]

#define ENC_IMR_FHOM

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)

FHOM - FHOM

ENC_IMR_FHOM [3/3]

#define ENC_IMR_FHOM

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)

FHOM - FHOM

ENC_IMR_FIND [1/3]

#define ENC_IMR_FIND

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)

FIND - FIND

ENC_IMR_FIND [2/3]

#define ENC_IMR_FIND

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)

FIND - FIND

ENC_IMR_FIND [3/3]

#define ENC_IMR_FIND

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)

FIND - FIND

ENC_IMR_FPHA [1/3]

#define ENC_IMR_FPHA

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)

FPHA - FPHA

ENC_IMR_FPHA [2/3]

#define ENC_IMR_FPHA

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)

FPHA - FPHA

ENC_IMR_FPHA [3/3]

#define ENC_IMR_FPHA

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)

FPHA - FPHA

ENC_IMR_FPHB [1/3]

#define ENC_IMR_FPHB

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)

FPHB - FPHB

ENC_IMR_FPHB [2/3]

#define ENC_IMR_FPHB

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)

FPHB - FPHB

ENC_IMR_FPHB [3/3]

#define ENC_IMR_FPHB

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)

FPHB - FPHB

ENC_IMR_HOME [1/3]

#define ENC_IMR_HOME

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)

HOME - HOME

ENC_IMR_HOME [2/3]

#define ENC_IMR_HOME

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)

HOME - HOME

ENC_IMR_HOME [3/3]

#define ENC_IMR_HOME

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)

HOME - HOME

ENC_IMR_INDEX [1/3]

#define ENC_IMR_INDEX

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)

INDEX - INDEX

ENC_IMR_INDEX [2/3]

#define ENC_IMR_INDEX

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)

INDEX - INDEX

ENC_IMR_INDEX [3/3]

#define ENC_IMR_INDEX

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)

INDEX - INDEX

ENC_IMR_PHA [1/3]

#define ENC_IMR_PHA

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)

PHA - PHA

ENC_IMR_PHA [2/3]

#define ENC_IMR_PHA

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)

PHA - PHA

ENC_IMR_PHA [3/3]

#define ENC_IMR_PHA

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)

PHA - PHA

ENC_IMR_PHB [1/3]

#define ENC_IMR_PHB

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)

PHB - PHB

ENC_IMR_PHB [2/3]

#define ENC_IMR_PHB

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)

PHB - PHB

ENC_IMR_PHB [3/3]

#define ENC_IMR_PHB

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)

PHB - PHB

ENC_LASTEDGE_LASTEDGE [1/2]

#define ENC_LASTEDGE_LASTEDGE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK)

LASTEDGE - Last Edge Time Counter

ENC_LASTEDGE_LASTEDGE [2/2]

#define ENC_LASTEDGE_LASTEDGE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK)

LASTEDGE - Last Edge Time Counter

ENC_LASTEDGEH_LASTEDGEH [1/2]

#define ENC_LASTEDGEH_LASTEDGEH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK)

LASTEDGEH - Last Edge Time Hold

ENC_LASTEDGEH_LASTEDGEH [2/2]

#define ENC_LASTEDGEH_LASTEDGEH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK)

LASTEDGEH - Last Edge Time Hold

ENC_LCOMP_COMP [1/3]

#define ENC_LCOMP_COMP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)

COMP - COMP

ENC_LCOMP_COMP [2/3]

#define ENC_LCOMP_COMP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)

COMP - COMP

ENC_LCOMP_COMP [3/3]

#define ENC_LCOMP_COMP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)

COMP - COMP

ENC_LINIT_INIT [1/3]

#define ENC_LINIT_INIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)

INIT - INIT

ENC_LINIT_INIT [2/3]

#define ENC_LINIT_INIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)

INIT - INIT

ENC_LINIT_INIT [3/3]

#define ENC_LINIT_INIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)

INIT - INIT

ENC_LMOD_MOD [1/3]

#define ENC_LMOD_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)

MOD - MOD

ENC_LMOD_MOD [2/3]

#define ENC_LMOD_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)

MOD - MOD

ENC_LMOD_MOD [3/3]

#define ENC_LMOD_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)

MOD - MOD

ENC_LPOS_POS [1/3]

#define ENC_LPOS_POS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)

POS - POS

ENC_LPOS_POS [2/3]

#define ENC_LPOS_POS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)

POS - POS

ENC_LPOS_POS [3/3]

#define ENC_LPOS_POS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)

POS - POS

ENC_LPOSH_POSH [1/3]

#define ENC_LPOSH_POSH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)

POSH - POSH

ENC_LPOSH_POSH [2/3]

#define ENC_LPOSH_POSH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)

POSH - POSH

ENC_LPOSH_POSH [3/3]

#define ENC_LPOSH_POSH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)

POSH - POSH

ENC_POSD_POSD [1/3]

#define ENC_POSD_POSD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)

POSD - POSD

ENC_POSD_POSD [2/3]

#define ENC_POSD_POSD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)

POSD - POSD

ENC_POSD_POSD [3/3]

#define ENC_POSD_POSD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)

POSD - POSD

ENC_POSDH_POSDH [1/3]

#define ENC_POSDH_POSDH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)

POSDH - POSDH

ENC_POSDH_POSDH [2/3]

#define ENC_POSDH_POSDH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)

POSDH - POSDH

ENC_POSDH_POSDH [3/3]

#define ENC_POSDH_POSDH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)

POSDH - POSDH

ENC_POSDPER_POSDPER [1/2]

#define ENC_POSDPER_POSDPER

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK)

POSDPER - Position difference period

ENC_POSDPER_POSDPER [2/2]

#define ENC_POSDPER_POSDPER

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK)

POSDPER - Position difference period

ENC_POSDPERBFR_POSDPERBFR [1/2]

#define ENC_POSDPERBFR_POSDPERBFR

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK)

POSDPERBFR - Position difference period buffer

ENC_POSDPERBFR_POSDPERBFR [2/2]

#define ENC_POSDPERBFR_POSDPERBFR

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK)

POSDPERBFR - Position difference period buffer

ENC_POSDPERH_POSDPERH [1/2]

#define ENC_POSDPERH_POSDPERH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK)

POSDPERH - Position difference period hold

ENC_POSDPERH_POSDPERH [2/2]

#define ENC_POSDPERH_POSDPERH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK)

POSDPERH - Position difference period hold

ENC_REV_REV [1/3]

#define ENC_REV_REV

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)

REV - REV

ENC_REV_REV [2/3]

#define ENC_REV_REV

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)

REV - REV

ENC_REV_REV [3/3]

#define ENC_REV_REV

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)

REV - REV

ENC_REVH_REVH [1/3]

#define ENC_REVH_REVH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)

REVH - REVH

ENC_REVH_REVH [2/3]

#define ENC_REVH_REVH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)

REVH - REVH

ENC_REVH_REVH [3/3]

#define ENC_REVH_REVH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)

REVH - REVH

ENC_TST_QDN [1/3]

#define ENC_TST_QDN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)

QDN - Quadrature Decoder Negative Signal 0b0..Generates a positive quadrature decoder signal 0b1..Generates a negative quadrature decoder signal

ENC_TST_QDN [2/3]

#define ENC_TST_QDN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)

QDN - Quadrature Decoder Negative Signal 0b0..Generates a positive quadrature decoder signal 0b1..Generates a negative quadrature decoder signal

ENC_TST_QDN [3/3]

#define ENC_TST_QDN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)

QDN - Quadrature Decoder Negative Signal 0b0..Generates a positive quadrature decoder signal 0b1..Generates a negative quadrature decoder signal

ENC_TST_TCE [1/3]

#define ENC_TST_TCE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)

TCE - Test Counter Enable 0b0..Disabled 0b1..Enabled

ENC_TST_TCE [2/3]

#define ENC_TST_TCE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)

TCE - Test Counter Enable 0b0..Disabled 0b1..Enabled

ENC_TST_TCE [3/3]

#define ENC_TST_TCE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)

TCE - Test Counter Enable 0b0..Disabled 0b1..Enabled

ENC_TST_TEN [1/3]

#define ENC_TST_TEN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)

TEN - Test Mode Enable 0b0..Disabled 0b1..Enabled

ENC_TST_TEN [2/3]

#define ENC_TST_TEN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)

TEN - Test Mode Enable 0b0..Disabled 0b1..Enabled

ENC_TST_TEN [3/3]

#define ENC_TST_TEN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)

TEN - Test Mode Enable 0b0..Disabled 0b1..Enabled

ENC_TST_TEST_COUNT [1/3]

#define ENC_TST_TEST_COUNT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)

TEST_COUNT - TEST_COUNT

ENC_TST_TEST_COUNT [2/3]

#define ENC_TST_TEST_COUNT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)

TEST_COUNT - TEST_COUNT

ENC_TST_TEST_COUNT [3/3]

#define ENC_TST_TEST_COUNT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)

TEST_COUNT - TEST_COUNT

ENC_TST_TEST_PERIOD [1/3]

#define ENC_TST_TEST_PERIOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)

TEST_PERIOD - TEST_PERIOD

ENC_TST_TEST_PERIOD [2/3]

#define ENC_TST_TEST_PERIOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)

TEST_PERIOD - TEST_PERIOD

ENC_TST_TEST_PERIOD [3/3]

#define ENC_TST_TEST_PERIOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)

TEST_PERIOD - TEST_PERIOD

ENC_UCOMP_COMP [1/3]

#define ENC_UCOMP_COMP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)

COMP - COMP

ENC_UCOMP_COMP [2/3]

#define ENC_UCOMP_COMP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)

COMP - COMP

ENC_UCOMP_COMP [3/3]

#define ENC_UCOMP_COMP

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)

COMP - COMP

ENC_UINIT_INIT [1/3]

#define ENC_UINIT_INIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)

INIT - INIT

ENC_UINIT_INIT [2/3]

#define ENC_UINIT_INIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)

INIT - INIT

ENC_UINIT_INIT [3/3]

#define ENC_UINIT_INIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)

INIT - INIT

ENC_UMOD_MOD [1/3]

#define ENC_UMOD_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)

MOD - MOD

ENC_UMOD_MOD [2/3]

#define ENC_UMOD_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)

MOD - MOD

ENC_UMOD_MOD [3/3]

#define ENC_UMOD_MOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)

MOD - MOD

ENC_UPOS_POS [1/3]

#define ENC_UPOS_POS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)

POS - POS

ENC_UPOS_POS [2/3]

#define ENC_UPOS_POS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)

POS - POS

ENC_UPOS_POS [3/3]

#define ENC_UPOS_POS

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)

POS - POS

ENC_UPOSH_POSH [1/3]

#define ENC_UPOSH_POSH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)

POSH - POSH

ENC_UPOSH_POSH [2/3]

#define ENC_UPOSH_POSH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)

POSH - POSH

ENC_UPOSH_POSH [3/3]

#define ENC_UPOSH_POSH

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)

POSH - POSH

ENC_WTR_WDOG [1/3]

#define ENC_WTR_WDOG

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)

WDOG - WDOG

ENC_WTR_WDOG [2/3]

#define ENC_WTR_WDOG

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)

WDOG - WDOG

ENC_WTR_WDOG [3/3]

#define ENC_WTR_WDOG

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)

WDOG - WDOG

EWM_CTRL_ASSIN [1/3]

#define EWM_CTRL_ASSIN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

ASSIN - EWM_in's Assertion State Select.

ASSIN - EWM_in's Assertion State Select. 0b0..Default assert state of the EWM_in signal. 0b1..Inverts the assert state of EWM_in signal.

EWM_CTRL_ASSIN [2/3]

#define EWM_CTRL_ASSIN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

ASSIN - EWM_in's Assertion State Select. 0b0..Default assert state of the EWM_in signal. 0b1..Inverts the assert state of EWM_in signal.

EWM_CTRL_ASSIN [3/3]

#define EWM_CTRL_ASSIN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

ASSIN - EWM_in's Assertion State Select. 0b0..Default assert state of the EWM_in signal. 0b1..Inverts the assert state of EWM_in signal.

EWM_CTRL_EWMEN [1/3]

#define EWM_CTRL_EWMEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

EWMEN - EWM enable.

EWMEN - EWM enable. 0b0..EWM module is disabled. 0b1..EWM module is enabled.

EWM_CTRL_EWMEN [2/3]

#define EWM_CTRL_EWMEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

EWMEN - EWM enable. 0b0..EWM module is disabled. 0b1..EWM module is enabled.

EWM_CTRL_EWMEN [3/3]

#define EWM_CTRL_EWMEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

EWMEN - EWM enable. 0b0..EWM module is disabled. 0b1..EWM module is enabled.

EWM_CTRL_INEN [1/3]

#define EWM_CTRL_INEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

INEN - Input Enable.

INEN - Input Enable. 0b0..EWM_in port is disabled. 0b1..EWM_in port is enabled.

EWM_CTRL_INEN [2/3]

#define EWM_CTRL_INEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

INEN - Input Enable. 0b0..EWM_in port is disabled. 0b1..EWM_in port is enabled.

EWM_CTRL_INEN [3/3]

#define EWM_CTRL_INEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

INEN - Input Enable. 0b0..EWM_in port is disabled. 0b1..EWM_in port is enabled.

EWM_CTRL_INTEN [1/3]

#define EWM_CTRL_INTEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)

INTEN - Interrupt Enable.

INTEN - Interrupt Enable. 0b1..Generates an interrupt request, when EWM_OUT_b is asserted. 0b0..Deasserts the interrupt request.

EWM_CTRL_INTEN [2/3]

#define EWM_CTRL_INTEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)

INTEN - Interrupt Enable. 0b1..Generates an interrupt request, when EWM_OUT_b is asserted. 0b0..Deasserts the interrupt request.

EWM_CTRL_INTEN [3/3]

#define EWM_CTRL_INTEN

(

x

)

Value:

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)

INTEN - Interrupt Enable. 0b1..Generates an interrupt request, when EWM_OUT_b is asserted. 0b0..Deasserts the interrupt request.

PWM_CTRL_COMPMODE [1/3]

#define PWM_CTRL_COMPMODE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)

COMPMODE - Compare Mode 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.

PWM_CTRL_COMPMODE [2/3]

#define PWM_CTRL_COMPMODE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)

COMPMODE - Compare Mode 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.

PWM_CTRL_COMPMODE [3/3]

#define PWM_CTRL_COMPMODE

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)

COMPMODE - Compare Mode 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.

PWM_CTRL_DBLEN [1/3]

#define PWM_CTRL_DBLEN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

DBLEN - Double Switching Enable 0b0..Double switching disabled. 0b1..Double switching enabled.

PWM_CTRL_DBLEN [2/3]

#define PWM_CTRL_DBLEN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

DBLEN - Double Switching Enable 0b0..Double switching disabled. 0b1..Double switching enabled.

PWM_CTRL_DBLEN [3/3]

#define PWM_CTRL_DBLEN

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

DBLEN - Double Switching Enable 0b0..Double switching disabled. 0b1..Double switching enabled.

PWM_CTRL_DBLX [1/3]

#define PWM_CTRL_DBLX

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

DBLX - PWMX Double Switching Enable 0b0..PWMX double pulse disabled. 0b1..PWMX double pulse enabled.

PWM_CTRL_DBLX [2/3]

#define PWM_CTRL_DBLX

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

DBLX - PWMX Double Switching Enable 0b0..PWMX double pulse disabled. 0b1..PWMX double pulse enabled.

PWM_CTRL_DBLX [3/3]

#define PWM_CTRL_DBLX

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

DBLX - PWMX Double Switching Enable 0b0..PWMX double pulse disabled. 0b1..PWMX double pulse enabled.

PWM_CTRL_DT [1/3]

#define PWM_CTRL_DT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

DT - Deadtime

PWM_CTRL_DT [2/3]

#define PWM_CTRL_DT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

DT - Deadtime

PWM_CTRL_DT [3/3]

#define PWM_CTRL_DT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

DT - Deadtime

PWM_CTRL_FULL [1/3]

#define PWM_CTRL_FULL

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

FULL - Full Cycle Reload 0b0..Full-cycle reloads disabled. 0b1..Full-cycle reloads enabled.

PWM_CTRL_FULL [2/3]

#define PWM_CTRL_FULL

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

FULL - Full Cycle Reload 0b0..Full-cycle reloads disabled. 0b1..Full-cycle reloads enabled.

PWM_CTRL_FULL [3/3]

#define PWM_CTRL_FULL

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

FULL - Full Cycle Reload 0b0..Full-cycle reloads disabled. 0b1..Full-cycle reloads enabled.

PWM_CTRL_HALF [1/3]

#define PWM_CTRL_HALF

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

HALF - Half Cycle Reload 0b0..Half-cycle reloads disabled. 0b1..Half-cycle reloads enabled.

PWM_CTRL_HALF [2/3]

#define PWM_CTRL_HALF

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

HALF - Half Cycle Reload 0b0..Half-cycle reloads disabled. 0b1..Half-cycle reloads enabled.

PWM_CTRL_HALF [3/3]

#define PWM_CTRL_HALF

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

HALF - Half Cycle Reload 0b0..Half-cycle reloads disabled. 0b1..Half-cycle reloads enabled.

PWM_CTRL_LDFQ [1/3]

#define PWM_CTRL_LDFQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

LDFQ - Load Frequency 0b0000..Every PWM opportunity 0b0001..Every 2 PWM opportunities 0b0010..Every 3 PWM opportunities 0b0011..Every 4 PWM opportunities 0b0100..Every 5 PWM opportunities 0b0101..Every 6 PWM opportunities 0b0110..Every 7 PWM opportunities 0b0111..Every 8 PWM opportunities 0b1000..Every 9 PWM opportunities 0b1001..Every 10 PWM opportunities 0b1010..Every 11 PWM opportunities 0b1011..Every 12 PWM opportunities 0b1100..Every 13 PWM opportunities 0b1101..Every 14 PWM opportunities 0b1110..Every 15 PWM opportunities 0b1111..Every 16 PWM opportunities

PWM_CTRL_LDFQ [2/3]

#define PWM_CTRL_LDFQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

LDFQ - Load Frequency 0b0000..Every PWM opportunity 0b0001..Every 2 PWM opportunities 0b0010..Every 3 PWM opportunities 0b0011..Every 4 PWM opportunities 0b0100..Every 5 PWM opportunities 0b0101..Every 6 PWM opportunities 0b0110..Every 7 PWM opportunities 0b0111..Every 8 PWM opportunities 0b1000..Every 9 PWM opportunities 0b1001..Every 10 PWM opportunities 0b1010..Every 11 PWM opportunities 0b1011..Every 12 PWM opportunities 0b1100..Every 13 PWM opportunities 0b1101..Every 14 PWM opportunities 0b1110..Every 15 PWM opportunities 0b1111..Every 16 PWM opportunities

PWM_CTRL_LDFQ [3/3]

#define PWM_CTRL_LDFQ

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

LDFQ - Load Frequency 0b0000..Every PWM opportunity 0b0001..Every 2 PWM opportunities 0b0010..Every 3 PWM opportunities 0b0011..Every 4 PWM opportunities 0b0100..Every 5 PWM opportunities 0b0101..Every 6 PWM opportunities 0b0110..Every 7 PWM opportunities 0b0111..Every 8 PWM opportunities 0b1000..Every 9 PWM opportunities 0b1001..Every 10 PWM opportunities 0b1010..Every 11 PWM opportunities 0b1011..Every 12 PWM opportunities 0b1100..Every 13 PWM opportunities 0b1101..Every 14 PWM opportunities 0b1110..Every 15 PWM opportunities 0b1111..Every 16 PWM opportunities

PWM_CTRL_LDMOD [1/3]

#define PWM_CTRL_LDMOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

LDMOD - Load Mode Select 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].

PWM_CTRL_LDMOD [2/3]

#define PWM_CTRL_LDMOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

LDMOD - Load Mode Select 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].

PWM_CTRL_LDMOD [3/3]

#define PWM_CTRL_LDMOD

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

LDMOD - Load Mode Select 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].

PWM_CTRL_PRSC [1/3]

#define PWM_CTRL_PRSC

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

PRSC - Prescaler 0b000..PWM clock frequency = fclk 0b001..PWM clock frequency = fclk/2 0b010..PWM clock frequency = fclk/4 0b011..PWM clock frequency = fclk/8 0b100..PWM clock frequency = fclk/16 0b101..PWM clock frequency = fclk/32 0b110..PWM clock frequency = fclk/64 0b111..PWM clock frequency = fclk/128

PRSC - Prescaler 0b000..Prescaler 1 0b001..Prescaler 2 0b010..Prescaler 4 0b011..Prescaler 8 0b100..Prescaler 16 0b101..Prescaler 32 0b110..Prescaler 64 0b111..Prescaler 128

PWM_CTRL_PRSC [2/3]

#define PWM_CTRL_PRSC

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

PRSC - Prescaler 0b000..Prescaler 1 0b001..Prescaler 2 0b010..Prescaler 4 0b011..Prescaler 8 0b100..Prescaler 16 0b101..Prescaler 32 0b110..Prescaler 64 0b111..Prescaler 128

PWM_CTRL_PRSC [3/3]

#define PWM_CTRL_PRSC

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

PRSC - Prescaler 0b000..Prescaler 1 0b001..Prescaler 2 0b010..Prescaler 4 0b011..Prescaler 8 0b100..Prescaler 16 0b101..Prescaler 32 0b110..Prescaler 64 0b111..Prescaler 128

PWM_CTRL_SPLIT [1/3]

#define PWM_CTRL_SPLIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)

SPLIT - Split the DBLPWM signal to PWMA and PWMB 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. 0b1..DBLPWM is split to PWMA and PWMB.

PWM_CTRL_SPLIT [2/3]

#define PWM_CTRL_SPLIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)

SPLIT - Split the DBLPWM signal to PWMA and PWMB 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. 0b1..DBLPWM is split to PWMA and PWMB.

PWM_CTRL_SPLIT [3/3]

#define PWM_CTRL_SPLIT

(

x

)

Value:

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)

SPLIT - Split the DBLPWM signal to PWMA and PWMB 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. 0b1..DBLPWM is split to PWMA and PWMB.