Macros
#define	DMA_SADDR_COUNT (32U)
#define	DMA_SOFF_COUNT (32U)
#define	DMA_ATTR_COUNT (32U)
#define	DMA_NBYTES_MLNO_COUNT (32U)
#define	DMA_NBYTES_MLOFFNO_COUNT (32U)
#define	DMA_NBYTES_MLOFFYES_COUNT (32U)
#define	DMA_SLAST_COUNT (32U)
#define	DMA_DADDR_COUNT (32U)
#define	DMA_DOFF_COUNT (32U)
#define	DMA_CITER_ELINKNO_COUNT (32U)
#define	DMA_CITER_ELINKYES_COUNT (32U)
#define	DMA_DLAST_SGA_COUNT (32U)
#define	DMA_CSR_COUNT (32U)
#define	DMA_BITER_ELINKNO_COUNT (32U)
#define	DMA_BITER_ELINKYES_COUNT (32U)
#define	DMA_SADDR_COUNT (32U)
#define	DMA_SOFF_COUNT (32U)
#define	DMA_ATTR_COUNT (32U)
#define	DMA_NBYTES_MLNO_COUNT (32U)
#define	DMA_NBYTES_MLOFFNO_COUNT (32U)
#define	DMA_NBYTES_MLOFFYES_COUNT (32U)
#define	DMA_SLAST_COUNT (32U)
#define	DMA_DADDR_COUNT (32U)
#define	DMA_DOFF_COUNT (32U)
#define	DMA_CITER_ELINKNO_COUNT (32U)
#define	DMA_CITER_ELINKYES_COUNT (32U)
#define	DMA_DLAST_SGA_COUNT (32U)
#define	DMA_CSR_COUNT (32U)
#define	DMA_BITER_ELINKNO_COUNT (32U)
#define	DMA_BITER_ELINKYES_COUNT (32U)
#define	DMA_SADDR_COUNT (32U)
#define	DMA_SOFF_COUNT (32U)
#define	DMA_ATTR_COUNT (32U)
#define	DMA_NBYTES_MLNO_COUNT (32U)
#define	DMA_NBYTES_MLOFFNO_COUNT (32U)
#define	DMA_NBYTES_MLOFFYES_COUNT (32U)
#define	DMA_SLAST_COUNT (32U)
#define	DMA_DADDR_COUNT (32U)
#define	DMA_DOFF_COUNT (32U)
#define	DMA_CITER_ELINKNO_COUNT (32U)
#define	DMA_CITER_ELINKYES_COUNT (32U)
#define	DMA_DLAST_SGA_COUNT (32U)
#define	DMA_CSR_COUNT (32U)
#define	DMA_BITER_ELINKNO_COUNT (32U)
#define	DMA_BITER_ELINKYES_COUNT (32U)

CR - Control
#define	DMA_CR_EDBG_MASK (0x2U)
#define	DMA_CR_EDBG_SHIFT (1U)
#define	DMA_CR_EDBG(x)
#define	DMA_CR_ERCA_MASK (0x4U)
#define	DMA_CR_ERCA_SHIFT (2U)
#define	DMA_CR_ERCA(x)
#define	DMA_CR_ERGA_MASK (0x8U)
#define	DMA_CR_ERGA_SHIFT (3U)
#define	DMA_CR_ERGA(x)
#define	DMA_CR_HOE_MASK (0x10U)
#define	DMA_CR_HOE_SHIFT (4U)
#define	DMA_CR_HOE(x)
#define	DMA_CR_HALT_MASK (0x20U)
#define	DMA_CR_HALT_SHIFT (5U)
#define	DMA_CR_HALT(x)
#define	DMA_CR_CLM_MASK (0x40U)
#define	DMA_CR_CLM_SHIFT (6U)
#define	DMA_CR_CLM(x)
#define	DMA_CR_EMLM_MASK (0x80U)
#define	DMA_CR_EMLM_SHIFT (7U)
#define	DMA_CR_EMLM(x)
#define	DMA_CR_GRP0PRI_MASK (0x100U)
#define	DMA_CR_GRP0PRI_SHIFT (8U)
#define	DMA_CR_GRP0PRI(x)
#define	DMA_CR_GRP1PRI_MASK (0x400U)
#define	DMA_CR_GRP1PRI_SHIFT (10U)
#define	DMA_CR_GRP1PRI(x)
#define	DMA_CR_ECX_MASK (0x10000U)
#define	DMA_CR_ECX_SHIFT (16U)
#define	DMA_CR_ECX(x)
#define	DMA_CR_CX_MASK (0x20000U)
#define	DMA_CR_CX_SHIFT (17U)
#define	DMA_CR_CX(x)
#define	DMA_CR_VERSION_MASK (0x7F000000U)
#define	DMA_CR_VERSION_SHIFT (24U)
#define	DMA_CR_VERSION(x)
#define	DMA_CR_ACTIVE_MASK (0x80000000U)
#define	DMA_CR_ACTIVE_SHIFT (31U)
#define	DMA_CR_ACTIVE(x)
#define	DMA_CR_EDBG_MASK (0x2U)
#define	DMA_CR_EDBG_SHIFT (1U)
#define	DMA_CR_EDBG(x)
#define	DMA_CR_ERCA_MASK (0x4U)
#define	DMA_CR_ERCA_SHIFT (2U)
#define	DMA_CR_ERCA(x)
#define	DMA_CR_ERGA_MASK (0x8U)
#define	DMA_CR_ERGA_SHIFT (3U)
#define	DMA_CR_ERGA(x)
#define	DMA_CR_HOE_MASK (0x10U)
#define	DMA_CR_HOE_SHIFT (4U)
#define	DMA_CR_HOE(x)
#define	DMA_CR_HALT_MASK (0x20U)
#define	DMA_CR_HALT_SHIFT (5U)
#define	DMA_CR_HALT(x)
#define	DMA_CR_CLM_MASK (0x40U)
#define	DMA_CR_CLM_SHIFT (6U)
#define	DMA_CR_CLM(x)
#define	DMA_CR_EMLM_MASK (0x80U)
#define	DMA_CR_EMLM_SHIFT (7U)
#define	DMA_CR_EMLM(x)
#define	DMA_CR_GRP0PRI_MASK (0x100U)
#define	DMA_CR_GRP0PRI_SHIFT (8U)
#define	DMA_CR_GRP0PRI(x)
#define	DMA_CR_GRP1PRI_MASK (0x400U)
#define	DMA_CR_GRP1PRI_SHIFT (10U)
#define	DMA_CR_GRP1PRI(x)
#define	DMA_CR_ECX_MASK (0x10000U)
#define	DMA_CR_ECX_SHIFT (16U)
#define	DMA_CR_ECX(x)
#define	DMA_CR_CX_MASK (0x20000U)
#define	DMA_CR_CX_SHIFT (17U)
#define	DMA_CR_CX(x)
#define	DMA_CR_VERSION_MASK (0x7F000000U)
#define	DMA_CR_VERSION_SHIFT (24U)
#define	DMA_CR_VERSION(x)
#define	DMA_CR_ACTIVE_MASK (0x80000000U)
#define	DMA_CR_ACTIVE_SHIFT (31U)
#define	DMA_CR_ACTIVE(x)
#define	DMA_CR_EDBG_MASK (0x2U)
#define	DMA_CR_EDBG_SHIFT (1U)
#define	DMA_CR_EDBG(x)
#define	DMA_CR_ERCA_MASK (0x4U)
#define	DMA_CR_ERCA_SHIFT (2U)
#define	DMA_CR_ERCA(x)
#define	DMA_CR_ERGA_MASK (0x8U)
#define	DMA_CR_ERGA_SHIFT (3U)
#define	DMA_CR_ERGA(x)
#define	DMA_CR_HOE_MASK (0x10U)
#define	DMA_CR_HOE_SHIFT (4U)
#define	DMA_CR_HOE(x)
#define	DMA_CR_HALT_MASK (0x20U)
#define	DMA_CR_HALT_SHIFT (5U)
#define	DMA_CR_HALT(x)
#define	DMA_CR_CLM_MASK (0x40U)
#define	DMA_CR_CLM_SHIFT (6U)
#define	DMA_CR_CLM(x)
#define	DMA_CR_EMLM_MASK (0x80U)
#define	DMA_CR_EMLM_SHIFT (7U)
#define	DMA_CR_EMLM(x)
#define	DMA_CR_GRP0PRI_MASK (0x100U)
#define	DMA_CR_GRP0PRI_SHIFT (8U)
#define	DMA_CR_GRP0PRI(x)
#define	DMA_CR_GRP1PRI_MASK (0x400U)
#define	DMA_CR_GRP1PRI_SHIFT (10U)
#define	DMA_CR_GRP1PRI(x)
#define	DMA_CR_ECX_MASK (0x10000U)
#define	DMA_CR_ECX_SHIFT (16U)
#define	DMA_CR_ECX(x)
#define	DMA_CR_CX_MASK (0x20000U)
#define	DMA_CR_CX_SHIFT (17U)
#define	DMA_CR_CX(x)
#define	DMA_CR_VERSION_MASK (0x7F000000U)
#define	DMA_CR_VERSION_SHIFT (24U)
#define	DMA_CR_VERSION(x)
#define	DMA_CR_ACTIVE_MASK (0x80000000U)
#define	DMA_CR_ACTIVE_SHIFT (31U)
#define	DMA_CR_ACTIVE(x)
#define	LPSPI_CR_MEN_MASK (0x1U)
#define	LPSPI_CR_MEN_SHIFT (0U)
#define	LPSPI_CR_MEN(x)
#define	LPSPI_CR_RST_MASK (0x2U)
#define	LPSPI_CR_RST_SHIFT (1U)
#define	LPSPI_CR_RST(x)
#define	LPSPI_CR_DOZEN_MASK (0x4U)
#define	LPSPI_CR_DOZEN_SHIFT (2U)
#define	LPSPI_CR_DOZEN(x)
#define	LPSPI_CR_DBGEN_MASK (0x8U)
#define	LPSPI_CR_DBGEN_SHIFT (3U)
#define	LPSPI_CR_DBGEN(x)
#define	LPSPI_CR_RTF_MASK (0x100U)
#define	LPSPI_CR_RTF_SHIFT (8U)
#define	LPSPI_CR_RTF(x)
#define	LPSPI_CR_RRF_MASK (0x200U)
#define	LPSPI_CR_RRF_SHIFT (9U)
#define	LPSPI_CR_RRF(x)
#define	LPSPI_CR_MEN_MASK (0x1U)
#define	LPSPI_CR_MEN_SHIFT (0U)
#define	LPSPI_CR_MEN(x)
#define	LPSPI_CR_RST_MASK (0x2U)
#define	LPSPI_CR_RST_SHIFT (1U)
#define	LPSPI_CR_RST(x)
#define	LPSPI_CR_DOZEN_MASK (0x4U)
#define	LPSPI_CR_DOZEN_SHIFT (2U)
#define	LPSPI_CR_DOZEN(x)
#define	LPSPI_CR_DBGEN_MASK (0x8U)
#define	LPSPI_CR_DBGEN_SHIFT (3U)
#define	LPSPI_CR_DBGEN(x)
#define	LPSPI_CR_RTF_MASK (0x100U)
#define	LPSPI_CR_RTF_SHIFT (8U)
#define	LPSPI_CR_RTF(x)
#define	LPSPI_CR_RRF_MASK (0x200U)
#define	LPSPI_CR_RRF_SHIFT (9U)
#define	LPSPI_CR_RRF(x)
#define	LPSPI_CR_MEN_MASK (0x1U)
#define	LPSPI_CR_MEN_SHIFT (0U)
#define	LPSPI_CR_MEN(x)
#define	LPSPI_CR_RST_MASK (0x2U)
#define	LPSPI_CR_RST_SHIFT (1U)
#define	LPSPI_CR_RST(x)
#define	LPSPI_CR_DOZEN_MASK (0x4U)
#define	LPSPI_CR_DOZEN_SHIFT (2U)
#define	LPSPI_CR_DOZEN(x)
#define	LPSPI_CR_DBGEN_MASK (0x8U)
#define	LPSPI_CR_DBGEN_SHIFT (3U)
#define	LPSPI_CR_DBGEN(x)
#define	LPSPI_CR_RTF_MASK (0x100U)
#define	LPSPI_CR_RTF_SHIFT (8U)
#define	LPSPI_CR_RTF(x)
#define	LPSPI_CR_RRF_MASK (0x200U)
#define	LPSPI_CR_RRF_SHIFT (9U)
#define	LPSPI_CR_RRF(x)

ES - Error Status
#define	DMA_ES_DBE_MASK (0x1U)
#define	DMA_ES_DBE_SHIFT (0U)
#define	DMA_ES_DBE(x)
#define	DMA_ES_SBE_MASK (0x2U)
#define	DMA_ES_SBE_SHIFT (1U)
#define	DMA_ES_SBE(x)
#define	DMA_ES_SGE_MASK (0x4U)
#define	DMA_ES_SGE_SHIFT (2U)
#define	DMA_ES_SGE(x)
#define	DMA_ES_NCE_MASK (0x8U)
#define	DMA_ES_NCE_SHIFT (3U)
#define	DMA_ES_NCE(x)
#define	DMA_ES_DOE_MASK (0x10U)
#define	DMA_ES_DOE_SHIFT (4U)
#define	DMA_ES_DOE(x)
#define	DMA_ES_DAE_MASK (0x20U)
#define	DMA_ES_DAE_SHIFT (5U)
#define	DMA_ES_DAE(x)
#define	DMA_ES_SOE_MASK (0x40U)
#define	DMA_ES_SOE_SHIFT (6U)
#define	DMA_ES_SOE(x)
#define	DMA_ES_SAE_MASK (0x80U)
#define	DMA_ES_SAE_SHIFT (7U)
#define	DMA_ES_SAE(x)
#define	DMA_ES_ERRCHN_MASK (0x1F00U)
#define	DMA_ES_ERRCHN_SHIFT (8U)
#define	DMA_ES_ERRCHN(x)
#define	DMA_ES_CPE_MASK (0x4000U)
#define	DMA_ES_CPE_SHIFT (14U)
#define	DMA_ES_CPE(x)
#define	DMA_ES_GPE_MASK (0x8000U)
#define	DMA_ES_GPE_SHIFT (15U)
#define	DMA_ES_GPE(x)
#define	DMA_ES_ECX_MASK (0x10000U)
#define	DMA_ES_ECX_SHIFT (16U)
#define	DMA_ES_ECX(x)
#define	DMA_ES_VLD_MASK (0x80000000U)
#define	DMA_ES_VLD_SHIFT (31U)
#define	DMA_ES_VLD(x)
#define	DMA_ES_DBE_MASK (0x1U)
#define	DMA_ES_DBE_SHIFT (0U)
#define	DMA_ES_DBE(x)
#define	DMA_ES_SBE_MASK (0x2U)
#define	DMA_ES_SBE_SHIFT (1U)
#define	DMA_ES_SBE(x)
#define	DMA_ES_SGE_MASK (0x4U)
#define	DMA_ES_SGE_SHIFT (2U)
#define	DMA_ES_SGE(x)
#define	DMA_ES_NCE_MASK (0x8U)
#define	DMA_ES_NCE_SHIFT (3U)
#define	DMA_ES_NCE(x)
#define	DMA_ES_DOE_MASK (0x10U)
#define	DMA_ES_DOE_SHIFT (4U)
#define	DMA_ES_DOE(x)
#define	DMA_ES_DAE_MASK (0x20U)
#define	DMA_ES_DAE_SHIFT (5U)
#define	DMA_ES_DAE(x)
#define	DMA_ES_SOE_MASK (0x40U)
#define	DMA_ES_SOE_SHIFT (6U)
#define	DMA_ES_SOE(x)
#define	DMA_ES_SAE_MASK (0x80U)
#define	DMA_ES_SAE_SHIFT (7U)
#define	DMA_ES_SAE(x)
#define	DMA_ES_ERRCHN_MASK (0x1F00U)
#define	DMA_ES_ERRCHN_SHIFT (8U)
#define	DMA_ES_ERRCHN(x)
#define	DMA_ES_CPE_MASK (0x4000U)
#define	DMA_ES_CPE_SHIFT (14U)
#define	DMA_ES_CPE(x)
#define	DMA_ES_GPE_MASK (0x8000U)
#define	DMA_ES_GPE_SHIFT (15U)
#define	DMA_ES_GPE(x)
#define	DMA_ES_ECX_MASK (0x10000U)
#define	DMA_ES_ECX_SHIFT (16U)
#define	DMA_ES_ECX(x)
#define	DMA_ES_VLD_MASK (0x80000000U)
#define	DMA_ES_VLD_SHIFT (31U)
#define	DMA_ES_VLD(x)
#define	DMA_ES_DBE_MASK (0x1U)
#define	DMA_ES_DBE_SHIFT (0U)
#define	DMA_ES_DBE(x)
#define	DMA_ES_SBE_MASK (0x2U)
#define	DMA_ES_SBE_SHIFT (1U)
#define	DMA_ES_SBE(x)
#define	DMA_ES_SGE_MASK (0x4U)
#define	DMA_ES_SGE_SHIFT (2U)
#define	DMA_ES_SGE(x)
#define	DMA_ES_NCE_MASK (0x8U)
#define	DMA_ES_NCE_SHIFT (3U)
#define	DMA_ES_NCE(x)
#define	DMA_ES_DOE_MASK (0x10U)
#define	DMA_ES_DOE_SHIFT (4U)
#define	DMA_ES_DOE(x)
#define	DMA_ES_DAE_MASK (0x20U)
#define	DMA_ES_DAE_SHIFT (5U)
#define	DMA_ES_DAE(x)
#define	DMA_ES_SOE_MASK (0x40U)
#define	DMA_ES_SOE_SHIFT (6U)
#define	DMA_ES_SOE(x)
#define	DMA_ES_SAE_MASK (0x80U)
#define	DMA_ES_SAE_SHIFT (7U)
#define	DMA_ES_SAE(x)
#define	DMA_ES_ERRCHN_MASK (0x1F00U)
#define	DMA_ES_ERRCHN_SHIFT (8U)
#define	DMA_ES_ERRCHN(x)
#define	DMA_ES_CPE_MASK (0x4000U)
#define	DMA_ES_CPE_SHIFT (14U)
#define	DMA_ES_CPE(x)
#define	DMA_ES_GPE_MASK (0x8000U)
#define	DMA_ES_GPE_SHIFT (15U)
#define	DMA_ES_GPE(x)
#define	DMA_ES_ECX_MASK (0x10000U)
#define	DMA_ES_ECX_SHIFT (16U)
#define	DMA_ES_ECX(x)
#define	DMA_ES_VLD_MASK (0x80000000U)
#define	DMA_ES_VLD_SHIFT (31U)
#define	DMA_ES_VLD(x)

ERQ - Enable Request
#define	DMA_ERQ_ERQ0_MASK (0x1U)
#define	DMA_ERQ_ERQ0_SHIFT (0U)
#define	DMA_ERQ_ERQ0(x)
#define	DMA_ERQ_ERQ1_MASK (0x2U)
#define	DMA_ERQ_ERQ1_SHIFT (1U)
#define	DMA_ERQ_ERQ1(x)
#define	DMA_ERQ_ERQ2_MASK (0x4U)
#define	DMA_ERQ_ERQ2_SHIFT (2U)
#define	DMA_ERQ_ERQ2(x)
#define	DMA_ERQ_ERQ3_MASK (0x8U)
#define	DMA_ERQ_ERQ3_SHIFT (3U)
#define	DMA_ERQ_ERQ3(x)
#define	DMA_ERQ_ERQ4_MASK (0x10U)
#define	DMA_ERQ_ERQ4_SHIFT (4U)
#define	DMA_ERQ_ERQ4(x)
#define	DMA_ERQ_ERQ5_MASK (0x20U)
#define	DMA_ERQ_ERQ5_SHIFT (5U)
#define	DMA_ERQ_ERQ5(x)
#define	DMA_ERQ_ERQ6_MASK (0x40U)
#define	DMA_ERQ_ERQ6_SHIFT (6U)
#define	DMA_ERQ_ERQ6(x)
#define	DMA_ERQ_ERQ7_MASK (0x80U)
#define	DMA_ERQ_ERQ7_SHIFT (7U)
#define	DMA_ERQ_ERQ7(x)
#define	DMA_ERQ_ERQ8_MASK (0x100U)
#define	DMA_ERQ_ERQ8_SHIFT (8U)
#define	DMA_ERQ_ERQ8(x)
#define	DMA_ERQ_ERQ9_MASK (0x200U)
#define	DMA_ERQ_ERQ9_SHIFT (9U)
#define	DMA_ERQ_ERQ9(x)
#define	DMA_ERQ_ERQ10_MASK (0x400U)
#define	DMA_ERQ_ERQ10_SHIFT (10U)
#define	DMA_ERQ_ERQ10(x)
#define	DMA_ERQ_ERQ11_MASK (0x800U)
#define	DMA_ERQ_ERQ11_SHIFT (11U)
#define	DMA_ERQ_ERQ11(x)
#define	DMA_ERQ_ERQ12_MASK (0x1000U)
#define	DMA_ERQ_ERQ12_SHIFT (12U)
#define	DMA_ERQ_ERQ12(x)
#define	DMA_ERQ_ERQ13_MASK (0x2000U)
#define	DMA_ERQ_ERQ13_SHIFT (13U)
#define	DMA_ERQ_ERQ13(x)
#define	DMA_ERQ_ERQ14_MASK (0x4000U)
#define	DMA_ERQ_ERQ14_SHIFT (14U)
#define	DMA_ERQ_ERQ14(x)
#define	DMA_ERQ_ERQ15_MASK (0x8000U)
#define	DMA_ERQ_ERQ15_SHIFT (15U)
#define	DMA_ERQ_ERQ15(x)
#define	DMA_ERQ_ERQ16_MASK (0x10000U)
#define	DMA_ERQ_ERQ16_SHIFT (16U)
#define	DMA_ERQ_ERQ16(x)
#define	DMA_ERQ_ERQ17_MASK (0x20000U)
#define	DMA_ERQ_ERQ17_SHIFT (17U)
#define	DMA_ERQ_ERQ17(x)
#define	DMA_ERQ_ERQ18_MASK (0x40000U)
#define	DMA_ERQ_ERQ18_SHIFT (18U)
#define	DMA_ERQ_ERQ18(x)
#define	DMA_ERQ_ERQ19_MASK (0x80000U)
#define	DMA_ERQ_ERQ19_SHIFT (19U)
#define	DMA_ERQ_ERQ19(x)
#define	DMA_ERQ_ERQ20_MASK (0x100000U)
#define	DMA_ERQ_ERQ20_SHIFT (20U)
#define	DMA_ERQ_ERQ20(x)
#define	DMA_ERQ_ERQ21_MASK (0x200000U)
#define	DMA_ERQ_ERQ21_SHIFT (21U)
#define	DMA_ERQ_ERQ21(x)
#define	DMA_ERQ_ERQ22_MASK (0x400000U)
#define	DMA_ERQ_ERQ22_SHIFT (22U)
#define	DMA_ERQ_ERQ22(x)
#define	DMA_ERQ_ERQ23_MASK (0x800000U)
#define	DMA_ERQ_ERQ23_SHIFT (23U)
#define	DMA_ERQ_ERQ23(x)
#define	DMA_ERQ_ERQ24_MASK (0x1000000U)
#define	DMA_ERQ_ERQ24_SHIFT (24U)
#define	DMA_ERQ_ERQ24(x)
#define	DMA_ERQ_ERQ25_MASK (0x2000000U)
#define	DMA_ERQ_ERQ25_SHIFT (25U)
#define	DMA_ERQ_ERQ25(x)
#define	DMA_ERQ_ERQ26_MASK (0x4000000U)
#define	DMA_ERQ_ERQ26_SHIFT (26U)
#define	DMA_ERQ_ERQ26(x)
#define	DMA_ERQ_ERQ27_MASK (0x8000000U)
#define	DMA_ERQ_ERQ27_SHIFT (27U)
#define	DMA_ERQ_ERQ27(x)
#define	DMA_ERQ_ERQ28_MASK (0x10000000U)
#define	DMA_ERQ_ERQ28_SHIFT (28U)
#define	DMA_ERQ_ERQ28(x)
#define	DMA_ERQ_ERQ29_MASK (0x20000000U)
#define	DMA_ERQ_ERQ29_SHIFT (29U)
#define	DMA_ERQ_ERQ29(x)
#define	DMA_ERQ_ERQ30_MASK (0x40000000U)
#define	DMA_ERQ_ERQ30_SHIFT (30U)
#define	DMA_ERQ_ERQ30(x)
#define	DMA_ERQ_ERQ31_MASK (0x80000000U)
#define	DMA_ERQ_ERQ31_SHIFT (31U)
#define	DMA_ERQ_ERQ31(x)
#define	DMA_ERQ_ERQ0_MASK (0x1U)
#define	DMA_ERQ_ERQ0_SHIFT (0U)
#define	DMA_ERQ_ERQ0(x)
#define	DMA_ERQ_ERQ1_MASK (0x2U)
#define	DMA_ERQ_ERQ1_SHIFT (1U)
#define	DMA_ERQ_ERQ1(x)
#define	DMA_ERQ_ERQ2_MASK (0x4U)
#define	DMA_ERQ_ERQ2_SHIFT (2U)
#define	DMA_ERQ_ERQ2(x)
#define	DMA_ERQ_ERQ3_MASK (0x8U)
#define	DMA_ERQ_ERQ3_SHIFT (3U)
#define	DMA_ERQ_ERQ3(x)
#define	DMA_ERQ_ERQ4_MASK (0x10U)
#define	DMA_ERQ_ERQ4_SHIFT (4U)
#define	DMA_ERQ_ERQ4(x)
#define	DMA_ERQ_ERQ5_MASK (0x20U)
#define	DMA_ERQ_ERQ5_SHIFT (5U)
#define	DMA_ERQ_ERQ5(x)
#define	DMA_ERQ_ERQ6_MASK (0x40U)
#define	DMA_ERQ_ERQ6_SHIFT (6U)
#define	DMA_ERQ_ERQ6(x)
#define	DMA_ERQ_ERQ7_MASK (0x80U)
#define	DMA_ERQ_ERQ7_SHIFT (7U)
#define	DMA_ERQ_ERQ7(x)
#define	DMA_ERQ_ERQ8_MASK (0x100U)
#define	DMA_ERQ_ERQ8_SHIFT (8U)
#define	DMA_ERQ_ERQ8(x)
#define	DMA_ERQ_ERQ9_MASK (0x200U)
#define	DMA_ERQ_ERQ9_SHIFT (9U)
#define	DMA_ERQ_ERQ9(x)
#define	DMA_ERQ_ERQ10_MASK (0x400U)
#define	DMA_ERQ_ERQ10_SHIFT (10U)
#define	DMA_ERQ_ERQ10(x)
#define	DMA_ERQ_ERQ11_MASK (0x800U)
#define	DMA_ERQ_ERQ11_SHIFT (11U)
#define	DMA_ERQ_ERQ11(x)
#define	DMA_ERQ_ERQ12_MASK (0x1000U)
#define	DMA_ERQ_ERQ12_SHIFT (12U)
#define	DMA_ERQ_ERQ12(x)
#define	DMA_ERQ_ERQ13_MASK (0x2000U)
#define	DMA_ERQ_ERQ13_SHIFT (13U)
#define	DMA_ERQ_ERQ13(x)
#define	DMA_ERQ_ERQ14_MASK (0x4000U)
#define	DMA_ERQ_ERQ14_SHIFT (14U)
#define	DMA_ERQ_ERQ14(x)
#define	DMA_ERQ_ERQ15_MASK (0x8000U)
#define	DMA_ERQ_ERQ15_SHIFT (15U)
#define	DMA_ERQ_ERQ15(x)
#define	DMA_ERQ_ERQ16_MASK (0x10000U)
#define	DMA_ERQ_ERQ16_SHIFT (16U)
#define	DMA_ERQ_ERQ16(x)
#define	DMA_ERQ_ERQ17_MASK (0x20000U)
#define	DMA_ERQ_ERQ17_SHIFT (17U)
#define	DMA_ERQ_ERQ17(x)
#define	DMA_ERQ_ERQ18_MASK (0x40000U)
#define	DMA_ERQ_ERQ18_SHIFT (18U)
#define	DMA_ERQ_ERQ18(x)
#define	DMA_ERQ_ERQ19_MASK (0x80000U)
#define	DMA_ERQ_ERQ19_SHIFT (19U)
#define	DMA_ERQ_ERQ19(x)
#define	DMA_ERQ_ERQ20_MASK (0x100000U)
#define	DMA_ERQ_ERQ20_SHIFT (20U)
#define	DMA_ERQ_ERQ20(x)
#define	DMA_ERQ_ERQ21_MASK (0x200000U)
#define	DMA_ERQ_ERQ21_SHIFT (21U)
#define	DMA_ERQ_ERQ21(x)
#define	DMA_ERQ_ERQ22_MASK (0x400000U)
#define	DMA_ERQ_ERQ22_SHIFT (22U)
#define	DMA_ERQ_ERQ22(x)
#define	DMA_ERQ_ERQ23_MASK (0x800000U)
#define	DMA_ERQ_ERQ23_SHIFT (23U)
#define	DMA_ERQ_ERQ23(x)
#define	DMA_ERQ_ERQ24_MASK (0x1000000U)
#define	DMA_ERQ_ERQ24_SHIFT (24U)
#define	DMA_ERQ_ERQ24(x)
#define	DMA_ERQ_ERQ25_MASK (0x2000000U)
#define	DMA_ERQ_ERQ25_SHIFT (25U)
#define	DMA_ERQ_ERQ25(x)
#define	DMA_ERQ_ERQ26_MASK (0x4000000U)
#define	DMA_ERQ_ERQ26_SHIFT (26U)
#define	DMA_ERQ_ERQ26(x)
#define	DMA_ERQ_ERQ27_MASK (0x8000000U)
#define	DMA_ERQ_ERQ27_SHIFT (27U)
#define	DMA_ERQ_ERQ27(x)
#define	DMA_ERQ_ERQ28_MASK (0x10000000U)
#define	DMA_ERQ_ERQ28_SHIFT (28U)
#define	DMA_ERQ_ERQ28(x)
#define	DMA_ERQ_ERQ29_MASK (0x20000000U)
#define	DMA_ERQ_ERQ29_SHIFT (29U)
#define	DMA_ERQ_ERQ29(x)
#define	DMA_ERQ_ERQ30_MASK (0x40000000U)
#define	DMA_ERQ_ERQ30_SHIFT (30U)
#define	DMA_ERQ_ERQ30(x)
#define	DMA_ERQ_ERQ31_MASK (0x80000000U)
#define	DMA_ERQ_ERQ31_SHIFT (31U)
#define	DMA_ERQ_ERQ31(x)
#define	DMA_ERQ_ERQ0_MASK (0x1U)
#define	DMA_ERQ_ERQ0_SHIFT (0U)
#define	DMA_ERQ_ERQ0(x)
#define	DMA_ERQ_ERQ1_MASK (0x2U)
#define	DMA_ERQ_ERQ1_SHIFT (1U)
#define	DMA_ERQ_ERQ1(x)
#define	DMA_ERQ_ERQ2_MASK (0x4U)
#define	DMA_ERQ_ERQ2_SHIFT (2U)
#define	DMA_ERQ_ERQ2(x)
#define	DMA_ERQ_ERQ3_MASK (0x8U)
#define	DMA_ERQ_ERQ3_SHIFT (3U)
#define	DMA_ERQ_ERQ3(x)
#define	DMA_ERQ_ERQ4_MASK (0x10U)
#define	DMA_ERQ_ERQ4_SHIFT (4U)
#define	DMA_ERQ_ERQ4(x)
#define	DMA_ERQ_ERQ5_MASK (0x20U)
#define	DMA_ERQ_ERQ5_SHIFT (5U)
#define	DMA_ERQ_ERQ5(x)
#define	DMA_ERQ_ERQ6_MASK (0x40U)
#define	DMA_ERQ_ERQ6_SHIFT (6U)
#define	DMA_ERQ_ERQ6(x)
#define	DMA_ERQ_ERQ7_MASK (0x80U)
#define	DMA_ERQ_ERQ7_SHIFT (7U)
#define	DMA_ERQ_ERQ7(x)
#define	DMA_ERQ_ERQ8_MASK (0x100U)
#define	DMA_ERQ_ERQ8_SHIFT (8U)
#define	DMA_ERQ_ERQ8(x)
#define	DMA_ERQ_ERQ9_MASK (0x200U)
#define	DMA_ERQ_ERQ9_SHIFT (9U)
#define	DMA_ERQ_ERQ9(x)
#define	DMA_ERQ_ERQ10_MASK (0x400U)
#define	DMA_ERQ_ERQ10_SHIFT (10U)
#define	DMA_ERQ_ERQ10(x)
#define	DMA_ERQ_ERQ11_MASK (0x800U)
#define	DMA_ERQ_ERQ11_SHIFT (11U)
#define	DMA_ERQ_ERQ11(x)
#define	DMA_ERQ_ERQ12_MASK (0x1000U)
#define	DMA_ERQ_ERQ12_SHIFT (12U)
#define	DMA_ERQ_ERQ12(x)
#define	DMA_ERQ_ERQ13_MASK (0x2000U)
#define	DMA_ERQ_ERQ13_SHIFT (13U)
#define	DMA_ERQ_ERQ13(x)
#define	DMA_ERQ_ERQ14_MASK (0x4000U)
#define	DMA_ERQ_ERQ14_SHIFT (14U)
#define	DMA_ERQ_ERQ14(x)
#define	DMA_ERQ_ERQ15_MASK (0x8000U)
#define	DMA_ERQ_ERQ15_SHIFT (15U)
#define	DMA_ERQ_ERQ15(x)
#define	DMA_ERQ_ERQ16_MASK (0x10000U)
#define	DMA_ERQ_ERQ16_SHIFT (16U)
#define	DMA_ERQ_ERQ16(x)
#define	DMA_ERQ_ERQ17_MASK (0x20000U)
#define	DMA_ERQ_ERQ17_SHIFT (17U)
#define	DMA_ERQ_ERQ17(x)
#define	DMA_ERQ_ERQ18_MASK (0x40000U)
#define	DMA_ERQ_ERQ18_SHIFT (18U)
#define	DMA_ERQ_ERQ18(x)
#define	DMA_ERQ_ERQ19_MASK (0x80000U)
#define	DMA_ERQ_ERQ19_SHIFT (19U)
#define	DMA_ERQ_ERQ19(x)
#define	DMA_ERQ_ERQ20_MASK (0x100000U)
#define	DMA_ERQ_ERQ20_SHIFT (20U)
#define	DMA_ERQ_ERQ20(x)
#define	DMA_ERQ_ERQ21_MASK (0x200000U)
#define	DMA_ERQ_ERQ21_SHIFT (21U)
#define	DMA_ERQ_ERQ21(x)
#define	DMA_ERQ_ERQ22_MASK (0x400000U)
#define	DMA_ERQ_ERQ22_SHIFT (22U)
#define	DMA_ERQ_ERQ22(x)
#define	DMA_ERQ_ERQ23_MASK (0x800000U)
#define	DMA_ERQ_ERQ23_SHIFT (23U)
#define	DMA_ERQ_ERQ23(x)
#define	DMA_ERQ_ERQ24_MASK (0x1000000U)
#define	DMA_ERQ_ERQ24_SHIFT (24U)
#define	DMA_ERQ_ERQ24(x)
#define	DMA_ERQ_ERQ25_MASK (0x2000000U)
#define	DMA_ERQ_ERQ25_SHIFT (25U)
#define	DMA_ERQ_ERQ25(x)
#define	DMA_ERQ_ERQ26_MASK (0x4000000U)
#define	DMA_ERQ_ERQ26_SHIFT (26U)
#define	DMA_ERQ_ERQ26(x)
#define	DMA_ERQ_ERQ27_MASK (0x8000000U)
#define	DMA_ERQ_ERQ27_SHIFT (27U)
#define	DMA_ERQ_ERQ27(x)
#define	DMA_ERQ_ERQ28_MASK (0x10000000U)
#define	DMA_ERQ_ERQ28_SHIFT (28U)
#define	DMA_ERQ_ERQ28(x)
#define	DMA_ERQ_ERQ29_MASK (0x20000000U)
#define	DMA_ERQ_ERQ29_SHIFT (29U)
#define	DMA_ERQ_ERQ29(x)
#define	DMA_ERQ_ERQ30_MASK (0x40000000U)
#define	DMA_ERQ_ERQ30_SHIFT (30U)
#define	DMA_ERQ_ERQ30(x)
#define	DMA_ERQ_ERQ31_MASK (0x80000000U)
#define	DMA_ERQ_ERQ31_SHIFT (31U)
#define	DMA_ERQ_ERQ31(x)

EEI - Enable Error Interrupt
#define	DMA_EEI_EEI0_MASK (0x1U)
#define	DMA_EEI_EEI0_SHIFT (0U)
#define	DMA_EEI_EEI0(x)
#define	DMA_EEI_EEI1_MASK (0x2U)
#define	DMA_EEI_EEI1_SHIFT (1U)
#define	DMA_EEI_EEI1(x)
#define	DMA_EEI_EEI2_MASK (0x4U)
#define	DMA_EEI_EEI2_SHIFT (2U)
#define	DMA_EEI_EEI2(x)
#define	DMA_EEI_EEI3_MASK (0x8U)
#define	DMA_EEI_EEI3_SHIFT (3U)
#define	DMA_EEI_EEI3(x)
#define	DMA_EEI_EEI4_MASK (0x10U)
#define	DMA_EEI_EEI4_SHIFT (4U)
#define	DMA_EEI_EEI4(x)
#define	DMA_EEI_EEI5_MASK (0x20U)
#define	DMA_EEI_EEI5_SHIFT (5U)
#define	DMA_EEI_EEI5(x)
#define	DMA_EEI_EEI6_MASK (0x40U)
#define	DMA_EEI_EEI6_SHIFT (6U)
#define	DMA_EEI_EEI6(x)
#define	DMA_EEI_EEI7_MASK (0x80U)
#define	DMA_EEI_EEI7_SHIFT (7U)
#define	DMA_EEI_EEI7(x)
#define	DMA_EEI_EEI8_MASK (0x100U)
#define	DMA_EEI_EEI8_SHIFT (8U)
#define	DMA_EEI_EEI8(x)
#define	DMA_EEI_EEI9_MASK (0x200U)
#define	DMA_EEI_EEI9_SHIFT (9U)
#define	DMA_EEI_EEI9(x)
#define	DMA_EEI_EEI10_MASK (0x400U)
#define	DMA_EEI_EEI10_SHIFT (10U)
#define	DMA_EEI_EEI10(x)
#define	DMA_EEI_EEI11_MASK (0x800U)
#define	DMA_EEI_EEI11_SHIFT (11U)
#define	DMA_EEI_EEI11(x)
#define	DMA_EEI_EEI12_MASK (0x1000U)
#define	DMA_EEI_EEI12_SHIFT (12U)
#define	DMA_EEI_EEI12(x)
#define	DMA_EEI_EEI13_MASK (0x2000U)
#define	DMA_EEI_EEI13_SHIFT (13U)
#define	DMA_EEI_EEI13(x)
#define	DMA_EEI_EEI14_MASK (0x4000U)
#define	DMA_EEI_EEI14_SHIFT (14U)
#define	DMA_EEI_EEI14(x)
#define	DMA_EEI_EEI15_MASK (0x8000U)
#define	DMA_EEI_EEI15_SHIFT (15U)
#define	DMA_EEI_EEI15(x)
#define	DMA_EEI_EEI16_MASK (0x10000U)
#define	DMA_EEI_EEI16_SHIFT (16U)
#define	DMA_EEI_EEI16(x)
#define	DMA_EEI_EEI17_MASK (0x20000U)
#define	DMA_EEI_EEI17_SHIFT (17U)
#define	DMA_EEI_EEI17(x)
#define	DMA_EEI_EEI18_MASK (0x40000U)
#define	DMA_EEI_EEI18_SHIFT (18U)
#define	DMA_EEI_EEI18(x)
#define	DMA_EEI_EEI19_MASK (0x80000U)
#define	DMA_EEI_EEI19_SHIFT (19U)
#define	DMA_EEI_EEI19(x)
#define	DMA_EEI_EEI20_MASK (0x100000U)
#define	DMA_EEI_EEI20_SHIFT (20U)
#define	DMA_EEI_EEI20(x)
#define	DMA_EEI_EEI21_MASK (0x200000U)
#define	DMA_EEI_EEI21_SHIFT (21U)
#define	DMA_EEI_EEI21(x)
#define	DMA_EEI_EEI22_MASK (0x400000U)
#define	DMA_EEI_EEI22_SHIFT (22U)
#define	DMA_EEI_EEI22(x)
#define	DMA_EEI_EEI23_MASK (0x800000U)
#define	DMA_EEI_EEI23_SHIFT (23U)
#define	DMA_EEI_EEI23(x)
#define	DMA_EEI_EEI24_MASK (0x1000000U)
#define	DMA_EEI_EEI24_SHIFT (24U)
#define	DMA_EEI_EEI24(x)
#define	DMA_EEI_EEI25_MASK (0x2000000U)
#define	DMA_EEI_EEI25_SHIFT (25U)
#define	DMA_EEI_EEI25(x)
#define	DMA_EEI_EEI26_MASK (0x4000000U)
#define	DMA_EEI_EEI26_SHIFT (26U)
#define	DMA_EEI_EEI26(x)
#define	DMA_EEI_EEI27_MASK (0x8000000U)
#define	DMA_EEI_EEI27_SHIFT (27U)
#define	DMA_EEI_EEI27(x)
#define	DMA_EEI_EEI28_MASK (0x10000000U)
#define	DMA_EEI_EEI28_SHIFT (28U)
#define	DMA_EEI_EEI28(x)
#define	DMA_EEI_EEI29_MASK (0x20000000U)
#define	DMA_EEI_EEI29_SHIFT (29U)
#define	DMA_EEI_EEI29(x)
#define	DMA_EEI_EEI30_MASK (0x40000000U)
#define	DMA_EEI_EEI30_SHIFT (30U)
#define	DMA_EEI_EEI30(x)
#define	DMA_EEI_EEI31_MASK (0x80000000U)
#define	DMA_EEI_EEI31_SHIFT (31U)
#define	DMA_EEI_EEI31(x)
#define	DMA_EEI_EEI0_MASK (0x1U)
#define	DMA_EEI_EEI0_SHIFT (0U)
#define	DMA_EEI_EEI0(x)
#define	DMA_EEI_EEI1_MASK (0x2U)
#define	DMA_EEI_EEI1_SHIFT (1U)
#define	DMA_EEI_EEI1(x)
#define	DMA_EEI_EEI2_MASK (0x4U)
#define	DMA_EEI_EEI2_SHIFT (2U)
#define	DMA_EEI_EEI2(x)
#define	DMA_EEI_EEI3_MASK (0x8U)
#define	DMA_EEI_EEI3_SHIFT (3U)
#define	DMA_EEI_EEI3(x)
#define	DMA_EEI_EEI4_MASK (0x10U)
#define	DMA_EEI_EEI4_SHIFT (4U)
#define	DMA_EEI_EEI4(x)
#define	DMA_EEI_EEI5_MASK (0x20U)
#define	DMA_EEI_EEI5_SHIFT (5U)
#define	DMA_EEI_EEI5(x)
#define	DMA_EEI_EEI6_MASK (0x40U)
#define	DMA_EEI_EEI6_SHIFT (6U)
#define	DMA_EEI_EEI6(x)
#define	DMA_EEI_EEI7_MASK (0x80U)
#define	DMA_EEI_EEI7_SHIFT (7U)
#define	DMA_EEI_EEI7(x)
#define	DMA_EEI_EEI8_MASK (0x100U)
#define	DMA_EEI_EEI8_SHIFT (8U)
#define	DMA_EEI_EEI8(x)
#define	DMA_EEI_EEI9_MASK (0x200U)
#define	DMA_EEI_EEI9_SHIFT (9U)
#define	DMA_EEI_EEI9(x)
#define	DMA_EEI_EEI10_MASK (0x400U)
#define	DMA_EEI_EEI10_SHIFT (10U)
#define	DMA_EEI_EEI10(x)
#define	DMA_EEI_EEI11_MASK (0x800U)
#define	DMA_EEI_EEI11_SHIFT (11U)
#define	DMA_EEI_EEI11(x)
#define	DMA_EEI_EEI12_MASK (0x1000U)
#define	DMA_EEI_EEI12_SHIFT (12U)
#define	DMA_EEI_EEI12(x)
#define	DMA_EEI_EEI13_MASK (0x2000U)
#define	DMA_EEI_EEI13_SHIFT (13U)
#define	DMA_EEI_EEI13(x)
#define	DMA_EEI_EEI14_MASK (0x4000U)
#define	DMA_EEI_EEI14_SHIFT (14U)
#define	DMA_EEI_EEI14(x)
#define	DMA_EEI_EEI15_MASK (0x8000U)
#define	DMA_EEI_EEI15_SHIFT (15U)
#define	DMA_EEI_EEI15(x)
#define	DMA_EEI_EEI16_MASK (0x10000U)
#define	DMA_EEI_EEI16_SHIFT (16U)
#define	DMA_EEI_EEI16(x)
#define	DMA_EEI_EEI17_MASK (0x20000U)
#define	DMA_EEI_EEI17_SHIFT (17U)
#define	DMA_EEI_EEI17(x)
#define	DMA_EEI_EEI18_MASK (0x40000U)
#define	DMA_EEI_EEI18_SHIFT (18U)
#define	DMA_EEI_EEI18(x)
#define	DMA_EEI_EEI19_MASK (0x80000U)
#define	DMA_EEI_EEI19_SHIFT (19U)
#define	DMA_EEI_EEI19(x)
#define	DMA_EEI_EEI20_MASK (0x100000U)
#define	DMA_EEI_EEI20_SHIFT (20U)
#define	DMA_EEI_EEI20(x)
#define	DMA_EEI_EEI21_MASK (0x200000U)
#define	DMA_EEI_EEI21_SHIFT (21U)
#define	DMA_EEI_EEI21(x)
#define	DMA_EEI_EEI22_MASK (0x400000U)
#define	DMA_EEI_EEI22_SHIFT (22U)
#define	DMA_EEI_EEI22(x)
#define	DMA_EEI_EEI23_MASK (0x800000U)
#define	DMA_EEI_EEI23_SHIFT (23U)
#define	DMA_EEI_EEI23(x)
#define	DMA_EEI_EEI24_MASK (0x1000000U)
#define	DMA_EEI_EEI24_SHIFT (24U)
#define	DMA_EEI_EEI24(x)
#define	DMA_EEI_EEI25_MASK (0x2000000U)
#define	DMA_EEI_EEI25_SHIFT (25U)
#define	DMA_EEI_EEI25(x)
#define	DMA_EEI_EEI26_MASK (0x4000000U)
#define	DMA_EEI_EEI26_SHIFT (26U)
#define	DMA_EEI_EEI26(x)
#define	DMA_EEI_EEI27_MASK (0x8000000U)
#define	DMA_EEI_EEI27_SHIFT (27U)
#define	DMA_EEI_EEI27(x)
#define	DMA_EEI_EEI28_MASK (0x10000000U)
#define	DMA_EEI_EEI28_SHIFT (28U)
#define	DMA_EEI_EEI28(x)
#define	DMA_EEI_EEI29_MASK (0x20000000U)
#define	DMA_EEI_EEI29_SHIFT (29U)
#define	DMA_EEI_EEI29(x)
#define	DMA_EEI_EEI30_MASK (0x40000000U)
#define	DMA_EEI_EEI30_SHIFT (30U)
#define	DMA_EEI_EEI30(x)
#define	DMA_EEI_EEI31_MASK (0x80000000U)
#define	DMA_EEI_EEI31_SHIFT (31U)
#define	DMA_EEI_EEI31(x)
#define	DMA_EEI_EEI0_MASK (0x1U)
#define	DMA_EEI_EEI0_SHIFT (0U)
#define	DMA_EEI_EEI0(x)
#define	DMA_EEI_EEI1_MASK (0x2U)
#define	DMA_EEI_EEI1_SHIFT (1U)
#define	DMA_EEI_EEI1(x)
#define	DMA_EEI_EEI2_MASK (0x4U)
#define	DMA_EEI_EEI2_SHIFT (2U)
#define	DMA_EEI_EEI2(x)
#define	DMA_EEI_EEI3_MASK (0x8U)
#define	DMA_EEI_EEI3_SHIFT (3U)
#define	DMA_EEI_EEI3(x)
#define	DMA_EEI_EEI4_MASK (0x10U)
#define	DMA_EEI_EEI4_SHIFT (4U)
#define	DMA_EEI_EEI4(x)
#define	DMA_EEI_EEI5_MASK (0x20U)
#define	DMA_EEI_EEI5_SHIFT (5U)
#define	DMA_EEI_EEI5(x)
#define	DMA_EEI_EEI6_MASK (0x40U)
#define	DMA_EEI_EEI6_SHIFT (6U)
#define	DMA_EEI_EEI6(x)
#define	DMA_EEI_EEI7_MASK (0x80U)
#define	DMA_EEI_EEI7_SHIFT (7U)
#define	DMA_EEI_EEI7(x)
#define	DMA_EEI_EEI8_MASK (0x100U)
#define	DMA_EEI_EEI8_SHIFT (8U)
#define	DMA_EEI_EEI8(x)
#define	DMA_EEI_EEI9_MASK (0x200U)
#define	DMA_EEI_EEI9_SHIFT (9U)
#define	DMA_EEI_EEI9(x)
#define	DMA_EEI_EEI10_MASK (0x400U)
#define	DMA_EEI_EEI10_SHIFT (10U)
#define	DMA_EEI_EEI10(x)
#define	DMA_EEI_EEI11_MASK (0x800U)
#define	DMA_EEI_EEI11_SHIFT (11U)
#define	DMA_EEI_EEI11(x)
#define	DMA_EEI_EEI12_MASK (0x1000U)
#define	DMA_EEI_EEI12_SHIFT (12U)
#define	DMA_EEI_EEI12(x)
#define	DMA_EEI_EEI13_MASK (0x2000U)
#define	DMA_EEI_EEI13_SHIFT (13U)
#define	DMA_EEI_EEI13(x)
#define	DMA_EEI_EEI14_MASK (0x4000U)
#define	DMA_EEI_EEI14_SHIFT (14U)
#define	DMA_EEI_EEI14(x)
#define	DMA_EEI_EEI15_MASK (0x8000U)
#define	DMA_EEI_EEI15_SHIFT (15U)
#define	DMA_EEI_EEI15(x)
#define	DMA_EEI_EEI16_MASK (0x10000U)
#define	DMA_EEI_EEI16_SHIFT (16U)
#define	DMA_EEI_EEI16(x)
#define	DMA_EEI_EEI17_MASK (0x20000U)
#define	DMA_EEI_EEI17_SHIFT (17U)
#define	DMA_EEI_EEI17(x)
#define	DMA_EEI_EEI18_MASK (0x40000U)
#define	DMA_EEI_EEI18_SHIFT (18U)
#define	DMA_EEI_EEI18(x)
#define	DMA_EEI_EEI19_MASK (0x80000U)
#define	DMA_EEI_EEI19_SHIFT (19U)
#define	DMA_EEI_EEI19(x)
#define	DMA_EEI_EEI20_MASK (0x100000U)
#define	DMA_EEI_EEI20_SHIFT (20U)
#define	DMA_EEI_EEI20(x)
#define	DMA_EEI_EEI21_MASK (0x200000U)
#define	DMA_EEI_EEI21_SHIFT (21U)
#define	DMA_EEI_EEI21(x)
#define	DMA_EEI_EEI22_MASK (0x400000U)
#define	DMA_EEI_EEI22_SHIFT (22U)
#define	DMA_EEI_EEI22(x)
#define	DMA_EEI_EEI23_MASK (0x800000U)
#define	DMA_EEI_EEI23_SHIFT (23U)
#define	DMA_EEI_EEI23(x)
#define	DMA_EEI_EEI24_MASK (0x1000000U)
#define	DMA_EEI_EEI24_SHIFT (24U)
#define	DMA_EEI_EEI24(x)
#define	DMA_EEI_EEI25_MASK (0x2000000U)
#define	DMA_EEI_EEI25_SHIFT (25U)
#define	DMA_EEI_EEI25(x)
#define	DMA_EEI_EEI26_MASK (0x4000000U)
#define	DMA_EEI_EEI26_SHIFT (26U)
#define	DMA_EEI_EEI26(x)
#define	DMA_EEI_EEI27_MASK (0x8000000U)
#define	DMA_EEI_EEI27_SHIFT (27U)
#define	DMA_EEI_EEI27(x)
#define	DMA_EEI_EEI28_MASK (0x10000000U)
#define	DMA_EEI_EEI28_SHIFT (28U)
#define	DMA_EEI_EEI28(x)
#define	DMA_EEI_EEI29_MASK (0x20000000U)
#define	DMA_EEI_EEI29_SHIFT (29U)
#define	DMA_EEI_EEI29(x)
#define	DMA_EEI_EEI30_MASK (0x40000000U)
#define	DMA_EEI_EEI30_SHIFT (30U)
#define	DMA_EEI_EEI30(x)
#define	DMA_EEI_EEI31_MASK (0x80000000U)
#define	DMA_EEI_EEI31_SHIFT (31U)
#define	DMA_EEI_EEI31(x)

CEEI - Clear Enable Error Interrupt
#define	DMA_CEEI_CEEI_MASK (0x1FU)
#define	DMA_CEEI_CEEI_SHIFT (0U)
#define	DMA_CEEI_CEEI(x)
#define	DMA_CEEI_CAEE_MASK (0x40U)
#define	DMA_CEEI_CAEE_SHIFT (6U)
#define	DMA_CEEI_CAEE(x)
#define	DMA_CEEI_NOP_MASK (0x80U)
#define	DMA_CEEI_NOP_SHIFT (7U)
#define	DMA_CEEI_NOP(x)
#define	DMA_CEEI_CEEI_MASK (0x1FU)
#define	DMA_CEEI_CEEI_SHIFT (0U)
#define	DMA_CEEI_CEEI(x)
#define	DMA_CEEI_CAEE_MASK (0x40U)
#define	DMA_CEEI_CAEE_SHIFT (6U)
#define	DMA_CEEI_CAEE(x)
#define	DMA_CEEI_NOP_MASK (0x80U)
#define	DMA_CEEI_NOP_SHIFT (7U)
#define	DMA_CEEI_NOP(x)
#define	DMA_CEEI_CEEI_MASK (0x1FU)
#define	DMA_CEEI_CEEI_SHIFT (0U)
#define	DMA_CEEI_CEEI(x)
#define	DMA_CEEI_CAEE_MASK (0x40U)
#define	DMA_CEEI_CAEE_SHIFT (6U)
#define	DMA_CEEI_CAEE(x)
#define	DMA_CEEI_NOP_MASK (0x80U)
#define	DMA_CEEI_NOP_SHIFT (7U)
#define	DMA_CEEI_NOP(x)

SEEI - Set Enable Error Interrupt
#define	DMA_SEEI_SEEI_MASK (0x1FU)
#define	DMA_SEEI_SEEI_SHIFT (0U)
#define	DMA_SEEI_SEEI(x)
#define	DMA_SEEI_SAEE_MASK (0x40U)
#define	DMA_SEEI_SAEE_SHIFT (6U)
#define	DMA_SEEI_SAEE(x)
#define	DMA_SEEI_NOP_MASK (0x80U)
#define	DMA_SEEI_NOP_SHIFT (7U)
#define	DMA_SEEI_NOP(x)
#define	DMA_SEEI_SEEI_MASK (0x1FU)
#define	DMA_SEEI_SEEI_SHIFT (0U)
#define	DMA_SEEI_SEEI(x)
#define	DMA_SEEI_SAEE_MASK (0x40U)
#define	DMA_SEEI_SAEE_SHIFT (6U)
#define	DMA_SEEI_SAEE(x)
#define	DMA_SEEI_NOP_MASK (0x80U)
#define	DMA_SEEI_NOP_SHIFT (7U)
#define	DMA_SEEI_NOP(x)
#define	DMA_SEEI_SEEI_MASK (0x1FU)
#define	DMA_SEEI_SEEI_SHIFT (0U)
#define	DMA_SEEI_SEEI(x)
#define	DMA_SEEI_SAEE_MASK (0x40U)
#define	DMA_SEEI_SAEE_SHIFT (6U)
#define	DMA_SEEI_SAEE(x)
#define	DMA_SEEI_NOP_MASK (0x80U)
#define	DMA_SEEI_NOP_SHIFT (7U)
#define	DMA_SEEI_NOP(x)

CERQ - Clear Enable Request
#define	DMA_CERQ_CERQ_MASK (0x1FU)
#define	DMA_CERQ_CERQ_SHIFT (0U)
#define	DMA_CERQ_CERQ(x)
#define	DMA_CERQ_CAER_MASK (0x40U)
#define	DMA_CERQ_CAER_SHIFT (6U)
#define	DMA_CERQ_CAER(x)
#define	DMA_CERQ_NOP_MASK (0x80U)
#define	DMA_CERQ_NOP_SHIFT (7U)
#define	DMA_CERQ_NOP(x)
#define	DMA_CERQ_CERQ_MASK (0x1FU)
#define	DMA_CERQ_CERQ_SHIFT (0U)
#define	DMA_CERQ_CERQ(x)
#define	DMA_CERQ_CAER_MASK (0x40U)
#define	DMA_CERQ_CAER_SHIFT (6U)
#define	DMA_CERQ_CAER(x)
#define	DMA_CERQ_NOP_MASK (0x80U)
#define	DMA_CERQ_NOP_SHIFT (7U)
#define	DMA_CERQ_NOP(x)
#define	DMA_CERQ_CERQ_MASK (0x1FU)
#define	DMA_CERQ_CERQ_SHIFT (0U)
#define	DMA_CERQ_CERQ(x)
#define	DMA_CERQ_CAER_MASK (0x40U)
#define	DMA_CERQ_CAER_SHIFT (6U)
#define	DMA_CERQ_CAER(x)
#define	DMA_CERQ_NOP_MASK (0x80U)
#define	DMA_CERQ_NOP_SHIFT (7U)
#define	DMA_CERQ_NOP(x)

SERQ - Set Enable Request
#define	DMA_SERQ_SERQ_MASK (0x1FU)
#define	DMA_SERQ_SERQ_SHIFT (0U)
#define	DMA_SERQ_SERQ(x)
#define	DMA_SERQ_SAER_MASK (0x40U)
#define	DMA_SERQ_SAER_SHIFT (6U)
#define	DMA_SERQ_SAER(x)
#define	DMA_SERQ_NOP_MASK (0x80U)
#define	DMA_SERQ_NOP_SHIFT (7U)
#define	DMA_SERQ_NOP(x)
#define	DMA_SERQ_SERQ_MASK (0x1FU)
#define	DMA_SERQ_SERQ_SHIFT (0U)
#define	DMA_SERQ_SERQ(x)
#define	DMA_SERQ_SAER_MASK (0x40U)
#define	DMA_SERQ_SAER_SHIFT (6U)
#define	DMA_SERQ_SAER(x)
#define	DMA_SERQ_NOP_MASK (0x80U)
#define	DMA_SERQ_NOP_SHIFT (7U)
#define	DMA_SERQ_NOP(x)
#define	DMA_SERQ_SERQ_MASK (0x1FU)
#define	DMA_SERQ_SERQ_SHIFT (0U)
#define	DMA_SERQ_SERQ(x)
#define	DMA_SERQ_SAER_MASK (0x40U)
#define	DMA_SERQ_SAER_SHIFT (6U)
#define	DMA_SERQ_SAER(x)
#define	DMA_SERQ_NOP_MASK (0x80U)
#define	DMA_SERQ_NOP_SHIFT (7U)
#define	DMA_SERQ_NOP(x)

CDNE - Clear DONE Status Bit
#define	DMA_CDNE_CDNE_MASK (0x1FU)
#define	DMA_CDNE_CDNE_SHIFT (0U)
#define	DMA_CDNE_CDNE(x)
#define	DMA_CDNE_CADN_MASK (0x40U)
#define	DMA_CDNE_CADN_SHIFT (6U)
#define	DMA_CDNE_CADN(x)
#define	DMA_CDNE_NOP_MASK (0x80U)
#define	DMA_CDNE_NOP_SHIFT (7U)
#define	DMA_CDNE_NOP(x)
#define	DMA_CDNE_CDNE_MASK (0x1FU)
#define	DMA_CDNE_CDNE_SHIFT (0U)
#define	DMA_CDNE_CDNE(x)
#define	DMA_CDNE_CADN_MASK (0x40U)
#define	DMA_CDNE_CADN_SHIFT (6U)
#define	DMA_CDNE_CADN(x)
#define	DMA_CDNE_NOP_MASK (0x80U)
#define	DMA_CDNE_NOP_SHIFT (7U)
#define	DMA_CDNE_NOP(x)
#define	DMA_CDNE_CDNE_MASK (0x1FU)
#define	DMA_CDNE_CDNE_SHIFT (0U)
#define	DMA_CDNE_CDNE(x)
#define	DMA_CDNE_CADN_MASK (0x40U)
#define	DMA_CDNE_CADN_SHIFT (6U)
#define	DMA_CDNE_CADN(x)
#define	DMA_CDNE_NOP_MASK (0x80U)
#define	DMA_CDNE_NOP_SHIFT (7U)
#define	DMA_CDNE_NOP(x)

SSRT - Set START Bit
#define	DMA_SSRT_SSRT_MASK (0x1FU)
#define	DMA_SSRT_SSRT_SHIFT (0U)
#define	DMA_SSRT_SSRT(x)
#define	DMA_SSRT_SAST_MASK (0x40U)
#define	DMA_SSRT_SAST_SHIFT (6U)
#define	DMA_SSRT_SAST(x)
#define	DMA_SSRT_NOP_MASK (0x80U)
#define	DMA_SSRT_NOP_SHIFT (7U)
#define	DMA_SSRT_NOP(x)
#define	DMA_SSRT_SSRT_MASK (0x1FU)
#define	DMA_SSRT_SSRT_SHIFT (0U)
#define	DMA_SSRT_SSRT(x)
#define	DMA_SSRT_SAST_MASK (0x40U)
#define	DMA_SSRT_SAST_SHIFT (6U)
#define	DMA_SSRT_SAST(x)
#define	DMA_SSRT_NOP_MASK (0x80U)
#define	DMA_SSRT_NOP_SHIFT (7U)
#define	DMA_SSRT_NOP(x)
#define	DMA_SSRT_SSRT_MASK (0x1FU)
#define	DMA_SSRT_SSRT_SHIFT (0U)
#define	DMA_SSRT_SSRT(x)
#define	DMA_SSRT_SAST_MASK (0x40U)
#define	DMA_SSRT_SAST_SHIFT (6U)
#define	DMA_SSRT_SAST(x)
#define	DMA_SSRT_NOP_MASK (0x80U)
#define	DMA_SSRT_NOP_SHIFT (7U)
#define	DMA_SSRT_NOP(x)

CERR - Clear Error
#define	DMA_CERR_CERR_MASK (0x1FU)
#define	DMA_CERR_CERR_SHIFT (0U)
#define	DMA_CERR_CERR(x)
#define	DMA_CERR_CAEI_MASK (0x40U)
#define	DMA_CERR_CAEI_SHIFT (6U)
#define	DMA_CERR_CAEI(x)
#define	DMA_CERR_NOP_MASK (0x80U)
#define	DMA_CERR_NOP_SHIFT (7U)
#define	DMA_CERR_NOP(x)
#define	DMA_CERR_CERR_MASK (0x1FU)
#define	DMA_CERR_CERR_SHIFT (0U)
#define	DMA_CERR_CERR(x)
#define	DMA_CERR_CAEI_MASK (0x40U)
#define	DMA_CERR_CAEI_SHIFT (6U)
#define	DMA_CERR_CAEI(x)
#define	DMA_CERR_NOP_MASK (0x80U)
#define	DMA_CERR_NOP_SHIFT (7U)
#define	DMA_CERR_NOP(x)
#define	DMA_CERR_CERR_MASK (0x1FU)
#define	DMA_CERR_CERR_SHIFT (0U)
#define	DMA_CERR_CERR(x)
#define	DMA_CERR_CAEI_MASK (0x40U)
#define	DMA_CERR_CAEI_SHIFT (6U)
#define	DMA_CERR_CAEI(x)
#define	DMA_CERR_NOP_MASK (0x80U)
#define	DMA_CERR_NOP_SHIFT (7U)
#define	DMA_CERR_NOP(x)

CINT - Clear Interrupt Request
#define	DMA_CINT_CINT_MASK (0x1FU)
#define	DMA_CINT_CINT_SHIFT (0U)
#define	DMA_CINT_CINT(x)
#define	DMA_CINT_CAIR_MASK (0x40U)
#define	DMA_CINT_CAIR_SHIFT (6U)
#define	DMA_CINT_CAIR(x)
#define	DMA_CINT_NOP_MASK (0x80U)
#define	DMA_CINT_NOP_SHIFT (7U)
#define	DMA_CINT_NOP(x)
#define	DMA_CINT_CINT_MASK (0x1FU)
#define	DMA_CINT_CINT_SHIFT (0U)
#define	DMA_CINT_CINT(x)
#define	DMA_CINT_CAIR_MASK (0x40U)
#define	DMA_CINT_CAIR_SHIFT (6U)
#define	DMA_CINT_CAIR(x)
#define	DMA_CINT_NOP_MASK (0x80U)
#define	DMA_CINT_NOP_SHIFT (7U)
#define	DMA_CINT_NOP(x)
#define	DMA_CINT_CINT_MASK (0x1FU)
#define	DMA_CINT_CINT_SHIFT (0U)
#define	DMA_CINT_CINT(x)
#define	DMA_CINT_CAIR_MASK (0x40U)
#define	DMA_CINT_CAIR_SHIFT (6U)
#define	DMA_CINT_CAIR(x)
#define	DMA_CINT_NOP_MASK (0x80U)
#define	DMA_CINT_NOP_SHIFT (7U)
#define	DMA_CINT_NOP(x)

INT - Interrupt Request
#define	DMA_INT_INT0_MASK (0x1U)
#define	DMA_INT_INT0_SHIFT (0U)
#define	DMA_INT_INT0(x)
#define	DMA_INT_INT1_MASK (0x2U)
#define	DMA_INT_INT1_SHIFT (1U)
#define	DMA_INT_INT1(x)
#define	DMA_INT_INT2_MASK (0x4U)
#define	DMA_INT_INT2_SHIFT (2U)
#define	DMA_INT_INT2(x)
#define	DMA_INT_INT3_MASK (0x8U)
#define	DMA_INT_INT3_SHIFT (3U)
#define	DMA_INT_INT3(x)
#define	DMA_INT_INT4_MASK (0x10U)
#define	DMA_INT_INT4_SHIFT (4U)
#define	DMA_INT_INT4(x)
#define	DMA_INT_INT5_MASK (0x20U)
#define	DMA_INT_INT5_SHIFT (5U)
#define	DMA_INT_INT5(x)
#define	DMA_INT_INT6_MASK (0x40U)
#define	DMA_INT_INT6_SHIFT (6U)
#define	DMA_INT_INT6(x)
#define	DMA_INT_INT7_MASK (0x80U)
#define	DMA_INT_INT7_SHIFT (7U)
#define	DMA_INT_INT7(x)
#define	DMA_INT_INT8_MASK (0x100U)
#define	DMA_INT_INT8_SHIFT (8U)
#define	DMA_INT_INT8(x)
#define	DMA_INT_INT9_MASK (0x200U)
#define	DMA_INT_INT9_SHIFT (9U)
#define	DMA_INT_INT9(x)
#define	DMA_INT_INT10_MASK (0x400U)
#define	DMA_INT_INT10_SHIFT (10U)
#define	DMA_INT_INT10(x)
#define	DMA_INT_INT11_MASK (0x800U)
#define	DMA_INT_INT11_SHIFT (11U)
#define	DMA_INT_INT11(x)
#define	DMA_INT_INT12_MASK (0x1000U)
#define	DMA_INT_INT12_SHIFT (12U)
#define	DMA_INT_INT12(x)
#define	DMA_INT_INT13_MASK (0x2000U)
#define	DMA_INT_INT13_SHIFT (13U)
#define	DMA_INT_INT13(x)
#define	DMA_INT_INT14_MASK (0x4000U)
#define	DMA_INT_INT14_SHIFT (14U)
#define	DMA_INT_INT14(x)
#define	DMA_INT_INT15_MASK (0x8000U)
#define	DMA_INT_INT15_SHIFT (15U)
#define	DMA_INT_INT15(x)
#define	DMA_INT_INT16_MASK (0x10000U)
#define	DMA_INT_INT16_SHIFT (16U)
#define	DMA_INT_INT16(x)
#define	DMA_INT_INT17_MASK (0x20000U)
#define	DMA_INT_INT17_SHIFT (17U)
#define	DMA_INT_INT17(x)
#define	DMA_INT_INT18_MASK (0x40000U)
#define	DMA_INT_INT18_SHIFT (18U)
#define	DMA_INT_INT18(x)
#define	DMA_INT_INT19_MASK (0x80000U)
#define	DMA_INT_INT19_SHIFT (19U)
#define	DMA_INT_INT19(x)
#define	DMA_INT_INT20_MASK (0x100000U)
#define	DMA_INT_INT20_SHIFT (20U)
#define	DMA_INT_INT20(x)
#define	DMA_INT_INT21_MASK (0x200000U)
#define	DMA_INT_INT21_SHIFT (21U)
#define	DMA_INT_INT21(x)
#define	DMA_INT_INT22_MASK (0x400000U)
#define	DMA_INT_INT22_SHIFT (22U)
#define	DMA_INT_INT22(x)
#define	DMA_INT_INT23_MASK (0x800000U)
#define	DMA_INT_INT23_SHIFT (23U)
#define	DMA_INT_INT23(x)
#define	DMA_INT_INT24_MASK (0x1000000U)
#define	DMA_INT_INT24_SHIFT (24U)
#define	DMA_INT_INT24(x)
#define	DMA_INT_INT25_MASK (0x2000000U)
#define	DMA_INT_INT25_SHIFT (25U)
#define	DMA_INT_INT25(x)
#define	DMA_INT_INT26_MASK (0x4000000U)
#define	DMA_INT_INT26_SHIFT (26U)
#define	DMA_INT_INT26(x)
#define	DMA_INT_INT27_MASK (0x8000000U)
#define	DMA_INT_INT27_SHIFT (27U)
#define	DMA_INT_INT27(x)
#define	DMA_INT_INT28_MASK (0x10000000U)
#define	DMA_INT_INT28_SHIFT (28U)
#define	DMA_INT_INT28(x)
#define	DMA_INT_INT29_MASK (0x20000000U)
#define	DMA_INT_INT29_SHIFT (29U)
#define	DMA_INT_INT29(x)
#define	DMA_INT_INT30_MASK (0x40000000U)
#define	DMA_INT_INT30_SHIFT (30U)
#define	DMA_INT_INT30(x)
#define	DMA_INT_INT31_MASK (0x80000000U)
#define	DMA_INT_INT31_SHIFT (31U)
#define	DMA_INT_INT31(x)
#define	DMA_INT_INT0_MASK (0x1U)
#define	DMA_INT_INT0_SHIFT (0U)
#define	DMA_INT_INT0(x)
#define	DMA_INT_INT1_MASK (0x2U)
#define	DMA_INT_INT1_SHIFT (1U)
#define	DMA_INT_INT1(x)
#define	DMA_INT_INT2_MASK (0x4U)
#define	DMA_INT_INT2_SHIFT (2U)
#define	DMA_INT_INT2(x)
#define	DMA_INT_INT3_MASK (0x8U)
#define	DMA_INT_INT3_SHIFT (3U)
#define	DMA_INT_INT3(x)
#define	DMA_INT_INT4_MASK (0x10U)
#define	DMA_INT_INT4_SHIFT (4U)
#define	DMA_INT_INT4(x)
#define	DMA_INT_INT5_MASK (0x20U)
#define	DMA_INT_INT5_SHIFT (5U)
#define	DMA_INT_INT5(x)
#define	DMA_INT_INT6_MASK (0x40U)
#define	DMA_INT_INT6_SHIFT (6U)
#define	DMA_INT_INT6(x)
#define	DMA_INT_INT7_MASK (0x80U)
#define	DMA_INT_INT7_SHIFT (7U)
#define	DMA_INT_INT7(x)
#define	DMA_INT_INT8_MASK (0x100U)
#define	DMA_INT_INT8_SHIFT (8U)
#define	DMA_INT_INT8(x)
#define	DMA_INT_INT9_MASK (0x200U)
#define	DMA_INT_INT9_SHIFT (9U)
#define	DMA_INT_INT9(x)
#define	DMA_INT_INT10_MASK (0x400U)
#define	DMA_INT_INT10_SHIFT (10U)
#define	DMA_INT_INT10(x)
#define	DMA_INT_INT11_MASK (0x800U)
#define	DMA_INT_INT11_SHIFT (11U)
#define	DMA_INT_INT11(x)
#define	DMA_INT_INT12_MASK (0x1000U)
#define	DMA_INT_INT12_SHIFT (12U)
#define	DMA_INT_INT12(x)
#define	DMA_INT_INT13_MASK (0x2000U)
#define	DMA_INT_INT13_SHIFT (13U)
#define	DMA_INT_INT13(x)
#define	DMA_INT_INT14_MASK (0x4000U)
#define	DMA_INT_INT14_SHIFT (14U)
#define	DMA_INT_INT14(x)
#define	DMA_INT_INT15_MASK (0x8000U)
#define	DMA_INT_INT15_SHIFT (15U)
#define	DMA_INT_INT15(x)
#define	DMA_INT_INT16_MASK (0x10000U)
#define	DMA_INT_INT16_SHIFT (16U)
#define	DMA_INT_INT16(x)
#define	DMA_INT_INT17_MASK (0x20000U)
#define	DMA_INT_INT17_SHIFT (17U)
#define	DMA_INT_INT17(x)
#define	DMA_INT_INT18_MASK (0x40000U)
#define	DMA_INT_INT18_SHIFT (18U)
#define	DMA_INT_INT18(x)
#define	DMA_INT_INT19_MASK (0x80000U)
#define	DMA_INT_INT19_SHIFT (19U)
#define	DMA_INT_INT19(x)
#define	DMA_INT_INT20_MASK (0x100000U)
#define	DMA_INT_INT20_SHIFT (20U)
#define	DMA_INT_INT20(x)
#define	DMA_INT_INT21_MASK (0x200000U)
#define	DMA_INT_INT21_SHIFT (21U)
#define	DMA_INT_INT21(x)
#define	DMA_INT_INT22_MASK (0x400000U)
#define	DMA_INT_INT22_SHIFT (22U)
#define	DMA_INT_INT22(x)
#define	DMA_INT_INT23_MASK (0x800000U)
#define	DMA_INT_INT23_SHIFT (23U)
#define	DMA_INT_INT23(x)
#define	DMA_INT_INT24_MASK (0x1000000U)
#define	DMA_INT_INT24_SHIFT (24U)
#define	DMA_INT_INT24(x)
#define	DMA_INT_INT25_MASK (0x2000000U)
#define	DMA_INT_INT25_SHIFT (25U)
#define	DMA_INT_INT25(x)
#define	DMA_INT_INT26_MASK (0x4000000U)
#define	DMA_INT_INT26_SHIFT (26U)
#define	DMA_INT_INT26(x)
#define	DMA_INT_INT27_MASK (0x8000000U)
#define	DMA_INT_INT27_SHIFT (27U)
#define	DMA_INT_INT27(x)
#define	DMA_INT_INT28_MASK (0x10000000U)
#define	DMA_INT_INT28_SHIFT (28U)
#define	DMA_INT_INT28(x)
#define	DMA_INT_INT29_MASK (0x20000000U)
#define	DMA_INT_INT29_SHIFT (29U)
#define	DMA_INT_INT29(x)
#define	DMA_INT_INT30_MASK (0x40000000U)
#define	DMA_INT_INT30_SHIFT (30U)
#define	DMA_INT_INT30(x)
#define	DMA_INT_INT31_MASK (0x80000000U)
#define	DMA_INT_INT31_SHIFT (31U)
#define	DMA_INT_INT31(x)
#define	DMA_INT_INT0_MASK (0x1U)
#define	DMA_INT_INT0_SHIFT (0U)
#define	DMA_INT_INT0(x)
#define	DMA_INT_INT1_MASK (0x2U)
#define	DMA_INT_INT1_SHIFT (1U)
#define	DMA_INT_INT1(x)
#define	DMA_INT_INT2_MASK (0x4U)
#define	DMA_INT_INT2_SHIFT (2U)
#define	DMA_INT_INT2(x)
#define	DMA_INT_INT3_MASK (0x8U)
#define	DMA_INT_INT3_SHIFT (3U)
#define	DMA_INT_INT3(x)
#define	DMA_INT_INT4_MASK (0x10U)
#define	DMA_INT_INT4_SHIFT (4U)
#define	DMA_INT_INT4(x)
#define	DMA_INT_INT5_MASK (0x20U)
#define	DMA_INT_INT5_SHIFT (5U)
#define	DMA_INT_INT5(x)
#define	DMA_INT_INT6_MASK (0x40U)
#define	DMA_INT_INT6_SHIFT (6U)
#define	DMA_INT_INT6(x)
#define	DMA_INT_INT7_MASK (0x80U)
#define	DMA_INT_INT7_SHIFT (7U)
#define	DMA_INT_INT7(x)
#define	DMA_INT_INT8_MASK (0x100U)
#define	DMA_INT_INT8_SHIFT (8U)
#define	DMA_INT_INT8(x)
#define	DMA_INT_INT9_MASK (0x200U)
#define	DMA_INT_INT9_SHIFT (9U)
#define	DMA_INT_INT9(x)
#define	DMA_INT_INT10_MASK (0x400U)
#define	DMA_INT_INT10_SHIFT (10U)
#define	DMA_INT_INT10(x)
#define	DMA_INT_INT11_MASK (0x800U)
#define	DMA_INT_INT11_SHIFT (11U)
#define	DMA_INT_INT11(x)
#define	DMA_INT_INT12_MASK (0x1000U)
#define	DMA_INT_INT12_SHIFT (12U)
#define	DMA_INT_INT12(x)
#define	DMA_INT_INT13_MASK (0x2000U)
#define	DMA_INT_INT13_SHIFT (13U)
#define	DMA_INT_INT13(x)
#define	DMA_INT_INT14_MASK (0x4000U)
#define	DMA_INT_INT14_SHIFT (14U)
#define	DMA_INT_INT14(x)
#define	DMA_INT_INT15_MASK (0x8000U)
#define	DMA_INT_INT15_SHIFT (15U)
#define	DMA_INT_INT15(x)
#define	DMA_INT_INT16_MASK (0x10000U)
#define	DMA_INT_INT16_SHIFT (16U)
#define	DMA_INT_INT16(x)
#define	DMA_INT_INT17_MASK (0x20000U)
#define	DMA_INT_INT17_SHIFT (17U)
#define	DMA_INT_INT17(x)
#define	DMA_INT_INT18_MASK (0x40000U)
#define	DMA_INT_INT18_SHIFT (18U)
#define	DMA_INT_INT18(x)
#define	DMA_INT_INT19_MASK (0x80000U)
#define	DMA_INT_INT19_SHIFT (19U)
#define	DMA_INT_INT19(x)
#define	DMA_INT_INT20_MASK (0x100000U)
#define	DMA_INT_INT20_SHIFT (20U)
#define	DMA_INT_INT20(x)
#define	DMA_INT_INT21_MASK (0x200000U)
#define	DMA_INT_INT21_SHIFT (21U)
#define	DMA_INT_INT21(x)
#define	DMA_INT_INT22_MASK (0x400000U)
#define	DMA_INT_INT22_SHIFT (22U)
#define	DMA_INT_INT22(x)
#define	DMA_INT_INT23_MASK (0x800000U)
#define	DMA_INT_INT23_SHIFT (23U)
#define	DMA_INT_INT23(x)
#define	DMA_INT_INT24_MASK (0x1000000U)
#define	DMA_INT_INT24_SHIFT (24U)
#define	DMA_INT_INT24(x)
#define	DMA_INT_INT25_MASK (0x2000000U)
#define	DMA_INT_INT25_SHIFT (25U)
#define	DMA_INT_INT25(x)
#define	DMA_INT_INT26_MASK (0x4000000U)
#define	DMA_INT_INT26_SHIFT (26U)
#define	DMA_INT_INT26(x)
#define	DMA_INT_INT27_MASK (0x8000000U)
#define	DMA_INT_INT27_SHIFT (27U)
#define	DMA_INT_INT27(x)
#define	DMA_INT_INT28_MASK (0x10000000U)
#define	DMA_INT_INT28_SHIFT (28U)
#define	DMA_INT_INT28(x)
#define	DMA_INT_INT29_MASK (0x20000000U)
#define	DMA_INT_INT29_SHIFT (29U)
#define	DMA_INT_INT29(x)
#define	DMA_INT_INT30_MASK (0x40000000U)
#define	DMA_INT_INT30_SHIFT (30U)
#define	DMA_INT_INT30(x)
#define	DMA_INT_INT31_MASK (0x80000000U)
#define	DMA_INT_INT31_SHIFT (31U)
#define	DMA_INT_INT31(x)

ERR - Error
#define	DMA_ERR_ERR0_MASK (0x1U)
#define	DMA_ERR_ERR0_SHIFT (0U)
#define	DMA_ERR_ERR0(x)
#define	DMA_ERR_ERR1_MASK (0x2U)
#define	DMA_ERR_ERR1_SHIFT (1U)
#define	DMA_ERR_ERR1(x)
#define	DMA_ERR_ERR2_MASK (0x4U)
#define	DMA_ERR_ERR2_SHIFT (2U)
#define	DMA_ERR_ERR2(x)
#define	DMA_ERR_ERR3_MASK (0x8U)
#define	DMA_ERR_ERR3_SHIFT (3U)
#define	DMA_ERR_ERR3(x)
#define	DMA_ERR_ERR4_MASK (0x10U)
#define	DMA_ERR_ERR4_SHIFT (4U)
#define	DMA_ERR_ERR4(x)
#define	DMA_ERR_ERR5_MASK (0x20U)
#define	DMA_ERR_ERR5_SHIFT (5U)
#define	DMA_ERR_ERR5(x)
#define	DMA_ERR_ERR6_MASK (0x40U)
#define	DMA_ERR_ERR6_SHIFT (6U)
#define	DMA_ERR_ERR6(x)
#define	DMA_ERR_ERR7_MASK (0x80U)
#define	DMA_ERR_ERR7_SHIFT (7U)
#define	DMA_ERR_ERR7(x)
#define	DMA_ERR_ERR8_MASK (0x100U)
#define	DMA_ERR_ERR8_SHIFT (8U)
#define	DMA_ERR_ERR8(x)
#define	DMA_ERR_ERR9_MASK (0x200U)
#define	DMA_ERR_ERR9_SHIFT (9U)
#define	DMA_ERR_ERR9(x)
#define	DMA_ERR_ERR10_MASK (0x400U)
#define	DMA_ERR_ERR10_SHIFT (10U)
#define	DMA_ERR_ERR10(x)
#define	DMA_ERR_ERR11_MASK (0x800U)
#define	DMA_ERR_ERR11_SHIFT (11U)
#define	DMA_ERR_ERR11(x)
#define	DMA_ERR_ERR12_MASK (0x1000U)
#define	DMA_ERR_ERR12_SHIFT (12U)
#define	DMA_ERR_ERR12(x)
#define	DMA_ERR_ERR13_MASK (0x2000U)
#define	DMA_ERR_ERR13_SHIFT (13U)
#define	DMA_ERR_ERR13(x)
#define	DMA_ERR_ERR14_MASK (0x4000U)
#define	DMA_ERR_ERR14_SHIFT (14U)
#define	DMA_ERR_ERR14(x)
#define	DMA_ERR_ERR15_MASK (0x8000U)
#define	DMA_ERR_ERR15_SHIFT (15U)
#define	DMA_ERR_ERR15(x)
#define	DMA_ERR_ERR16_MASK (0x10000U)
#define	DMA_ERR_ERR16_SHIFT (16U)
#define	DMA_ERR_ERR16(x)
#define	DMA_ERR_ERR17_MASK (0x20000U)
#define	DMA_ERR_ERR17_SHIFT (17U)
#define	DMA_ERR_ERR17(x)
#define	DMA_ERR_ERR18_MASK (0x40000U)
#define	DMA_ERR_ERR18_SHIFT (18U)
#define	DMA_ERR_ERR18(x)
#define	DMA_ERR_ERR19_MASK (0x80000U)
#define	DMA_ERR_ERR19_SHIFT (19U)
#define	DMA_ERR_ERR19(x)
#define	DMA_ERR_ERR20_MASK (0x100000U)
#define	DMA_ERR_ERR20_SHIFT (20U)
#define	DMA_ERR_ERR20(x)
#define	DMA_ERR_ERR21_MASK (0x200000U)
#define	DMA_ERR_ERR21_SHIFT (21U)
#define	DMA_ERR_ERR21(x)
#define	DMA_ERR_ERR22_MASK (0x400000U)
#define	DMA_ERR_ERR22_SHIFT (22U)
#define	DMA_ERR_ERR22(x)
#define	DMA_ERR_ERR23_MASK (0x800000U)
#define	DMA_ERR_ERR23_SHIFT (23U)
#define	DMA_ERR_ERR23(x)
#define	DMA_ERR_ERR24_MASK (0x1000000U)
#define	DMA_ERR_ERR24_SHIFT (24U)
#define	DMA_ERR_ERR24(x)
#define	DMA_ERR_ERR25_MASK (0x2000000U)
#define	DMA_ERR_ERR25_SHIFT (25U)
#define	DMA_ERR_ERR25(x)
#define	DMA_ERR_ERR26_MASK (0x4000000U)
#define	DMA_ERR_ERR26_SHIFT (26U)
#define	DMA_ERR_ERR26(x)
#define	DMA_ERR_ERR27_MASK (0x8000000U)
#define	DMA_ERR_ERR27_SHIFT (27U)
#define	DMA_ERR_ERR27(x)
#define	DMA_ERR_ERR28_MASK (0x10000000U)
#define	DMA_ERR_ERR28_SHIFT (28U)
#define	DMA_ERR_ERR28(x)
#define	DMA_ERR_ERR29_MASK (0x20000000U)
#define	DMA_ERR_ERR29_SHIFT (29U)
#define	DMA_ERR_ERR29(x)
#define	DMA_ERR_ERR30_MASK (0x40000000U)
#define	DMA_ERR_ERR30_SHIFT (30U)
#define	DMA_ERR_ERR30(x)
#define	DMA_ERR_ERR31_MASK (0x80000000U)
#define	DMA_ERR_ERR31_SHIFT (31U)
#define	DMA_ERR_ERR31(x)
#define	DMA_ERR_ERR0_MASK (0x1U)
#define	DMA_ERR_ERR0_SHIFT (0U)
#define	DMA_ERR_ERR0(x)
#define	DMA_ERR_ERR1_MASK (0x2U)
#define	DMA_ERR_ERR1_SHIFT (1U)
#define	DMA_ERR_ERR1(x)
#define	DMA_ERR_ERR2_MASK (0x4U)
#define	DMA_ERR_ERR2_SHIFT (2U)
#define	DMA_ERR_ERR2(x)
#define	DMA_ERR_ERR3_MASK (0x8U)
#define	DMA_ERR_ERR3_SHIFT (3U)
#define	DMA_ERR_ERR3(x)
#define	DMA_ERR_ERR4_MASK (0x10U)
#define	DMA_ERR_ERR4_SHIFT (4U)
#define	DMA_ERR_ERR4(x)
#define	DMA_ERR_ERR5_MASK (0x20U)
#define	DMA_ERR_ERR5_SHIFT (5U)
#define	DMA_ERR_ERR5(x)
#define	DMA_ERR_ERR6_MASK (0x40U)
#define	DMA_ERR_ERR6_SHIFT (6U)
#define	DMA_ERR_ERR6(x)
#define	DMA_ERR_ERR7_MASK (0x80U)
#define	DMA_ERR_ERR7_SHIFT (7U)
#define	DMA_ERR_ERR7(x)
#define	DMA_ERR_ERR8_MASK (0x100U)
#define	DMA_ERR_ERR8_SHIFT (8U)
#define	DMA_ERR_ERR8(x)
#define	DMA_ERR_ERR9_MASK (0x200U)
#define	DMA_ERR_ERR9_SHIFT (9U)
#define	DMA_ERR_ERR9(x)
#define	DMA_ERR_ERR10_MASK (0x400U)
#define	DMA_ERR_ERR10_SHIFT (10U)
#define	DMA_ERR_ERR10(x)
#define	DMA_ERR_ERR11_MASK (0x800U)
#define	DMA_ERR_ERR11_SHIFT (11U)
#define	DMA_ERR_ERR11(x)
#define	DMA_ERR_ERR12_MASK (0x1000U)
#define	DMA_ERR_ERR12_SHIFT (12U)
#define	DMA_ERR_ERR12(x)
#define	DMA_ERR_ERR13_MASK (0x2000U)
#define	DMA_ERR_ERR13_SHIFT (13U)
#define	DMA_ERR_ERR13(x)
#define	DMA_ERR_ERR14_MASK (0x4000U)
#define	DMA_ERR_ERR14_SHIFT (14U)
#define	DMA_ERR_ERR14(x)
#define	DMA_ERR_ERR15_MASK (0x8000U)
#define	DMA_ERR_ERR15_SHIFT (15U)
#define	DMA_ERR_ERR15(x)
#define	DMA_ERR_ERR16_MASK (0x10000U)
#define	DMA_ERR_ERR16_SHIFT (16U)
#define	DMA_ERR_ERR16(x)
#define	DMA_ERR_ERR17_MASK (0x20000U)
#define	DMA_ERR_ERR17_SHIFT (17U)
#define	DMA_ERR_ERR17(x)
#define	DMA_ERR_ERR18_MASK (0x40000U)
#define	DMA_ERR_ERR18_SHIFT (18U)
#define	DMA_ERR_ERR18(x)
#define	DMA_ERR_ERR19_MASK (0x80000U)
#define	DMA_ERR_ERR19_SHIFT (19U)
#define	DMA_ERR_ERR19(x)
#define	DMA_ERR_ERR20_MASK (0x100000U)
#define	DMA_ERR_ERR20_SHIFT (20U)
#define	DMA_ERR_ERR20(x)
#define	DMA_ERR_ERR21_MASK (0x200000U)
#define	DMA_ERR_ERR21_SHIFT (21U)
#define	DMA_ERR_ERR21(x)
#define	DMA_ERR_ERR22_MASK (0x400000U)
#define	DMA_ERR_ERR22_SHIFT (22U)
#define	DMA_ERR_ERR22(x)
#define	DMA_ERR_ERR23_MASK (0x800000U)
#define	DMA_ERR_ERR23_SHIFT (23U)
#define	DMA_ERR_ERR23(x)
#define	DMA_ERR_ERR24_MASK (0x1000000U)
#define	DMA_ERR_ERR24_SHIFT (24U)
#define	DMA_ERR_ERR24(x)
#define	DMA_ERR_ERR25_MASK (0x2000000U)
#define	DMA_ERR_ERR25_SHIFT (25U)
#define	DMA_ERR_ERR25(x)
#define	DMA_ERR_ERR26_MASK (0x4000000U)
#define	DMA_ERR_ERR26_SHIFT (26U)
#define	DMA_ERR_ERR26(x)
#define	DMA_ERR_ERR27_MASK (0x8000000U)
#define	DMA_ERR_ERR27_SHIFT (27U)
#define	DMA_ERR_ERR27(x)
#define	DMA_ERR_ERR28_MASK (0x10000000U)
#define	DMA_ERR_ERR28_SHIFT (28U)
#define	DMA_ERR_ERR28(x)
#define	DMA_ERR_ERR29_MASK (0x20000000U)
#define	DMA_ERR_ERR29_SHIFT (29U)
#define	DMA_ERR_ERR29(x)
#define	DMA_ERR_ERR30_MASK (0x40000000U)
#define	DMA_ERR_ERR30_SHIFT (30U)
#define	DMA_ERR_ERR30(x)
#define	DMA_ERR_ERR31_MASK (0x80000000U)
#define	DMA_ERR_ERR31_SHIFT (31U)
#define	DMA_ERR_ERR31(x)
#define	DMA_ERR_ERR0_MASK (0x1U)
#define	DMA_ERR_ERR0_SHIFT (0U)
#define	DMA_ERR_ERR0(x)
#define	DMA_ERR_ERR1_MASK (0x2U)
#define	DMA_ERR_ERR1_SHIFT (1U)
#define	DMA_ERR_ERR1(x)
#define	DMA_ERR_ERR2_MASK (0x4U)
#define	DMA_ERR_ERR2_SHIFT (2U)
#define	DMA_ERR_ERR2(x)
#define	DMA_ERR_ERR3_MASK (0x8U)
#define	DMA_ERR_ERR3_SHIFT (3U)
#define	DMA_ERR_ERR3(x)
#define	DMA_ERR_ERR4_MASK (0x10U)
#define	DMA_ERR_ERR4_SHIFT (4U)
#define	DMA_ERR_ERR4(x)
#define	DMA_ERR_ERR5_MASK (0x20U)
#define	DMA_ERR_ERR5_SHIFT (5U)
#define	DMA_ERR_ERR5(x)
#define	DMA_ERR_ERR6_MASK (0x40U)
#define	DMA_ERR_ERR6_SHIFT (6U)
#define	DMA_ERR_ERR6(x)
#define	DMA_ERR_ERR7_MASK (0x80U)
#define	DMA_ERR_ERR7_SHIFT (7U)
#define	DMA_ERR_ERR7(x)
#define	DMA_ERR_ERR8_MASK (0x100U)
#define	DMA_ERR_ERR8_SHIFT (8U)
#define	DMA_ERR_ERR8(x)
#define	DMA_ERR_ERR9_MASK (0x200U)
#define	DMA_ERR_ERR9_SHIFT (9U)
#define	DMA_ERR_ERR9(x)
#define	DMA_ERR_ERR10_MASK (0x400U)
#define	DMA_ERR_ERR10_SHIFT (10U)
#define	DMA_ERR_ERR10(x)
#define	DMA_ERR_ERR11_MASK (0x800U)
#define	DMA_ERR_ERR11_SHIFT (11U)
#define	DMA_ERR_ERR11(x)
#define	DMA_ERR_ERR12_MASK (0x1000U)
#define	DMA_ERR_ERR12_SHIFT (12U)
#define	DMA_ERR_ERR12(x)
#define	DMA_ERR_ERR13_MASK (0x2000U)
#define	DMA_ERR_ERR13_SHIFT (13U)
#define	DMA_ERR_ERR13(x)
#define	DMA_ERR_ERR14_MASK (0x4000U)
#define	DMA_ERR_ERR14_SHIFT (14U)
#define	DMA_ERR_ERR14(x)
#define	DMA_ERR_ERR15_MASK (0x8000U)
#define	DMA_ERR_ERR15_SHIFT (15U)
#define	DMA_ERR_ERR15(x)
#define	DMA_ERR_ERR16_MASK (0x10000U)
#define	DMA_ERR_ERR16_SHIFT (16U)
#define	DMA_ERR_ERR16(x)
#define	DMA_ERR_ERR17_MASK (0x20000U)
#define	DMA_ERR_ERR17_SHIFT (17U)
#define	DMA_ERR_ERR17(x)
#define	DMA_ERR_ERR18_MASK (0x40000U)
#define	DMA_ERR_ERR18_SHIFT (18U)
#define	DMA_ERR_ERR18(x)
#define	DMA_ERR_ERR19_MASK (0x80000U)
#define	DMA_ERR_ERR19_SHIFT (19U)
#define	DMA_ERR_ERR19(x)
#define	DMA_ERR_ERR20_MASK (0x100000U)
#define	DMA_ERR_ERR20_SHIFT (20U)
#define	DMA_ERR_ERR20(x)
#define	DMA_ERR_ERR21_MASK (0x200000U)
#define	DMA_ERR_ERR21_SHIFT (21U)
#define	DMA_ERR_ERR21(x)
#define	DMA_ERR_ERR22_MASK (0x400000U)
#define	DMA_ERR_ERR22_SHIFT (22U)
#define	DMA_ERR_ERR22(x)
#define	DMA_ERR_ERR23_MASK (0x800000U)
#define	DMA_ERR_ERR23_SHIFT (23U)
#define	DMA_ERR_ERR23(x)
#define	DMA_ERR_ERR24_MASK (0x1000000U)
#define	DMA_ERR_ERR24_SHIFT (24U)
#define	DMA_ERR_ERR24(x)
#define	DMA_ERR_ERR25_MASK (0x2000000U)
#define	DMA_ERR_ERR25_SHIFT (25U)
#define	DMA_ERR_ERR25(x)
#define	DMA_ERR_ERR26_MASK (0x4000000U)
#define	DMA_ERR_ERR26_SHIFT (26U)
#define	DMA_ERR_ERR26(x)
#define	DMA_ERR_ERR27_MASK (0x8000000U)
#define	DMA_ERR_ERR27_SHIFT (27U)
#define	DMA_ERR_ERR27(x)
#define	DMA_ERR_ERR28_MASK (0x10000000U)
#define	DMA_ERR_ERR28_SHIFT (28U)
#define	DMA_ERR_ERR28(x)
#define	DMA_ERR_ERR29_MASK (0x20000000U)
#define	DMA_ERR_ERR29_SHIFT (29U)
#define	DMA_ERR_ERR29(x)
#define	DMA_ERR_ERR30_MASK (0x40000000U)
#define	DMA_ERR_ERR30_SHIFT (30U)
#define	DMA_ERR_ERR30(x)
#define	DMA_ERR_ERR31_MASK (0x80000000U)
#define	DMA_ERR_ERR31_SHIFT (31U)
#define	DMA_ERR_ERR31(x)

HRS - Hardware Request Status
#define	DMA_HRS_HRS0_MASK (0x1U)
#define	DMA_HRS_HRS0_SHIFT (0U)
#define	DMA_HRS_HRS0(x)
#define	DMA_HRS_HRS1_MASK (0x2U)
#define	DMA_HRS_HRS1_SHIFT (1U)
#define	DMA_HRS_HRS1(x)
#define	DMA_HRS_HRS2_MASK (0x4U)
#define	DMA_HRS_HRS2_SHIFT (2U)
#define	DMA_HRS_HRS2(x)
#define	DMA_HRS_HRS3_MASK (0x8U)
#define	DMA_HRS_HRS3_SHIFT (3U)
#define	DMA_HRS_HRS3(x)
#define	DMA_HRS_HRS4_MASK (0x10U)
#define	DMA_HRS_HRS4_SHIFT (4U)
#define	DMA_HRS_HRS4(x)
#define	DMA_HRS_HRS5_MASK (0x20U)
#define	DMA_HRS_HRS5_SHIFT (5U)
#define	DMA_HRS_HRS5(x)
#define	DMA_HRS_HRS6_MASK (0x40U)
#define	DMA_HRS_HRS6_SHIFT (6U)
#define	DMA_HRS_HRS6(x)
#define	DMA_HRS_HRS7_MASK (0x80U)
#define	DMA_HRS_HRS7_SHIFT (7U)
#define	DMA_HRS_HRS7(x)
#define	DMA_HRS_HRS8_MASK (0x100U)
#define	DMA_HRS_HRS8_SHIFT (8U)
#define	DMA_HRS_HRS8(x)
#define	DMA_HRS_HRS9_MASK (0x200U)
#define	DMA_HRS_HRS9_SHIFT (9U)
#define	DMA_HRS_HRS9(x)
#define	DMA_HRS_HRS10_MASK (0x400U)
#define	DMA_HRS_HRS10_SHIFT (10U)
#define	DMA_HRS_HRS10(x)
#define	DMA_HRS_HRS11_MASK (0x800U)
#define	DMA_HRS_HRS11_SHIFT (11U)
#define	DMA_HRS_HRS11(x)
#define	DMA_HRS_HRS12_MASK (0x1000U)
#define	DMA_HRS_HRS12_SHIFT (12U)
#define	DMA_HRS_HRS12(x)
#define	DMA_HRS_HRS13_MASK (0x2000U)
#define	DMA_HRS_HRS13_SHIFT (13U)
#define	DMA_HRS_HRS13(x)
#define	DMA_HRS_HRS14_MASK (0x4000U)
#define	DMA_HRS_HRS14_SHIFT (14U)
#define	DMA_HRS_HRS14(x)
#define	DMA_HRS_HRS15_MASK (0x8000U)
#define	DMA_HRS_HRS15_SHIFT (15U)
#define	DMA_HRS_HRS15(x)
#define	DMA_HRS_HRS16_MASK (0x10000U)
#define	DMA_HRS_HRS16_SHIFT (16U)
#define	DMA_HRS_HRS16(x)
#define	DMA_HRS_HRS17_MASK (0x20000U)
#define	DMA_HRS_HRS17_SHIFT (17U)
#define	DMA_HRS_HRS17(x)
#define	DMA_HRS_HRS18_MASK (0x40000U)
#define	DMA_HRS_HRS18_SHIFT (18U)
#define	DMA_HRS_HRS18(x)
#define	DMA_HRS_HRS19_MASK (0x80000U)
#define	DMA_HRS_HRS19_SHIFT (19U)
#define	DMA_HRS_HRS19(x)
#define	DMA_HRS_HRS20_MASK (0x100000U)
#define	DMA_HRS_HRS20_SHIFT (20U)
#define	DMA_HRS_HRS20(x)
#define	DMA_HRS_HRS21_MASK (0x200000U)
#define	DMA_HRS_HRS21_SHIFT (21U)
#define	DMA_HRS_HRS21(x)
#define	DMA_HRS_HRS22_MASK (0x400000U)
#define	DMA_HRS_HRS22_SHIFT (22U)
#define	DMA_HRS_HRS22(x)
#define	DMA_HRS_HRS23_MASK (0x800000U)
#define	DMA_HRS_HRS23_SHIFT (23U)
#define	DMA_HRS_HRS23(x)
#define	DMA_HRS_HRS24_MASK (0x1000000U)
#define	DMA_HRS_HRS24_SHIFT (24U)
#define	DMA_HRS_HRS24(x)
#define	DMA_HRS_HRS25_MASK (0x2000000U)
#define	DMA_HRS_HRS25_SHIFT (25U)
#define	DMA_HRS_HRS25(x)
#define	DMA_HRS_HRS26_MASK (0x4000000U)
#define	DMA_HRS_HRS26_SHIFT (26U)
#define	DMA_HRS_HRS26(x)
#define	DMA_HRS_HRS27_MASK (0x8000000U)
#define	DMA_HRS_HRS27_SHIFT (27U)
#define	DMA_HRS_HRS27(x)
#define	DMA_HRS_HRS28_MASK (0x10000000U)
#define	DMA_HRS_HRS28_SHIFT (28U)
#define	DMA_HRS_HRS28(x)
#define	DMA_HRS_HRS29_MASK (0x20000000U)
#define	DMA_HRS_HRS29_SHIFT (29U)
#define	DMA_HRS_HRS29(x)
#define	DMA_HRS_HRS30_MASK (0x40000000U)
#define	DMA_HRS_HRS30_SHIFT (30U)
#define	DMA_HRS_HRS30(x)
#define	DMA_HRS_HRS31_MASK (0x80000000U)
#define	DMA_HRS_HRS31_SHIFT (31U)
#define	DMA_HRS_HRS31(x)
#define	DMA_HRS_HRS0_MASK (0x1U)
#define	DMA_HRS_HRS0_SHIFT (0U)
#define	DMA_HRS_HRS0(x)
#define	DMA_HRS_HRS1_MASK (0x2U)
#define	DMA_HRS_HRS1_SHIFT (1U)
#define	DMA_HRS_HRS1(x)
#define	DMA_HRS_HRS2_MASK (0x4U)
#define	DMA_HRS_HRS2_SHIFT (2U)
#define	DMA_HRS_HRS2(x)
#define	DMA_HRS_HRS3_MASK (0x8U)
#define	DMA_HRS_HRS3_SHIFT (3U)
#define	DMA_HRS_HRS3(x)
#define	DMA_HRS_HRS4_MASK (0x10U)
#define	DMA_HRS_HRS4_SHIFT (4U)
#define	DMA_HRS_HRS4(x)
#define	DMA_HRS_HRS5_MASK (0x20U)
#define	DMA_HRS_HRS5_SHIFT (5U)
#define	DMA_HRS_HRS5(x)
#define	DMA_HRS_HRS6_MASK (0x40U)
#define	DMA_HRS_HRS6_SHIFT (6U)
#define	DMA_HRS_HRS6(x)
#define	DMA_HRS_HRS7_MASK (0x80U)
#define	DMA_HRS_HRS7_SHIFT (7U)
#define	DMA_HRS_HRS7(x)
#define	DMA_HRS_HRS8_MASK (0x100U)
#define	DMA_HRS_HRS8_SHIFT (8U)
#define	DMA_HRS_HRS8(x)
#define	DMA_HRS_HRS9_MASK (0x200U)
#define	DMA_HRS_HRS9_SHIFT (9U)
#define	DMA_HRS_HRS9(x)
#define	DMA_HRS_HRS10_MASK (0x400U)
#define	DMA_HRS_HRS10_SHIFT (10U)
#define	DMA_HRS_HRS10(x)
#define	DMA_HRS_HRS11_MASK (0x800U)
#define	DMA_HRS_HRS11_SHIFT (11U)
#define	DMA_HRS_HRS11(x)
#define	DMA_HRS_HRS12_MASK (0x1000U)
#define	DMA_HRS_HRS12_SHIFT (12U)
#define	DMA_HRS_HRS12(x)
#define	DMA_HRS_HRS13_MASK (0x2000U)
#define	DMA_HRS_HRS13_SHIFT (13U)
#define	DMA_HRS_HRS13(x)
#define	DMA_HRS_HRS14_MASK (0x4000U)
#define	DMA_HRS_HRS14_SHIFT (14U)
#define	DMA_HRS_HRS14(x)
#define	DMA_HRS_HRS15_MASK (0x8000U)
#define	DMA_HRS_HRS15_SHIFT (15U)
#define	DMA_HRS_HRS15(x)
#define	DMA_HRS_HRS16_MASK (0x10000U)
#define	DMA_HRS_HRS16_SHIFT (16U)
#define	DMA_HRS_HRS16(x)
#define	DMA_HRS_HRS17_MASK (0x20000U)
#define	DMA_HRS_HRS17_SHIFT (17U)
#define	DMA_HRS_HRS17(x)
#define	DMA_HRS_HRS18_MASK (0x40000U)
#define	DMA_HRS_HRS18_SHIFT (18U)
#define	DMA_HRS_HRS18(x)
#define	DMA_HRS_HRS19_MASK (0x80000U)
#define	DMA_HRS_HRS19_SHIFT (19U)
#define	DMA_HRS_HRS19(x)
#define	DMA_HRS_HRS20_MASK (0x100000U)
#define	DMA_HRS_HRS20_SHIFT (20U)
#define	DMA_HRS_HRS20(x)
#define	DMA_HRS_HRS21_MASK (0x200000U)
#define	DMA_HRS_HRS21_SHIFT (21U)
#define	DMA_HRS_HRS21(x)
#define	DMA_HRS_HRS22_MASK (0x400000U)
#define	DMA_HRS_HRS22_SHIFT (22U)
#define	DMA_HRS_HRS22(x)
#define	DMA_HRS_HRS23_MASK (0x800000U)
#define	DMA_HRS_HRS23_SHIFT (23U)
#define	DMA_HRS_HRS23(x)
#define	DMA_HRS_HRS24_MASK (0x1000000U)
#define	DMA_HRS_HRS24_SHIFT (24U)
#define	DMA_HRS_HRS24(x)
#define	DMA_HRS_HRS25_MASK (0x2000000U)
#define	DMA_HRS_HRS25_SHIFT (25U)
#define	DMA_HRS_HRS25(x)
#define	DMA_HRS_HRS26_MASK (0x4000000U)
#define	DMA_HRS_HRS26_SHIFT (26U)
#define	DMA_HRS_HRS26(x)
#define	DMA_HRS_HRS27_MASK (0x8000000U)
#define	DMA_HRS_HRS27_SHIFT (27U)
#define	DMA_HRS_HRS27(x)
#define	DMA_HRS_HRS28_MASK (0x10000000U)
#define	DMA_HRS_HRS28_SHIFT (28U)
#define	DMA_HRS_HRS28(x)
#define	DMA_HRS_HRS29_MASK (0x20000000U)
#define	DMA_HRS_HRS29_SHIFT (29U)
#define	DMA_HRS_HRS29(x)
#define	DMA_HRS_HRS30_MASK (0x40000000U)
#define	DMA_HRS_HRS30_SHIFT (30U)
#define	DMA_HRS_HRS30(x)
#define	DMA_HRS_HRS31_MASK (0x80000000U)
#define	DMA_HRS_HRS31_SHIFT (31U)
#define	DMA_HRS_HRS31(x)
#define	DMA_HRS_HRS0_MASK (0x1U)
#define	DMA_HRS_HRS0_SHIFT (0U)
#define	DMA_HRS_HRS0(x)
#define	DMA_HRS_HRS1_MASK (0x2U)
#define	DMA_HRS_HRS1_SHIFT (1U)
#define	DMA_HRS_HRS1(x)
#define	DMA_HRS_HRS2_MASK (0x4U)
#define	DMA_HRS_HRS2_SHIFT (2U)
#define	DMA_HRS_HRS2(x)
#define	DMA_HRS_HRS3_MASK (0x8U)
#define	DMA_HRS_HRS3_SHIFT (3U)
#define	DMA_HRS_HRS3(x)
#define	DMA_HRS_HRS4_MASK (0x10U)
#define	DMA_HRS_HRS4_SHIFT (4U)
#define	DMA_HRS_HRS4(x)
#define	DMA_HRS_HRS5_MASK (0x20U)
#define	DMA_HRS_HRS5_SHIFT (5U)
#define	DMA_HRS_HRS5(x)
#define	DMA_HRS_HRS6_MASK (0x40U)
#define	DMA_HRS_HRS6_SHIFT (6U)
#define	DMA_HRS_HRS6(x)
#define	DMA_HRS_HRS7_MASK (0x80U)
#define	DMA_HRS_HRS7_SHIFT (7U)
#define	DMA_HRS_HRS7(x)
#define	DMA_HRS_HRS8_MASK (0x100U)
#define	DMA_HRS_HRS8_SHIFT (8U)
#define	DMA_HRS_HRS8(x)
#define	DMA_HRS_HRS9_MASK (0x200U)
#define	DMA_HRS_HRS9_SHIFT (9U)
#define	DMA_HRS_HRS9(x)
#define	DMA_HRS_HRS10_MASK (0x400U)
#define	DMA_HRS_HRS10_SHIFT (10U)
#define	DMA_HRS_HRS10(x)
#define	DMA_HRS_HRS11_MASK (0x800U)
#define	DMA_HRS_HRS11_SHIFT (11U)
#define	DMA_HRS_HRS11(x)
#define	DMA_HRS_HRS12_MASK (0x1000U)
#define	DMA_HRS_HRS12_SHIFT (12U)
#define	DMA_HRS_HRS12(x)
#define	DMA_HRS_HRS13_MASK (0x2000U)
#define	DMA_HRS_HRS13_SHIFT (13U)
#define	DMA_HRS_HRS13(x)
#define	DMA_HRS_HRS14_MASK (0x4000U)
#define	DMA_HRS_HRS14_SHIFT (14U)
#define	DMA_HRS_HRS14(x)
#define	DMA_HRS_HRS15_MASK (0x8000U)
#define	DMA_HRS_HRS15_SHIFT (15U)
#define	DMA_HRS_HRS15(x)
#define	DMA_HRS_HRS16_MASK (0x10000U)
#define	DMA_HRS_HRS16_SHIFT (16U)
#define	DMA_HRS_HRS16(x)
#define	DMA_HRS_HRS17_MASK (0x20000U)
#define	DMA_HRS_HRS17_SHIFT (17U)
#define	DMA_HRS_HRS17(x)
#define	DMA_HRS_HRS18_MASK (0x40000U)
#define	DMA_HRS_HRS18_SHIFT (18U)
#define	DMA_HRS_HRS18(x)
#define	DMA_HRS_HRS19_MASK (0x80000U)
#define	DMA_HRS_HRS19_SHIFT (19U)
#define	DMA_HRS_HRS19(x)
#define	DMA_HRS_HRS20_MASK (0x100000U)
#define	DMA_HRS_HRS20_SHIFT (20U)
#define	DMA_HRS_HRS20(x)
#define	DMA_HRS_HRS21_MASK (0x200000U)
#define	DMA_HRS_HRS21_SHIFT (21U)
#define	DMA_HRS_HRS21(x)
#define	DMA_HRS_HRS22_MASK (0x400000U)
#define	DMA_HRS_HRS22_SHIFT (22U)
#define	DMA_HRS_HRS22(x)
#define	DMA_HRS_HRS23_MASK (0x800000U)
#define	DMA_HRS_HRS23_SHIFT (23U)
#define	DMA_HRS_HRS23(x)
#define	DMA_HRS_HRS24_MASK (0x1000000U)
#define	DMA_HRS_HRS24_SHIFT (24U)
#define	DMA_HRS_HRS24(x)
#define	DMA_HRS_HRS25_MASK (0x2000000U)
#define	DMA_HRS_HRS25_SHIFT (25U)
#define	DMA_HRS_HRS25(x)
#define	DMA_HRS_HRS26_MASK (0x4000000U)
#define	DMA_HRS_HRS26_SHIFT (26U)
#define	DMA_HRS_HRS26(x)
#define	DMA_HRS_HRS27_MASK (0x8000000U)
#define	DMA_HRS_HRS27_SHIFT (27U)
#define	DMA_HRS_HRS27(x)
#define	DMA_HRS_HRS28_MASK (0x10000000U)
#define	DMA_HRS_HRS28_SHIFT (28U)
#define	DMA_HRS_HRS28(x)
#define	DMA_HRS_HRS29_MASK (0x20000000U)
#define	DMA_HRS_HRS29_SHIFT (29U)
#define	DMA_HRS_HRS29(x)
#define	DMA_HRS_HRS30_MASK (0x40000000U)
#define	DMA_HRS_HRS30_SHIFT (30U)
#define	DMA_HRS_HRS30(x)
#define	DMA_HRS_HRS31_MASK (0x80000000U)
#define	DMA_HRS_HRS31_SHIFT (31U)
#define	DMA_HRS_HRS31(x)

EARS - Enable Asynchronous Request in Stop
#define	DMA_EARS_EDREQ_0_MASK (0x1U)
#define	DMA_EARS_EDREQ_0_SHIFT (0U)
#define	DMA_EARS_EDREQ_0(x)
#define	DMA_EARS_EDREQ_1_MASK (0x2U)
#define	DMA_EARS_EDREQ_1_SHIFT (1U)
#define	DMA_EARS_EDREQ_1(x)
#define	DMA_EARS_EDREQ_2_MASK (0x4U)
#define	DMA_EARS_EDREQ_2_SHIFT (2U)
#define	DMA_EARS_EDREQ_2(x)
#define	DMA_EARS_EDREQ_3_MASK (0x8U)
#define	DMA_EARS_EDREQ_3_SHIFT (3U)
#define	DMA_EARS_EDREQ_3(x)
#define	DMA_EARS_EDREQ_4_MASK (0x10U)
#define	DMA_EARS_EDREQ_4_SHIFT (4U)
#define	DMA_EARS_EDREQ_4(x)
#define	DMA_EARS_EDREQ_5_MASK (0x20U)
#define	DMA_EARS_EDREQ_5_SHIFT (5U)
#define	DMA_EARS_EDREQ_5(x)
#define	DMA_EARS_EDREQ_6_MASK (0x40U)
#define	DMA_EARS_EDREQ_6_SHIFT (6U)
#define	DMA_EARS_EDREQ_6(x)
#define	DMA_EARS_EDREQ_7_MASK (0x80U)
#define	DMA_EARS_EDREQ_7_SHIFT (7U)
#define	DMA_EARS_EDREQ_7(x)
#define	DMA_EARS_EDREQ_8_MASK (0x100U)
#define	DMA_EARS_EDREQ_8_SHIFT (8U)
#define	DMA_EARS_EDREQ_8(x)
#define	DMA_EARS_EDREQ_9_MASK (0x200U)
#define	DMA_EARS_EDREQ_9_SHIFT (9U)
#define	DMA_EARS_EDREQ_9(x)
#define	DMA_EARS_EDREQ_10_MASK (0x400U)
#define	DMA_EARS_EDREQ_10_SHIFT (10U)
#define	DMA_EARS_EDREQ_10(x)
#define	DMA_EARS_EDREQ_11_MASK (0x800U)
#define	DMA_EARS_EDREQ_11_SHIFT (11U)
#define	DMA_EARS_EDREQ_11(x)
#define	DMA_EARS_EDREQ_12_MASK (0x1000U)
#define	DMA_EARS_EDREQ_12_SHIFT (12U)
#define	DMA_EARS_EDREQ_12(x)
#define	DMA_EARS_EDREQ_13_MASK (0x2000U)
#define	DMA_EARS_EDREQ_13_SHIFT (13U)
#define	DMA_EARS_EDREQ_13(x)
#define	DMA_EARS_EDREQ_14_MASK (0x4000U)
#define	DMA_EARS_EDREQ_14_SHIFT (14U)
#define	DMA_EARS_EDREQ_14(x)
#define	DMA_EARS_EDREQ_15_MASK (0x8000U)
#define	DMA_EARS_EDREQ_15_SHIFT (15U)
#define	DMA_EARS_EDREQ_15(x)
#define	DMA_EARS_EDREQ_16_MASK (0x10000U)
#define	DMA_EARS_EDREQ_16_SHIFT (16U)
#define	DMA_EARS_EDREQ_16(x)
#define	DMA_EARS_EDREQ_17_MASK (0x20000U)
#define	DMA_EARS_EDREQ_17_SHIFT (17U)
#define	DMA_EARS_EDREQ_17(x)
#define	DMA_EARS_EDREQ_18_MASK (0x40000U)
#define	DMA_EARS_EDREQ_18_SHIFT (18U)
#define	DMA_EARS_EDREQ_18(x)
#define	DMA_EARS_EDREQ_19_MASK (0x80000U)
#define	DMA_EARS_EDREQ_19_SHIFT (19U)
#define	DMA_EARS_EDREQ_19(x)
#define	DMA_EARS_EDREQ_20_MASK (0x100000U)
#define	DMA_EARS_EDREQ_20_SHIFT (20U)
#define	DMA_EARS_EDREQ_20(x)
#define	DMA_EARS_EDREQ_21_MASK (0x200000U)
#define	DMA_EARS_EDREQ_21_SHIFT (21U)
#define	DMA_EARS_EDREQ_21(x)
#define	DMA_EARS_EDREQ_22_MASK (0x400000U)
#define	DMA_EARS_EDREQ_22_SHIFT (22U)
#define	DMA_EARS_EDREQ_22(x)
#define	DMA_EARS_EDREQ_23_MASK (0x800000U)
#define	DMA_EARS_EDREQ_23_SHIFT (23U)
#define	DMA_EARS_EDREQ_23(x)
#define	DMA_EARS_EDREQ_24_MASK (0x1000000U)
#define	DMA_EARS_EDREQ_24_SHIFT (24U)
#define	DMA_EARS_EDREQ_24(x)
#define	DMA_EARS_EDREQ_25_MASK (0x2000000U)
#define	DMA_EARS_EDREQ_25_SHIFT (25U)
#define	DMA_EARS_EDREQ_25(x)
#define	DMA_EARS_EDREQ_26_MASK (0x4000000U)
#define	DMA_EARS_EDREQ_26_SHIFT (26U)
#define	DMA_EARS_EDREQ_26(x)
#define	DMA_EARS_EDREQ_27_MASK (0x8000000U)
#define	DMA_EARS_EDREQ_27_SHIFT (27U)
#define	DMA_EARS_EDREQ_27(x)
#define	DMA_EARS_EDREQ_28_MASK (0x10000000U)
#define	DMA_EARS_EDREQ_28_SHIFT (28U)
#define	DMA_EARS_EDREQ_28(x)
#define	DMA_EARS_EDREQ_29_MASK (0x20000000U)
#define	DMA_EARS_EDREQ_29_SHIFT (29U)
#define	DMA_EARS_EDREQ_29(x)
#define	DMA_EARS_EDREQ_30_MASK (0x40000000U)
#define	DMA_EARS_EDREQ_30_SHIFT (30U)
#define	DMA_EARS_EDREQ_30(x)
#define	DMA_EARS_EDREQ_31_MASK (0x80000000U)
#define	DMA_EARS_EDREQ_31_SHIFT (31U)
#define	DMA_EARS_EDREQ_31(x)
#define	DMA_EARS_EDREQ_0_MASK (0x1U)
#define	DMA_EARS_EDREQ_0_SHIFT (0U)
#define	DMA_EARS_EDREQ_0(x)
#define	DMA_EARS_EDREQ_1_MASK (0x2U)
#define	DMA_EARS_EDREQ_1_SHIFT (1U)
#define	DMA_EARS_EDREQ_1(x)
#define	DMA_EARS_EDREQ_2_MASK (0x4U)
#define	DMA_EARS_EDREQ_2_SHIFT (2U)
#define	DMA_EARS_EDREQ_2(x)
#define	DMA_EARS_EDREQ_3_MASK (0x8U)
#define	DMA_EARS_EDREQ_3_SHIFT (3U)
#define	DMA_EARS_EDREQ_3(x)
#define	DMA_EARS_EDREQ_4_MASK (0x10U)
#define	DMA_EARS_EDREQ_4_SHIFT (4U)
#define	DMA_EARS_EDREQ_4(x)
#define	DMA_EARS_EDREQ_5_MASK (0x20U)
#define	DMA_EARS_EDREQ_5_SHIFT (5U)
#define	DMA_EARS_EDREQ_5(x)
#define	DMA_EARS_EDREQ_6_MASK (0x40U)
#define	DMA_EARS_EDREQ_6_SHIFT (6U)
#define	DMA_EARS_EDREQ_6(x)
#define	DMA_EARS_EDREQ_7_MASK (0x80U)
#define	DMA_EARS_EDREQ_7_SHIFT (7U)
#define	DMA_EARS_EDREQ_7(x)
#define	DMA_EARS_EDREQ_8_MASK (0x100U)
#define	DMA_EARS_EDREQ_8_SHIFT (8U)
#define	DMA_EARS_EDREQ_8(x)
#define	DMA_EARS_EDREQ_9_MASK (0x200U)
#define	DMA_EARS_EDREQ_9_SHIFT (9U)
#define	DMA_EARS_EDREQ_9(x)
#define	DMA_EARS_EDREQ_10_MASK (0x400U)
#define	DMA_EARS_EDREQ_10_SHIFT (10U)
#define	DMA_EARS_EDREQ_10(x)
#define	DMA_EARS_EDREQ_11_MASK (0x800U)
#define	DMA_EARS_EDREQ_11_SHIFT (11U)
#define	DMA_EARS_EDREQ_11(x)
#define	DMA_EARS_EDREQ_12_MASK (0x1000U)
#define	DMA_EARS_EDREQ_12_SHIFT (12U)
#define	DMA_EARS_EDREQ_12(x)
#define	DMA_EARS_EDREQ_13_MASK (0x2000U)
#define	DMA_EARS_EDREQ_13_SHIFT (13U)
#define	DMA_EARS_EDREQ_13(x)
#define	DMA_EARS_EDREQ_14_MASK (0x4000U)
#define	DMA_EARS_EDREQ_14_SHIFT (14U)
#define	DMA_EARS_EDREQ_14(x)
#define	DMA_EARS_EDREQ_15_MASK (0x8000U)
#define	DMA_EARS_EDREQ_15_SHIFT (15U)
#define	DMA_EARS_EDREQ_15(x)
#define	DMA_EARS_EDREQ_16_MASK (0x10000U)
#define	DMA_EARS_EDREQ_16_SHIFT (16U)
#define	DMA_EARS_EDREQ_16(x)
#define	DMA_EARS_EDREQ_17_MASK (0x20000U)
#define	DMA_EARS_EDREQ_17_SHIFT (17U)
#define	DMA_EARS_EDREQ_17(x)
#define	DMA_EARS_EDREQ_18_MASK (0x40000U)
#define	DMA_EARS_EDREQ_18_SHIFT (18U)
#define	DMA_EARS_EDREQ_18(x)
#define	DMA_EARS_EDREQ_19_MASK (0x80000U)
#define	DMA_EARS_EDREQ_19_SHIFT (19U)
#define	DMA_EARS_EDREQ_19(x)
#define	DMA_EARS_EDREQ_20_MASK (0x100000U)
#define	DMA_EARS_EDREQ_20_SHIFT (20U)
#define	DMA_EARS_EDREQ_20(x)
#define	DMA_EARS_EDREQ_21_MASK (0x200000U)
#define	DMA_EARS_EDREQ_21_SHIFT (21U)
#define	DMA_EARS_EDREQ_21(x)
#define	DMA_EARS_EDREQ_22_MASK (0x400000U)
#define	DMA_EARS_EDREQ_22_SHIFT (22U)
#define	DMA_EARS_EDREQ_22(x)
#define	DMA_EARS_EDREQ_23_MASK (0x800000U)
#define	DMA_EARS_EDREQ_23_SHIFT (23U)
#define	DMA_EARS_EDREQ_23(x)
#define	DMA_EARS_EDREQ_24_MASK (0x1000000U)
#define	DMA_EARS_EDREQ_24_SHIFT (24U)
#define	DMA_EARS_EDREQ_24(x)
#define	DMA_EARS_EDREQ_25_MASK (0x2000000U)
#define	DMA_EARS_EDREQ_25_SHIFT (25U)
#define	DMA_EARS_EDREQ_25(x)
#define	DMA_EARS_EDREQ_26_MASK (0x4000000U)
#define	DMA_EARS_EDREQ_26_SHIFT (26U)
#define	DMA_EARS_EDREQ_26(x)
#define	DMA_EARS_EDREQ_27_MASK (0x8000000U)
#define	DMA_EARS_EDREQ_27_SHIFT (27U)
#define	DMA_EARS_EDREQ_27(x)
#define	DMA_EARS_EDREQ_28_MASK (0x10000000U)
#define	DMA_EARS_EDREQ_28_SHIFT (28U)
#define	DMA_EARS_EDREQ_28(x)
#define	DMA_EARS_EDREQ_29_MASK (0x20000000U)
#define	DMA_EARS_EDREQ_29_SHIFT (29U)
#define	DMA_EARS_EDREQ_29(x)
#define	DMA_EARS_EDREQ_30_MASK (0x40000000U)
#define	DMA_EARS_EDREQ_30_SHIFT (30U)
#define	DMA_EARS_EDREQ_30(x)
#define	DMA_EARS_EDREQ_31_MASK (0x80000000U)
#define	DMA_EARS_EDREQ_31_SHIFT (31U)
#define	DMA_EARS_EDREQ_31(x)
#define	DMA_EARS_EDREQ_0_MASK (0x1U)
#define	DMA_EARS_EDREQ_0_SHIFT (0U)
#define	DMA_EARS_EDREQ_0(x)
#define	DMA_EARS_EDREQ_1_MASK (0x2U)
#define	DMA_EARS_EDREQ_1_SHIFT (1U)
#define	DMA_EARS_EDREQ_1(x)
#define	DMA_EARS_EDREQ_2_MASK (0x4U)
#define	DMA_EARS_EDREQ_2_SHIFT (2U)
#define	DMA_EARS_EDREQ_2(x)
#define	DMA_EARS_EDREQ_3_MASK (0x8U)
#define	DMA_EARS_EDREQ_3_SHIFT (3U)
#define	DMA_EARS_EDREQ_3(x)
#define	DMA_EARS_EDREQ_4_MASK (0x10U)
#define	DMA_EARS_EDREQ_4_SHIFT (4U)
#define	DMA_EARS_EDREQ_4(x)
#define	DMA_EARS_EDREQ_5_MASK (0x20U)
#define	DMA_EARS_EDREQ_5_SHIFT (5U)
#define	DMA_EARS_EDREQ_5(x)
#define	DMA_EARS_EDREQ_6_MASK (0x40U)
#define	DMA_EARS_EDREQ_6_SHIFT (6U)
#define	DMA_EARS_EDREQ_6(x)
#define	DMA_EARS_EDREQ_7_MASK (0x80U)
#define	DMA_EARS_EDREQ_7_SHIFT (7U)
#define	DMA_EARS_EDREQ_7(x)
#define	DMA_EARS_EDREQ_8_MASK (0x100U)
#define	DMA_EARS_EDREQ_8_SHIFT (8U)
#define	DMA_EARS_EDREQ_8(x)
#define	DMA_EARS_EDREQ_9_MASK (0x200U)
#define	DMA_EARS_EDREQ_9_SHIFT (9U)
#define	DMA_EARS_EDREQ_9(x)
#define	DMA_EARS_EDREQ_10_MASK (0x400U)
#define	DMA_EARS_EDREQ_10_SHIFT (10U)
#define	DMA_EARS_EDREQ_10(x)
#define	DMA_EARS_EDREQ_11_MASK (0x800U)
#define	DMA_EARS_EDREQ_11_SHIFT (11U)
#define	DMA_EARS_EDREQ_11(x)
#define	DMA_EARS_EDREQ_12_MASK (0x1000U)
#define	DMA_EARS_EDREQ_12_SHIFT (12U)
#define	DMA_EARS_EDREQ_12(x)
#define	DMA_EARS_EDREQ_13_MASK (0x2000U)
#define	DMA_EARS_EDREQ_13_SHIFT (13U)
#define	DMA_EARS_EDREQ_13(x)
#define	DMA_EARS_EDREQ_14_MASK (0x4000U)
#define	DMA_EARS_EDREQ_14_SHIFT (14U)
#define	DMA_EARS_EDREQ_14(x)
#define	DMA_EARS_EDREQ_15_MASK (0x8000U)
#define	DMA_EARS_EDREQ_15_SHIFT (15U)
#define	DMA_EARS_EDREQ_15(x)
#define	DMA_EARS_EDREQ_16_MASK (0x10000U)
#define	DMA_EARS_EDREQ_16_SHIFT (16U)
#define	DMA_EARS_EDREQ_16(x)
#define	DMA_EARS_EDREQ_17_MASK (0x20000U)
#define	DMA_EARS_EDREQ_17_SHIFT (17U)
#define	DMA_EARS_EDREQ_17(x)
#define	DMA_EARS_EDREQ_18_MASK (0x40000U)
#define	DMA_EARS_EDREQ_18_SHIFT (18U)
#define	DMA_EARS_EDREQ_18(x)
#define	DMA_EARS_EDREQ_19_MASK (0x80000U)
#define	DMA_EARS_EDREQ_19_SHIFT (19U)
#define	DMA_EARS_EDREQ_19(x)
#define	DMA_EARS_EDREQ_20_MASK (0x100000U)
#define	DMA_EARS_EDREQ_20_SHIFT (20U)
#define	DMA_EARS_EDREQ_20(x)
#define	DMA_EARS_EDREQ_21_MASK (0x200000U)
#define	DMA_EARS_EDREQ_21_SHIFT (21U)
#define	DMA_EARS_EDREQ_21(x)
#define	DMA_EARS_EDREQ_22_MASK (0x400000U)
#define	DMA_EARS_EDREQ_22_SHIFT (22U)
#define	DMA_EARS_EDREQ_22(x)
#define	DMA_EARS_EDREQ_23_MASK (0x800000U)
#define	DMA_EARS_EDREQ_23_SHIFT (23U)
#define	DMA_EARS_EDREQ_23(x)
#define	DMA_EARS_EDREQ_24_MASK (0x1000000U)
#define	DMA_EARS_EDREQ_24_SHIFT (24U)
#define	DMA_EARS_EDREQ_24(x)
#define	DMA_EARS_EDREQ_25_MASK (0x2000000U)
#define	DMA_EARS_EDREQ_25_SHIFT (25U)
#define	DMA_EARS_EDREQ_25(x)
#define	DMA_EARS_EDREQ_26_MASK (0x4000000U)
#define	DMA_EARS_EDREQ_26_SHIFT (26U)
#define	DMA_EARS_EDREQ_26(x)
#define	DMA_EARS_EDREQ_27_MASK (0x8000000U)
#define	DMA_EARS_EDREQ_27_SHIFT (27U)
#define	DMA_EARS_EDREQ_27(x)
#define	DMA_EARS_EDREQ_28_MASK (0x10000000U)
#define	DMA_EARS_EDREQ_28_SHIFT (28U)
#define	DMA_EARS_EDREQ_28(x)
#define	DMA_EARS_EDREQ_29_MASK (0x20000000U)
#define	DMA_EARS_EDREQ_29_SHIFT (29U)
#define	DMA_EARS_EDREQ_29(x)
#define	DMA_EARS_EDREQ_30_MASK (0x40000000U)
#define	DMA_EARS_EDREQ_30_SHIFT (30U)
#define	DMA_EARS_EDREQ_30(x)
#define	DMA_EARS_EDREQ_31_MASK (0x80000000U)
#define	DMA_EARS_EDREQ_31_SHIFT (31U)
#define	DMA_EARS_EDREQ_31(x)

DCHPRI3 - Channel Priority
#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI3_CHPRI(x)
#define	DMA_DCHPRI3_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI3_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI3_GRPPRI(x)
#define	DMA_DCHPRI3_DPA_MASK (0x40U)
#define	DMA_DCHPRI3_DPA_SHIFT (6U)
#define	DMA_DCHPRI3_DPA(x)
#define	DMA_DCHPRI3_ECP_MASK (0x80U)
#define	DMA_DCHPRI3_ECP_SHIFT (7U)
#define	DMA_DCHPRI3_ECP(x)
#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI3_CHPRI(x)
#define	DMA_DCHPRI3_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI3_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI3_GRPPRI(x)
#define	DMA_DCHPRI3_DPA_MASK (0x40U)
#define	DMA_DCHPRI3_DPA_SHIFT (6U)
#define	DMA_DCHPRI3_DPA(x)
#define	DMA_DCHPRI3_ECP_MASK (0x80U)
#define	DMA_DCHPRI3_ECP_SHIFT (7U)
#define	DMA_DCHPRI3_ECP(x)
#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI3_CHPRI(x)
#define	DMA_DCHPRI3_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI3_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI3_GRPPRI(x)
#define	DMA_DCHPRI3_DPA_MASK (0x40U)
#define	DMA_DCHPRI3_DPA_SHIFT (6U)
#define	DMA_DCHPRI3_DPA(x)
#define	DMA_DCHPRI3_ECP_MASK (0x80U)
#define	DMA_DCHPRI3_ECP_SHIFT (7U)
#define	DMA_DCHPRI3_ECP(x)

DCHPRI2 - Channel Priority
#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI2_CHPRI(x)
#define	DMA_DCHPRI2_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI2_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI2_GRPPRI(x)
#define	DMA_DCHPRI2_DPA_MASK (0x40U)
#define	DMA_DCHPRI2_DPA_SHIFT (6U)
#define	DMA_DCHPRI2_DPA(x)
#define	DMA_DCHPRI2_ECP_MASK (0x80U)
#define	DMA_DCHPRI2_ECP_SHIFT (7U)
#define	DMA_DCHPRI2_ECP(x)
#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI2_CHPRI(x)
#define	DMA_DCHPRI2_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI2_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI2_GRPPRI(x)
#define	DMA_DCHPRI2_DPA_MASK (0x40U)
#define	DMA_DCHPRI2_DPA_SHIFT (6U)
#define	DMA_DCHPRI2_DPA(x)
#define	DMA_DCHPRI2_ECP_MASK (0x80U)
#define	DMA_DCHPRI2_ECP_SHIFT (7U)
#define	DMA_DCHPRI2_ECP(x)
#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI2_CHPRI(x)
#define	DMA_DCHPRI2_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI2_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI2_GRPPRI(x)
#define	DMA_DCHPRI2_DPA_MASK (0x40U)
#define	DMA_DCHPRI2_DPA_SHIFT (6U)
#define	DMA_DCHPRI2_DPA(x)
#define	DMA_DCHPRI2_ECP_MASK (0x80U)
#define	DMA_DCHPRI2_ECP_SHIFT (7U)
#define	DMA_DCHPRI2_ECP(x)

DCHPRI1 - Channel Priority
#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI1_CHPRI(x)
#define	DMA_DCHPRI1_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI1_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI1_GRPPRI(x)
#define	DMA_DCHPRI1_DPA_MASK (0x40U)
#define	DMA_DCHPRI1_DPA_SHIFT (6U)
#define	DMA_DCHPRI1_DPA(x)
#define	DMA_DCHPRI1_ECP_MASK (0x80U)
#define	DMA_DCHPRI1_ECP_SHIFT (7U)
#define	DMA_DCHPRI1_ECP(x)
#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI1_CHPRI(x)
#define	DMA_DCHPRI1_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI1_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI1_GRPPRI(x)
#define	DMA_DCHPRI1_DPA_MASK (0x40U)
#define	DMA_DCHPRI1_DPA_SHIFT (6U)
#define	DMA_DCHPRI1_DPA(x)
#define	DMA_DCHPRI1_ECP_MASK (0x80U)
#define	DMA_DCHPRI1_ECP_SHIFT (7U)
#define	DMA_DCHPRI1_ECP(x)
#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI1_CHPRI(x)
#define	DMA_DCHPRI1_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI1_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI1_GRPPRI(x)
#define	DMA_DCHPRI1_DPA_MASK (0x40U)
#define	DMA_DCHPRI1_DPA_SHIFT (6U)
#define	DMA_DCHPRI1_DPA(x)
#define	DMA_DCHPRI1_ECP_MASK (0x80U)
#define	DMA_DCHPRI1_ECP_SHIFT (7U)
#define	DMA_DCHPRI1_ECP(x)

DCHPRI0 - Channel Priority
#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI0_CHPRI(x)
#define	DMA_DCHPRI0_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI0_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI0_GRPPRI(x)
#define	DMA_DCHPRI0_DPA_MASK (0x40U)
#define	DMA_DCHPRI0_DPA_SHIFT (6U)
#define	DMA_DCHPRI0_DPA(x)
#define	DMA_DCHPRI0_ECP_MASK (0x80U)
#define	DMA_DCHPRI0_ECP_SHIFT (7U)
#define	DMA_DCHPRI0_ECP(x)
#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI0_CHPRI(x)
#define	DMA_DCHPRI0_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI0_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI0_GRPPRI(x)
#define	DMA_DCHPRI0_DPA_MASK (0x40U)
#define	DMA_DCHPRI0_DPA_SHIFT (6U)
#define	DMA_DCHPRI0_DPA(x)
#define	DMA_DCHPRI0_ECP_MASK (0x80U)
#define	DMA_DCHPRI0_ECP_SHIFT (7U)
#define	DMA_DCHPRI0_ECP(x)
#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI0_CHPRI(x)
#define	DMA_DCHPRI0_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI0_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI0_GRPPRI(x)
#define	DMA_DCHPRI0_DPA_MASK (0x40U)
#define	DMA_DCHPRI0_DPA_SHIFT (6U)
#define	DMA_DCHPRI0_DPA(x)
#define	DMA_DCHPRI0_ECP_MASK (0x80U)
#define	DMA_DCHPRI0_ECP_SHIFT (7U)
#define	DMA_DCHPRI0_ECP(x)

DCHPRI7 - Channel Priority
#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI7_CHPRI(x)
#define	DMA_DCHPRI7_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI7_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI7_GRPPRI(x)
#define	DMA_DCHPRI7_DPA_MASK (0x40U)
#define	DMA_DCHPRI7_DPA_SHIFT (6U)
#define	DMA_DCHPRI7_DPA(x)
#define	DMA_DCHPRI7_ECP_MASK (0x80U)
#define	DMA_DCHPRI7_ECP_SHIFT (7U)
#define	DMA_DCHPRI7_ECP(x)
#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI7_CHPRI(x)
#define	DMA_DCHPRI7_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI7_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI7_GRPPRI(x)
#define	DMA_DCHPRI7_DPA_MASK (0x40U)
#define	DMA_DCHPRI7_DPA_SHIFT (6U)
#define	DMA_DCHPRI7_DPA(x)
#define	DMA_DCHPRI7_ECP_MASK (0x80U)
#define	DMA_DCHPRI7_ECP_SHIFT (7U)
#define	DMA_DCHPRI7_ECP(x)
#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI7_CHPRI(x)
#define	DMA_DCHPRI7_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI7_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI7_GRPPRI(x)
#define	DMA_DCHPRI7_DPA_MASK (0x40U)
#define	DMA_DCHPRI7_DPA_SHIFT (6U)
#define	DMA_DCHPRI7_DPA(x)
#define	DMA_DCHPRI7_ECP_MASK (0x80U)
#define	DMA_DCHPRI7_ECP_SHIFT (7U)
#define	DMA_DCHPRI7_ECP(x)

DCHPRI6 - Channel Priority
#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI6_CHPRI(x)
#define	DMA_DCHPRI6_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI6_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI6_GRPPRI(x)
#define	DMA_DCHPRI6_DPA_MASK (0x40U)
#define	DMA_DCHPRI6_DPA_SHIFT (6U)
#define	DMA_DCHPRI6_DPA(x)
#define	DMA_DCHPRI6_ECP_MASK (0x80U)
#define	DMA_DCHPRI6_ECP_SHIFT (7U)
#define	DMA_DCHPRI6_ECP(x)
#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI6_CHPRI(x)
#define	DMA_DCHPRI6_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI6_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI6_GRPPRI(x)
#define	DMA_DCHPRI6_DPA_MASK (0x40U)
#define	DMA_DCHPRI6_DPA_SHIFT (6U)
#define	DMA_DCHPRI6_DPA(x)
#define	DMA_DCHPRI6_ECP_MASK (0x80U)
#define	DMA_DCHPRI6_ECP_SHIFT (7U)
#define	DMA_DCHPRI6_ECP(x)
#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI6_CHPRI(x)
#define	DMA_DCHPRI6_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI6_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI6_GRPPRI(x)
#define	DMA_DCHPRI6_DPA_MASK (0x40U)
#define	DMA_DCHPRI6_DPA_SHIFT (6U)
#define	DMA_DCHPRI6_DPA(x)
#define	DMA_DCHPRI6_ECP_MASK (0x80U)
#define	DMA_DCHPRI6_ECP_SHIFT (7U)
#define	DMA_DCHPRI6_ECP(x)

DCHPRI5 - Channel Priority
#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI5_CHPRI(x)
#define	DMA_DCHPRI5_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI5_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI5_GRPPRI(x)
#define	DMA_DCHPRI5_DPA_MASK (0x40U)
#define	DMA_DCHPRI5_DPA_SHIFT (6U)
#define	DMA_DCHPRI5_DPA(x)
#define	DMA_DCHPRI5_ECP_MASK (0x80U)
#define	DMA_DCHPRI5_ECP_SHIFT (7U)
#define	DMA_DCHPRI5_ECP(x)
#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI5_CHPRI(x)
#define	DMA_DCHPRI5_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI5_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI5_GRPPRI(x)
#define	DMA_DCHPRI5_DPA_MASK (0x40U)
#define	DMA_DCHPRI5_DPA_SHIFT (6U)
#define	DMA_DCHPRI5_DPA(x)
#define	DMA_DCHPRI5_ECP_MASK (0x80U)
#define	DMA_DCHPRI5_ECP_SHIFT (7U)
#define	DMA_DCHPRI5_ECP(x)
#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI5_CHPRI(x)
#define	DMA_DCHPRI5_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI5_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI5_GRPPRI(x)
#define	DMA_DCHPRI5_DPA_MASK (0x40U)
#define	DMA_DCHPRI5_DPA_SHIFT (6U)
#define	DMA_DCHPRI5_DPA(x)
#define	DMA_DCHPRI5_ECP_MASK (0x80U)
#define	DMA_DCHPRI5_ECP_SHIFT (7U)
#define	DMA_DCHPRI5_ECP(x)

DCHPRI4 - Channel Priority
#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI4_CHPRI(x)
#define	DMA_DCHPRI4_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI4_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI4_GRPPRI(x)
#define	DMA_DCHPRI4_DPA_MASK (0x40U)
#define	DMA_DCHPRI4_DPA_SHIFT (6U)
#define	DMA_DCHPRI4_DPA(x)
#define	DMA_DCHPRI4_ECP_MASK (0x80U)
#define	DMA_DCHPRI4_ECP_SHIFT (7U)
#define	DMA_DCHPRI4_ECP(x)
#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI4_CHPRI(x)
#define	DMA_DCHPRI4_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI4_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI4_GRPPRI(x)
#define	DMA_DCHPRI4_DPA_MASK (0x40U)
#define	DMA_DCHPRI4_DPA_SHIFT (6U)
#define	DMA_DCHPRI4_DPA(x)
#define	DMA_DCHPRI4_ECP_MASK (0x80U)
#define	DMA_DCHPRI4_ECP_SHIFT (7U)
#define	DMA_DCHPRI4_ECP(x)
#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI4_CHPRI(x)
#define	DMA_DCHPRI4_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI4_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI4_GRPPRI(x)
#define	DMA_DCHPRI4_DPA_MASK (0x40U)
#define	DMA_DCHPRI4_DPA_SHIFT (6U)
#define	DMA_DCHPRI4_DPA(x)
#define	DMA_DCHPRI4_ECP_MASK (0x80U)
#define	DMA_DCHPRI4_ECP_SHIFT (7U)
#define	DMA_DCHPRI4_ECP(x)

DCHPRI11 - Channel Priority
#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI11_CHPRI(x)
#define	DMA_DCHPRI11_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI11_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI11_GRPPRI(x)
#define	DMA_DCHPRI11_DPA_MASK (0x40U)
#define	DMA_DCHPRI11_DPA_SHIFT (6U)
#define	DMA_DCHPRI11_DPA(x)
#define	DMA_DCHPRI11_ECP_MASK (0x80U)
#define	DMA_DCHPRI11_ECP_SHIFT (7U)
#define	DMA_DCHPRI11_ECP(x)
#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI11_CHPRI(x)
#define	DMA_DCHPRI11_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI11_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI11_GRPPRI(x)
#define	DMA_DCHPRI11_DPA_MASK (0x40U)
#define	DMA_DCHPRI11_DPA_SHIFT (6U)
#define	DMA_DCHPRI11_DPA(x)
#define	DMA_DCHPRI11_ECP_MASK (0x80U)
#define	DMA_DCHPRI11_ECP_SHIFT (7U)
#define	DMA_DCHPRI11_ECP(x)
#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI11_CHPRI(x)
#define	DMA_DCHPRI11_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI11_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI11_GRPPRI(x)
#define	DMA_DCHPRI11_DPA_MASK (0x40U)
#define	DMA_DCHPRI11_DPA_SHIFT (6U)
#define	DMA_DCHPRI11_DPA(x)
#define	DMA_DCHPRI11_ECP_MASK (0x80U)
#define	DMA_DCHPRI11_ECP_SHIFT (7U)
#define	DMA_DCHPRI11_ECP(x)

DCHPRI10 - Channel Priority
#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI10_CHPRI(x)
#define	DMA_DCHPRI10_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI10_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI10_GRPPRI(x)
#define	DMA_DCHPRI10_DPA_MASK (0x40U)
#define	DMA_DCHPRI10_DPA_SHIFT (6U)
#define	DMA_DCHPRI10_DPA(x)
#define	DMA_DCHPRI10_ECP_MASK (0x80U)
#define	DMA_DCHPRI10_ECP_SHIFT (7U)
#define	DMA_DCHPRI10_ECP(x)
#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI10_CHPRI(x)
#define	DMA_DCHPRI10_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI10_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI10_GRPPRI(x)
#define	DMA_DCHPRI10_DPA_MASK (0x40U)
#define	DMA_DCHPRI10_DPA_SHIFT (6U)
#define	DMA_DCHPRI10_DPA(x)
#define	DMA_DCHPRI10_ECP_MASK (0x80U)
#define	DMA_DCHPRI10_ECP_SHIFT (7U)
#define	DMA_DCHPRI10_ECP(x)
#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI10_CHPRI(x)
#define	DMA_DCHPRI10_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI10_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI10_GRPPRI(x)
#define	DMA_DCHPRI10_DPA_MASK (0x40U)
#define	DMA_DCHPRI10_DPA_SHIFT (6U)
#define	DMA_DCHPRI10_DPA(x)
#define	DMA_DCHPRI10_ECP_MASK (0x80U)
#define	DMA_DCHPRI10_ECP_SHIFT (7U)
#define	DMA_DCHPRI10_ECP(x)

DCHPRI9 - Channel Priority
#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI9_CHPRI(x)
#define	DMA_DCHPRI9_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI9_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI9_GRPPRI(x)
#define	DMA_DCHPRI9_DPA_MASK (0x40U)
#define	DMA_DCHPRI9_DPA_SHIFT (6U)
#define	DMA_DCHPRI9_DPA(x)
#define	DMA_DCHPRI9_ECP_MASK (0x80U)
#define	DMA_DCHPRI9_ECP_SHIFT (7U)
#define	DMA_DCHPRI9_ECP(x)
#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI9_CHPRI(x)
#define	DMA_DCHPRI9_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI9_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI9_GRPPRI(x)
#define	DMA_DCHPRI9_DPA_MASK (0x40U)
#define	DMA_DCHPRI9_DPA_SHIFT (6U)
#define	DMA_DCHPRI9_DPA(x)
#define	DMA_DCHPRI9_ECP_MASK (0x80U)
#define	DMA_DCHPRI9_ECP_SHIFT (7U)
#define	DMA_DCHPRI9_ECP(x)
#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI9_CHPRI(x)
#define	DMA_DCHPRI9_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI9_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI9_GRPPRI(x)
#define	DMA_DCHPRI9_DPA_MASK (0x40U)
#define	DMA_DCHPRI9_DPA_SHIFT (6U)
#define	DMA_DCHPRI9_DPA(x)
#define	DMA_DCHPRI9_ECP_MASK (0x80U)
#define	DMA_DCHPRI9_ECP_SHIFT (7U)
#define	DMA_DCHPRI9_ECP(x)

DCHPRI8 - Channel Priority
#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI8_CHPRI(x)
#define	DMA_DCHPRI8_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI8_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI8_GRPPRI(x)
#define	DMA_DCHPRI8_DPA_MASK (0x40U)
#define	DMA_DCHPRI8_DPA_SHIFT (6U)
#define	DMA_DCHPRI8_DPA(x)
#define	DMA_DCHPRI8_ECP_MASK (0x80U)
#define	DMA_DCHPRI8_ECP_SHIFT (7U)
#define	DMA_DCHPRI8_ECP(x)
#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI8_CHPRI(x)
#define	DMA_DCHPRI8_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI8_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI8_GRPPRI(x)
#define	DMA_DCHPRI8_DPA_MASK (0x40U)
#define	DMA_DCHPRI8_DPA_SHIFT (6U)
#define	DMA_DCHPRI8_DPA(x)
#define	DMA_DCHPRI8_ECP_MASK (0x80U)
#define	DMA_DCHPRI8_ECP_SHIFT (7U)
#define	DMA_DCHPRI8_ECP(x)
#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI8_CHPRI(x)
#define	DMA_DCHPRI8_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI8_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI8_GRPPRI(x)
#define	DMA_DCHPRI8_DPA_MASK (0x40U)
#define	DMA_DCHPRI8_DPA_SHIFT (6U)
#define	DMA_DCHPRI8_DPA(x)
#define	DMA_DCHPRI8_ECP_MASK (0x80U)
#define	DMA_DCHPRI8_ECP_SHIFT (7U)
#define	DMA_DCHPRI8_ECP(x)

DCHPRI15 - Channel Priority
#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI15_CHPRI(x)
#define	DMA_DCHPRI15_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI15_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI15_GRPPRI(x)
#define	DMA_DCHPRI15_DPA_MASK (0x40U)
#define	DMA_DCHPRI15_DPA_SHIFT (6U)
#define	DMA_DCHPRI15_DPA(x)
#define	DMA_DCHPRI15_ECP_MASK (0x80U)
#define	DMA_DCHPRI15_ECP_SHIFT (7U)
#define	DMA_DCHPRI15_ECP(x)
#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI15_CHPRI(x)
#define	DMA_DCHPRI15_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI15_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI15_GRPPRI(x)
#define	DMA_DCHPRI15_DPA_MASK (0x40U)
#define	DMA_DCHPRI15_DPA_SHIFT (6U)
#define	DMA_DCHPRI15_DPA(x)
#define	DMA_DCHPRI15_ECP_MASK (0x80U)
#define	DMA_DCHPRI15_ECP_SHIFT (7U)
#define	DMA_DCHPRI15_ECP(x)
#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI15_CHPRI(x)
#define	DMA_DCHPRI15_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI15_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI15_GRPPRI(x)
#define	DMA_DCHPRI15_DPA_MASK (0x40U)
#define	DMA_DCHPRI15_DPA_SHIFT (6U)
#define	DMA_DCHPRI15_DPA(x)
#define	DMA_DCHPRI15_ECP_MASK (0x80U)
#define	DMA_DCHPRI15_ECP_SHIFT (7U)
#define	DMA_DCHPRI15_ECP(x)

DCHPRI14 - Channel Priority
#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI14_CHPRI(x)
#define	DMA_DCHPRI14_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI14_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI14_GRPPRI(x)
#define	DMA_DCHPRI14_DPA_MASK (0x40U)
#define	DMA_DCHPRI14_DPA_SHIFT (6U)
#define	DMA_DCHPRI14_DPA(x)
#define	DMA_DCHPRI14_ECP_MASK (0x80U)
#define	DMA_DCHPRI14_ECP_SHIFT (7U)
#define	DMA_DCHPRI14_ECP(x)
#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI14_CHPRI(x)
#define	DMA_DCHPRI14_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI14_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI14_GRPPRI(x)
#define	DMA_DCHPRI14_DPA_MASK (0x40U)
#define	DMA_DCHPRI14_DPA_SHIFT (6U)
#define	DMA_DCHPRI14_DPA(x)
#define	DMA_DCHPRI14_ECP_MASK (0x80U)
#define	DMA_DCHPRI14_ECP_SHIFT (7U)
#define	DMA_DCHPRI14_ECP(x)
#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI14_CHPRI(x)
#define	DMA_DCHPRI14_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI14_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI14_GRPPRI(x)
#define	DMA_DCHPRI14_DPA_MASK (0x40U)
#define	DMA_DCHPRI14_DPA_SHIFT (6U)
#define	DMA_DCHPRI14_DPA(x)
#define	DMA_DCHPRI14_ECP_MASK (0x80U)
#define	DMA_DCHPRI14_ECP_SHIFT (7U)
#define	DMA_DCHPRI14_ECP(x)

DCHPRI13 - Channel Priority
#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI13_CHPRI(x)
#define	DMA_DCHPRI13_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI13_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI13_GRPPRI(x)
#define	DMA_DCHPRI13_DPA_MASK (0x40U)
#define	DMA_DCHPRI13_DPA_SHIFT (6U)
#define	DMA_DCHPRI13_DPA(x)
#define	DMA_DCHPRI13_ECP_MASK (0x80U)
#define	DMA_DCHPRI13_ECP_SHIFT (7U)
#define	DMA_DCHPRI13_ECP(x)
#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI13_CHPRI(x)
#define	DMA_DCHPRI13_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI13_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI13_GRPPRI(x)
#define	DMA_DCHPRI13_DPA_MASK (0x40U)
#define	DMA_DCHPRI13_DPA_SHIFT (6U)
#define	DMA_DCHPRI13_DPA(x)
#define	DMA_DCHPRI13_ECP_MASK (0x80U)
#define	DMA_DCHPRI13_ECP_SHIFT (7U)
#define	DMA_DCHPRI13_ECP(x)
#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI13_CHPRI(x)
#define	DMA_DCHPRI13_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI13_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI13_GRPPRI(x)
#define	DMA_DCHPRI13_DPA_MASK (0x40U)
#define	DMA_DCHPRI13_DPA_SHIFT (6U)
#define	DMA_DCHPRI13_DPA(x)
#define	DMA_DCHPRI13_ECP_MASK (0x80U)
#define	DMA_DCHPRI13_ECP_SHIFT (7U)
#define	DMA_DCHPRI13_ECP(x)

DCHPRI12 - Channel Priority
#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI12_CHPRI(x)
#define	DMA_DCHPRI12_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI12_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI12_GRPPRI(x)
#define	DMA_DCHPRI12_DPA_MASK (0x40U)
#define	DMA_DCHPRI12_DPA_SHIFT (6U)
#define	DMA_DCHPRI12_DPA(x)
#define	DMA_DCHPRI12_ECP_MASK (0x80U)
#define	DMA_DCHPRI12_ECP_SHIFT (7U)
#define	DMA_DCHPRI12_ECP(x)
#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI12_CHPRI(x)
#define	DMA_DCHPRI12_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI12_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI12_GRPPRI(x)
#define	DMA_DCHPRI12_DPA_MASK (0x40U)
#define	DMA_DCHPRI12_DPA_SHIFT (6U)
#define	DMA_DCHPRI12_DPA(x)
#define	DMA_DCHPRI12_ECP_MASK (0x80U)
#define	DMA_DCHPRI12_ECP_SHIFT (7U)
#define	DMA_DCHPRI12_ECP(x)
#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI12_CHPRI(x)
#define	DMA_DCHPRI12_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI12_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI12_GRPPRI(x)
#define	DMA_DCHPRI12_DPA_MASK (0x40U)
#define	DMA_DCHPRI12_DPA_SHIFT (6U)
#define	DMA_DCHPRI12_DPA(x)
#define	DMA_DCHPRI12_ECP_MASK (0x80U)
#define	DMA_DCHPRI12_ECP_SHIFT (7U)
#define	DMA_DCHPRI12_ECP(x)

DCHPRI19 - Channel Priority
#define	DMA_DCHPRI19_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI19_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI19_CHPRI(x)
#define	DMA_DCHPRI19_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI19_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI19_GRPPRI(x)
#define	DMA_DCHPRI19_DPA_MASK (0x40U)
#define	DMA_DCHPRI19_DPA_SHIFT (6U)
#define	DMA_DCHPRI19_DPA(x)
#define	DMA_DCHPRI19_ECP_MASK (0x80U)
#define	DMA_DCHPRI19_ECP_SHIFT (7U)
#define	DMA_DCHPRI19_ECP(x)
#define	DMA_DCHPRI19_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI19_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI19_CHPRI(x)
#define	DMA_DCHPRI19_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI19_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI19_GRPPRI(x)
#define	DMA_DCHPRI19_DPA_MASK (0x40U)
#define	DMA_DCHPRI19_DPA_SHIFT (6U)
#define	DMA_DCHPRI19_DPA(x)
#define	DMA_DCHPRI19_ECP_MASK (0x80U)
#define	DMA_DCHPRI19_ECP_SHIFT (7U)
#define	DMA_DCHPRI19_ECP(x)
#define	DMA_DCHPRI19_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI19_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI19_CHPRI(x)
#define	DMA_DCHPRI19_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI19_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI19_GRPPRI(x)
#define	DMA_DCHPRI19_DPA_MASK (0x40U)
#define	DMA_DCHPRI19_DPA_SHIFT (6U)
#define	DMA_DCHPRI19_DPA(x)
#define	DMA_DCHPRI19_ECP_MASK (0x80U)
#define	DMA_DCHPRI19_ECP_SHIFT (7U)
#define	DMA_DCHPRI19_ECP(x)

DCHPRI18 - Channel Priority
#define	DMA_DCHPRI18_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI18_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI18_CHPRI(x)
#define	DMA_DCHPRI18_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI18_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI18_GRPPRI(x)
#define	DMA_DCHPRI18_DPA_MASK (0x40U)
#define	DMA_DCHPRI18_DPA_SHIFT (6U)
#define	DMA_DCHPRI18_DPA(x)
#define	DMA_DCHPRI18_ECP_MASK (0x80U)
#define	DMA_DCHPRI18_ECP_SHIFT (7U)
#define	DMA_DCHPRI18_ECP(x)
#define	DMA_DCHPRI18_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI18_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI18_CHPRI(x)
#define	DMA_DCHPRI18_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI18_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI18_GRPPRI(x)
#define	DMA_DCHPRI18_DPA_MASK (0x40U)
#define	DMA_DCHPRI18_DPA_SHIFT (6U)
#define	DMA_DCHPRI18_DPA(x)
#define	DMA_DCHPRI18_ECP_MASK (0x80U)
#define	DMA_DCHPRI18_ECP_SHIFT (7U)
#define	DMA_DCHPRI18_ECP(x)
#define	DMA_DCHPRI18_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI18_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI18_CHPRI(x)
#define	DMA_DCHPRI18_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI18_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI18_GRPPRI(x)
#define	DMA_DCHPRI18_DPA_MASK (0x40U)
#define	DMA_DCHPRI18_DPA_SHIFT (6U)
#define	DMA_DCHPRI18_DPA(x)
#define	DMA_DCHPRI18_ECP_MASK (0x80U)
#define	DMA_DCHPRI18_ECP_SHIFT (7U)
#define	DMA_DCHPRI18_ECP(x)

DCHPRI17 - Channel Priority
#define	DMA_DCHPRI17_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI17_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI17_CHPRI(x)
#define	DMA_DCHPRI17_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI17_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI17_GRPPRI(x)
#define	DMA_DCHPRI17_DPA_MASK (0x40U)
#define	DMA_DCHPRI17_DPA_SHIFT (6U)
#define	DMA_DCHPRI17_DPA(x)
#define	DMA_DCHPRI17_ECP_MASK (0x80U)
#define	DMA_DCHPRI17_ECP_SHIFT (7U)
#define	DMA_DCHPRI17_ECP(x)
#define	DMA_DCHPRI17_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI17_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI17_CHPRI(x)
#define	DMA_DCHPRI17_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI17_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI17_GRPPRI(x)
#define	DMA_DCHPRI17_DPA_MASK (0x40U)
#define	DMA_DCHPRI17_DPA_SHIFT (6U)
#define	DMA_DCHPRI17_DPA(x)
#define	DMA_DCHPRI17_ECP_MASK (0x80U)
#define	DMA_DCHPRI17_ECP_SHIFT (7U)
#define	DMA_DCHPRI17_ECP(x)
#define	DMA_DCHPRI17_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI17_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI17_CHPRI(x)
#define	DMA_DCHPRI17_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI17_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI17_GRPPRI(x)
#define	DMA_DCHPRI17_DPA_MASK (0x40U)
#define	DMA_DCHPRI17_DPA_SHIFT (6U)
#define	DMA_DCHPRI17_DPA(x)
#define	DMA_DCHPRI17_ECP_MASK (0x80U)
#define	DMA_DCHPRI17_ECP_SHIFT (7U)
#define	DMA_DCHPRI17_ECP(x)

DCHPRI16 - Channel Priority
#define	DMA_DCHPRI16_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI16_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI16_CHPRI(x)
#define	DMA_DCHPRI16_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI16_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI16_GRPPRI(x)
#define	DMA_DCHPRI16_DPA_MASK (0x40U)
#define	DMA_DCHPRI16_DPA_SHIFT (6U)
#define	DMA_DCHPRI16_DPA(x)
#define	DMA_DCHPRI16_ECP_MASK (0x80U)
#define	DMA_DCHPRI16_ECP_SHIFT (7U)
#define	DMA_DCHPRI16_ECP(x)
#define	DMA_DCHPRI16_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI16_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI16_CHPRI(x)
#define	DMA_DCHPRI16_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI16_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI16_GRPPRI(x)
#define	DMA_DCHPRI16_DPA_MASK (0x40U)
#define	DMA_DCHPRI16_DPA_SHIFT (6U)
#define	DMA_DCHPRI16_DPA(x)
#define	DMA_DCHPRI16_ECP_MASK (0x80U)
#define	DMA_DCHPRI16_ECP_SHIFT (7U)
#define	DMA_DCHPRI16_ECP(x)
#define	DMA_DCHPRI16_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI16_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI16_CHPRI(x)
#define	DMA_DCHPRI16_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI16_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI16_GRPPRI(x)
#define	DMA_DCHPRI16_DPA_MASK (0x40U)
#define	DMA_DCHPRI16_DPA_SHIFT (6U)
#define	DMA_DCHPRI16_DPA(x)
#define	DMA_DCHPRI16_ECP_MASK (0x80U)
#define	DMA_DCHPRI16_ECP_SHIFT (7U)
#define	DMA_DCHPRI16_ECP(x)

DCHPRI23 - Channel Priority
#define	DMA_DCHPRI23_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI23_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI23_CHPRI(x)
#define	DMA_DCHPRI23_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI23_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI23_GRPPRI(x)
#define	DMA_DCHPRI23_DPA_MASK (0x40U)
#define	DMA_DCHPRI23_DPA_SHIFT (6U)
#define	DMA_DCHPRI23_DPA(x)
#define	DMA_DCHPRI23_ECP_MASK (0x80U)
#define	DMA_DCHPRI23_ECP_SHIFT (7U)
#define	DMA_DCHPRI23_ECP(x)
#define	DMA_DCHPRI23_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI23_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI23_CHPRI(x)
#define	DMA_DCHPRI23_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI23_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI23_GRPPRI(x)
#define	DMA_DCHPRI23_DPA_MASK (0x40U)
#define	DMA_DCHPRI23_DPA_SHIFT (6U)
#define	DMA_DCHPRI23_DPA(x)
#define	DMA_DCHPRI23_ECP_MASK (0x80U)
#define	DMA_DCHPRI23_ECP_SHIFT (7U)
#define	DMA_DCHPRI23_ECP(x)
#define	DMA_DCHPRI23_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI23_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI23_CHPRI(x)
#define	DMA_DCHPRI23_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI23_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI23_GRPPRI(x)
#define	DMA_DCHPRI23_DPA_MASK (0x40U)
#define	DMA_DCHPRI23_DPA_SHIFT (6U)
#define	DMA_DCHPRI23_DPA(x)
#define	DMA_DCHPRI23_ECP_MASK (0x80U)
#define	DMA_DCHPRI23_ECP_SHIFT (7U)
#define	DMA_DCHPRI23_ECP(x)

DCHPRI22 - Channel Priority
#define	DMA_DCHPRI22_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI22_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI22_CHPRI(x)
#define	DMA_DCHPRI22_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI22_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI22_GRPPRI(x)
#define	DMA_DCHPRI22_DPA_MASK (0x40U)
#define	DMA_DCHPRI22_DPA_SHIFT (6U)
#define	DMA_DCHPRI22_DPA(x)
#define	DMA_DCHPRI22_ECP_MASK (0x80U)
#define	DMA_DCHPRI22_ECP_SHIFT (7U)
#define	DMA_DCHPRI22_ECP(x)
#define	DMA_DCHPRI22_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI22_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI22_CHPRI(x)
#define	DMA_DCHPRI22_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI22_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI22_GRPPRI(x)
#define	DMA_DCHPRI22_DPA_MASK (0x40U)
#define	DMA_DCHPRI22_DPA_SHIFT (6U)
#define	DMA_DCHPRI22_DPA(x)
#define	DMA_DCHPRI22_ECP_MASK (0x80U)
#define	DMA_DCHPRI22_ECP_SHIFT (7U)
#define	DMA_DCHPRI22_ECP(x)
#define	DMA_DCHPRI22_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI22_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI22_CHPRI(x)
#define	DMA_DCHPRI22_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI22_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI22_GRPPRI(x)
#define	DMA_DCHPRI22_DPA_MASK (0x40U)
#define	DMA_DCHPRI22_DPA_SHIFT (6U)
#define	DMA_DCHPRI22_DPA(x)
#define	DMA_DCHPRI22_ECP_MASK (0x80U)
#define	DMA_DCHPRI22_ECP_SHIFT (7U)
#define	DMA_DCHPRI22_ECP(x)

DCHPRI21 - Channel Priority
#define	DMA_DCHPRI21_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI21_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI21_CHPRI(x)
#define	DMA_DCHPRI21_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI21_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI21_GRPPRI(x)
#define	DMA_DCHPRI21_DPA_MASK (0x40U)
#define	DMA_DCHPRI21_DPA_SHIFT (6U)
#define	DMA_DCHPRI21_DPA(x)
#define	DMA_DCHPRI21_ECP_MASK (0x80U)
#define	DMA_DCHPRI21_ECP_SHIFT (7U)
#define	DMA_DCHPRI21_ECP(x)
#define	DMA_DCHPRI21_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI21_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI21_CHPRI(x)
#define	DMA_DCHPRI21_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI21_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI21_GRPPRI(x)
#define	DMA_DCHPRI21_DPA_MASK (0x40U)
#define	DMA_DCHPRI21_DPA_SHIFT (6U)
#define	DMA_DCHPRI21_DPA(x)
#define	DMA_DCHPRI21_ECP_MASK (0x80U)
#define	DMA_DCHPRI21_ECP_SHIFT (7U)
#define	DMA_DCHPRI21_ECP(x)
#define	DMA_DCHPRI21_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI21_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI21_CHPRI(x)
#define	DMA_DCHPRI21_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI21_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI21_GRPPRI(x)
#define	DMA_DCHPRI21_DPA_MASK (0x40U)
#define	DMA_DCHPRI21_DPA_SHIFT (6U)
#define	DMA_DCHPRI21_DPA(x)
#define	DMA_DCHPRI21_ECP_MASK (0x80U)
#define	DMA_DCHPRI21_ECP_SHIFT (7U)
#define	DMA_DCHPRI21_ECP(x)

DCHPRI20 - Channel Priority
#define	DMA_DCHPRI20_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI20_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI20_CHPRI(x)
#define	DMA_DCHPRI20_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI20_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI20_GRPPRI(x)
#define	DMA_DCHPRI20_DPA_MASK (0x40U)
#define	DMA_DCHPRI20_DPA_SHIFT (6U)
#define	DMA_DCHPRI20_DPA(x)
#define	DMA_DCHPRI20_ECP_MASK (0x80U)
#define	DMA_DCHPRI20_ECP_SHIFT (7U)
#define	DMA_DCHPRI20_ECP(x)
#define	DMA_DCHPRI20_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI20_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI20_CHPRI(x)
#define	DMA_DCHPRI20_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI20_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI20_GRPPRI(x)
#define	DMA_DCHPRI20_DPA_MASK (0x40U)
#define	DMA_DCHPRI20_DPA_SHIFT (6U)
#define	DMA_DCHPRI20_DPA(x)
#define	DMA_DCHPRI20_ECP_MASK (0x80U)
#define	DMA_DCHPRI20_ECP_SHIFT (7U)
#define	DMA_DCHPRI20_ECP(x)
#define	DMA_DCHPRI20_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI20_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI20_CHPRI(x)
#define	DMA_DCHPRI20_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI20_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI20_GRPPRI(x)
#define	DMA_DCHPRI20_DPA_MASK (0x40U)
#define	DMA_DCHPRI20_DPA_SHIFT (6U)
#define	DMA_DCHPRI20_DPA(x)
#define	DMA_DCHPRI20_ECP_MASK (0x80U)
#define	DMA_DCHPRI20_ECP_SHIFT (7U)
#define	DMA_DCHPRI20_ECP(x)

DCHPRI27 - Channel Priority
#define	DMA_DCHPRI27_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI27_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI27_CHPRI(x)
#define	DMA_DCHPRI27_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI27_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI27_GRPPRI(x)
#define	DMA_DCHPRI27_DPA_MASK (0x40U)
#define	DMA_DCHPRI27_DPA_SHIFT (6U)
#define	DMA_DCHPRI27_DPA(x)
#define	DMA_DCHPRI27_ECP_MASK (0x80U)
#define	DMA_DCHPRI27_ECP_SHIFT (7U)
#define	DMA_DCHPRI27_ECP(x)
#define	DMA_DCHPRI27_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI27_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI27_CHPRI(x)
#define	DMA_DCHPRI27_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI27_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI27_GRPPRI(x)
#define	DMA_DCHPRI27_DPA_MASK (0x40U)
#define	DMA_DCHPRI27_DPA_SHIFT (6U)
#define	DMA_DCHPRI27_DPA(x)
#define	DMA_DCHPRI27_ECP_MASK (0x80U)
#define	DMA_DCHPRI27_ECP_SHIFT (7U)
#define	DMA_DCHPRI27_ECP(x)
#define	DMA_DCHPRI27_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI27_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI27_CHPRI(x)
#define	DMA_DCHPRI27_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI27_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI27_GRPPRI(x)
#define	DMA_DCHPRI27_DPA_MASK (0x40U)
#define	DMA_DCHPRI27_DPA_SHIFT (6U)
#define	DMA_DCHPRI27_DPA(x)
#define	DMA_DCHPRI27_ECP_MASK (0x80U)
#define	DMA_DCHPRI27_ECP_SHIFT (7U)
#define	DMA_DCHPRI27_ECP(x)

DCHPRI26 - Channel Priority
#define	DMA_DCHPRI26_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI26_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI26_CHPRI(x)
#define	DMA_DCHPRI26_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI26_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI26_GRPPRI(x)
#define	DMA_DCHPRI26_DPA_MASK (0x40U)
#define	DMA_DCHPRI26_DPA_SHIFT (6U)
#define	DMA_DCHPRI26_DPA(x)
#define	DMA_DCHPRI26_ECP_MASK (0x80U)
#define	DMA_DCHPRI26_ECP_SHIFT (7U)
#define	DMA_DCHPRI26_ECP(x)
#define	DMA_DCHPRI26_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI26_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI26_CHPRI(x)
#define	DMA_DCHPRI26_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI26_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI26_GRPPRI(x)
#define	DMA_DCHPRI26_DPA_MASK (0x40U)
#define	DMA_DCHPRI26_DPA_SHIFT (6U)
#define	DMA_DCHPRI26_DPA(x)
#define	DMA_DCHPRI26_ECP_MASK (0x80U)
#define	DMA_DCHPRI26_ECP_SHIFT (7U)
#define	DMA_DCHPRI26_ECP(x)
#define	DMA_DCHPRI26_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI26_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI26_CHPRI(x)
#define	DMA_DCHPRI26_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI26_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI26_GRPPRI(x)
#define	DMA_DCHPRI26_DPA_MASK (0x40U)
#define	DMA_DCHPRI26_DPA_SHIFT (6U)
#define	DMA_DCHPRI26_DPA(x)
#define	DMA_DCHPRI26_ECP_MASK (0x80U)
#define	DMA_DCHPRI26_ECP_SHIFT (7U)
#define	DMA_DCHPRI26_ECP(x)

DCHPRI25 - Channel Priority
#define	DMA_DCHPRI25_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI25_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI25_CHPRI(x)
#define	DMA_DCHPRI25_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI25_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI25_GRPPRI(x)
#define	DMA_DCHPRI25_DPA_MASK (0x40U)
#define	DMA_DCHPRI25_DPA_SHIFT (6U)
#define	DMA_DCHPRI25_DPA(x)
#define	DMA_DCHPRI25_ECP_MASK (0x80U)
#define	DMA_DCHPRI25_ECP_SHIFT (7U)
#define	DMA_DCHPRI25_ECP(x)
#define	DMA_DCHPRI25_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI25_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI25_CHPRI(x)
#define	DMA_DCHPRI25_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI25_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI25_GRPPRI(x)
#define	DMA_DCHPRI25_DPA_MASK (0x40U)
#define	DMA_DCHPRI25_DPA_SHIFT (6U)
#define	DMA_DCHPRI25_DPA(x)
#define	DMA_DCHPRI25_ECP_MASK (0x80U)
#define	DMA_DCHPRI25_ECP_SHIFT (7U)
#define	DMA_DCHPRI25_ECP(x)
#define	DMA_DCHPRI25_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI25_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI25_CHPRI(x)
#define	DMA_DCHPRI25_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI25_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI25_GRPPRI(x)
#define	DMA_DCHPRI25_DPA_MASK (0x40U)
#define	DMA_DCHPRI25_DPA_SHIFT (6U)
#define	DMA_DCHPRI25_DPA(x)
#define	DMA_DCHPRI25_ECP_MASK (0x80U)
#define	DMA_DCHPRI25_ECP_SHIFT (7U)
#define	DMA_DCHPRI25_ECP(x)

DCHPRI24 - Channel Priority
#define	DMA_DCHPRI24_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI24_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI24_CHPRI(x)
#define	DMA_DCHPRI24_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI24_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI24_GRPPRI(x)
#define	DMA_DCHPRI24_DPA_MASK (0x40U)
#define	DMA_DCHPRI24_DPA_SHIFT (6U)
#define	DMA_DCHPRI24_DPA(x)
#define	DMA_DCHPRI24_ECP_MASK (0x80U)
#define	DMA_DCHPRI24_ECP_SHIFT (7U)
#define	DMA_DCHPRI24_ECP(x)
#define	DMA_DCHPRI24_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI24_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI24_CHPRI(x)
#define	DMA_DCHPRI24_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI24_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI24_GRPPRI(x)
#define	DMA_DCHPRI24_DPA_MASK (0x40U)
#define	DMA_DCHPRI24_DPA_SHIFT (6U)
#define	DMA_DCHPRI24_DPA(x)
#define	DMA_DCHPRI24_ECP_MASK (0x80U)
#define	DMA_DCHPRI24_ECP_SHIFT (7U)
#define	DMA_DCHPRI24_ECP(x)
#define	DMA_DCHPRI24_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI24_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI24_CHPRI(x)
#define	DMA_DCHPRI24_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI24_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI24_GRPPRI(x)
#define	DMA_DCHPRI24_DPA_MASK (0x40U)
#define	DMA_DCHPRI24_DPA_SHIFT (6U)
#define	DMA_DCHPRI24_DPA(x)
#define	DMA_DCHPRI24_ECP_MASK (0x80U)
#define	DMA_DCHPRI24_ECP_SHIFT (7U)
#define	DMA_DCHPRI24_ECP(x)

DCHPRI31 - Channel Priority
#define	DMA_DCHPRI31_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI31_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI31_CHPRI(x)
#define	DMA_DCHPRI31_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI31_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI31_GRPPRI(x)
#define	DMA_DCHPRI31_DPA_MASK (0x40U)
#define	DMA_DCHPRI31_DPA_SHIFT (6U)
#define	DMA_DCHPRI31_DPA(x)
#define	DMA_DCHPRI31_ECP_MASK (0x80U)
#define	DMA_DCHPRI31_ECP_SHIFT (7U)
#define	DMA_DCHPRI31_ECP(x)
#define	DMA_DCHPRI31_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI31_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI31_CHPRI(x)
#define	DMA_DCHPRI31_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI31_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI31_GRPPRI(x)
#define	DMA_DCHPRI31_DPA_MASK (0x40U)
#define	DMA_DCHPRI31_DPA_SHIFT (6U)
#define	DMA_DCHPRI31_DPA(x)
#define	DMA_DCHPRI31_ECP_MASK (0x80U)
#define	DMA_DCHPRI31_ECP_SHIFT (7U)
#define	DMA_DCHPRI31_ECP(x)
#define	DMA_DCHPRI31_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI31_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI31_CHPRI(x)
#define	DMA_DCHPRI31_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI31_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI31_GRPPRI(x)
#define	DMA_DCHPRI31_DPA_MASK (0x40U)
#define	DMA_DCHPRI31_DPA_SHIFT (6U)
#define	DMA_DCHPRI31_DPA(x)
#define	DMA_DCHPRI31_ECP_MASK (0x80U)
#define	DMA_DCHPRI31_ECP_SHIFT (7U)
#define	DMA_DCHPRI31_ECP(x)

DCHPRI30 - Channel Priority
#define	DMA_DCHPRI30_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI30_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI30_CHPRI(x)
#define	DMA_DCHPRI30_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI30_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI30_GRPPRI(x)
#define	DMA_DCHPRI30_DPA_MASK (0x40U)
#define	DMA_DCHPRI30_DPA_SHIFT (6U)
#define	DMA_DCHPRI30_DPA(x)
#define	DMA_DCHPRI30_ECP_MASK (0x80U)
#define	DMA_DCHPRI30_ECP_SHIFT (7U)
#define	DMA_DCHPRI30_ECP(x)
#define	DMA_DCHPRI30_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI30_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI30_CHPRI(x)
#define	DMA_DCHPRI30_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI30_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI30_GRPPRI(x)
#define	DMA_DCHPRI30_DPA_MASK (0x40U)
#define	DMA_DCHPRI30_DPA_SHIFT (6U)
#define	DMA_DCHPRI30_DPA(x)
#define	DMA_DCHPRI30_ECP_MASK (0x80U)
#define	DMA_DCHPRI30_ECP_SHIFT (7U)
#define	DMA_DCHPRI30_ECP(x)
#define	DMA_DCHPRI30_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI30_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI30_CHPRI(x)
#define	DMA_DCHPRI30_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI30_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI30_GRPPRI(x)
#define	DMA_DCHPRI30_DPA_MASK (0x40U)
#define	DMA_DCHPRI30_DPA_SHIFT (6U)
#define	DMA_DCHPRI30_DPA(x)
#define	DMA_DCHPRI30_ECP_MASK (0x80U)
#define	DMA_DCHPRI30_ECP_SHIFT (7U)
#define	DMA_DCHPRI30_ECP(x)

DCHPRI29 - Channel Priority
#define	DMA_DCHPRI29_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI29_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI29_CHPRI(x)
#define	DMA_DCHPRI29_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI29_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI29_GRPPRI(x)
#define	DMA_DCHPRI29_DPA_MASK (0x40U)
#define	DMA_DCHPRI29_DPA_SHIFT (6U)
#define	DMA_DCHPRI29_DPA(x)
#define	DMA_DCHPRI29_ECP_MASK (0x80U)
#define	DMA_DCHPRI29_ECP_SHIFT (7U)
#define	DMA_DCHPRI29_ECP(x)
#define	DMA_DCHPRI29_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI29_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI29_CHPRI(x)
#define	DMA_DCHPRI29_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI29_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI29_GRPPRI(x)
#define	DMA_DCHPRI29_DPA_MASK (0x40U)
#define	DMA_DCHPRI29_DPA_SHIFT (6U)
#define	DMA_DCHPRI29_DPA(x)
#define	DMA_DCHPRI29_ECP_MASK (0x80U)
#define	DMA_DCHPRI29_ECP_SHIFT (7U)
#define	DMA_DCHPRI29_ECP(x)
#define	DMA_DCHPRI29_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI29_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI29_CHPRI(x)
#define	DMA_DCHPRI29_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI29_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI29_GRPPRI(x)
#define	DMA_DCHPRI29_DPA_MASK (0x40U)
#define	DMA_DCHPRI29_DPA_SHIFT (6U)
#define	DMA_DCHPRI29_DPA(x)
#define	DMA_DCHPRI29_ECP_MASK (0x80U)
#define	DMA_DCHPRI29_ECP_SHIFT (7U)
#define	DMA_DCHPRI29_ECP(x)

DCHPRI28 - Channel Priority
#define	DMA_DCHPRI28_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI28_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI28_CHPRI(x)
#define	DMA_DCHPRI28_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI28_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI28_GRPPRI(x)
#define	DMA_DCHPRI28_DPA_MASK (0x40U)
#define	DMA_DCHPRI28_DPA_SHIFT (6U)
#define	DMA_DCHPRI28_DPA(x)
#define	DMA_DCHPRI28_ECP_MASK (0x80U)
#define	DMA_DCHPRI28_ECP_SHIFT (7U)
#define	DMA_DCHPRI28_ECP(x)
#define	DMA_DCHPRI28_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI28_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI28_CHPRI(x)
#define	DMA_DCHPRI28_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI28_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI28_GRPPRI(x)
#define	DMA_DCHPRI28_DPA_MASK (0x40U)
#define	DMA_DCHPRI28_DPA_SHIFT (6U)
#define	DMA_DCHPRI28_DPA(x)
#define	DMA_DCHPRI28_ECP_MASK (0x80U)
#define	DMA_DCHPRI28_ECP_SHIFT (7U)
#define	DMA_DCHPRI28_ECP(x)
#define	DMA_DCHPRI28_CHPRI_MASK (0xFU)
#define	DMA_DCHPRI28_CHPRI_SHIFT (0U)
#define	DMA_DCHPRI28_CHPRI(x)
#define	DMA_DCHPRI28_GRPPRI_MASK (0x30U)
#define	DMA_DCHPRI28_GRPPRI_SHIFT (4U)
#define	DMA_DCHPRI28_GRPPRI(x)
#define	DMA_DCHPRI28_DPA_MASK (0x40U)
#define	DMA_DCHPRI28_DPA_SHIFT (6U)
#define	DMA_DCHPRI28_DPA(x)
#define	DMA_DCHPRI28_ECP_MASK (0x80U)
#define	DMA_DCHPRI28_ECP_SHIFT (7U)
#define	DMA_DCHPRI28_ECP(x)

SADDR - TCD Source Address
#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define	DMA_SADDR_SADDR_SHIFT (0U)
#define	DMA_SADDR_SADDR(x)
#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define	DMA_SADDR_SADDR_SHIFT (0U)
#define	DMA_SADDR_SADDR(x)
#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define	DMA_SADDR_SADDR_SHIFT (0U)
#define	DMA_SADDR_SADDR(x)

SOFF - TCD Signed Source Address Offset
#define	DMA_SOFF_SOFF_MASK (0xFFFFU)
#define	DMA_SOFF_SOFF_SHIFT (0U)
#define	DMA_SOFF_SOFF(x)
#define	DMA_SOFF_SOFF_MASK (0xFFFFU)
#define	DMA_SOFF_SOFF_SHIFT (0U)
#define	DMA_SOFF_SOFF(x)
#define	DMA_SOFF_SOFF_MASK (0xFFFFU)
#define	DMA_SOFF_SOFF_SHIFT (0U)
#define	DMA_SOFF_SOFF(x)

ATTR - TCD Transfer Attributes
#define	DMA_ATTR_DSIZE_MASK (0x7U)
#define	DMA_ATTR_DSIZE_SHIFT (0U)
#define	DMA_ATTR_DSIZE(x)
#define	DMA_ATTR_DMOD_MASK (0xF8U)
#define	DMA_ATTR_DMOD_SHIFT (3U)
#define	DMA_ATTR_DMOD(x)
#define	DMA_ATTR_SSIZE_MASK (0x700U)
#define	DMA_ATTR_SSIZE_SHIFT (8U)
#define	DMA_ATTR_SSIZE(x)
#define	DMA_ATTR_SMOD_MASK (0xF800U)
#define	DMA_ATTR_SMOD_SHIFT (11U)
#define	DMA_ATTR_SMOD(x)
#define	DMA_ATTR_DSIZE_MASK (0x7U)
#define	DMA_ATTR_DSIZE_SHIFT (0U)
#define	DMA_ATTR_DSIZE(x)
#define	DMA_ATTR_DMOD_MASK (0xF8U)
#define	DMA_ATTR_DMOD_SHIFT (3U)
#define	DMA_ATTR_DMOD(x)
#define	DMA_ATTR_SSIZE_MASK (0x700U)
#define	DMA_ATTR_SSIZE_SHIFT (8U)
#define	DMA_ATTR_SSIZE(x)
#define	DMA_ATTR_SMOD_MASK (0xF800U)
#define	DMA_ATTR_SMOD_SHIFT (11U)
#define	DMA_ATTR_SMOD(x)
#define	DMA_ATTR_DSIZE_MASK (0x7U)
#define	DMA_ATTR_DSIZE_SHIFT (0U)
#define	DMA_ATTR_DSIZE(x)
#define	DMA_ATTR_DMOD_MASK (0xF8U)
#define	DMA_ATTR_DMOD_SHIFT (3U)
#define	DMA_ATTR_DMOD(x)
#define	DMA_ATTR_SSIZE_MASK (0x700U)
#define	DMA_ATTR_SSIZE_SHIFT (8U)
#define	DMA_ATTR_SSIZE(x)
#define	DMA_ATTR_SMOD_MASK (0xF800U)
#define	DMA_ATTR_SMOD_SHIFT (11U)
#define	DMA_ATTR_SMOD(x)

NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)
#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLNO_NBYTES(x)
#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLNO_NBYTES(x)
#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLNO_NBYTES(x)

NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLOFFNO_NBYTES(x)
#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
#define	DMA_NBYTES_MLOFFNO_DMLOE(x)
#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
#define	DMA_NBYTES_MLOFFNO_SMLOE(x)
#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLOFFNO_NBYTES(x)
#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
#define	DMA_NBYTES_MLOFFNO_DMLOE(x)
#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
#define	DMA_NBYTES_MLOFFNO_SMLOE(x)
#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLOFFNO_NBYTES(x)
#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
#define	DMA_NBYTES_MLOFFNO_DMLOE(x)
#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
#define	DMA_NBYTES_MLOFFNO_SMLOE(x)

NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLOFFYES_NBYTES(x)
#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
#define	DMA_NBYTES_MLOFFYES_MLOFF(x)
#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
#define	DMA_NBYTES_MLOFFYES_DMLOE(x)
#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
#define	DMA_NBYTES_MLOFFYES_SMLOE(x)
#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLOFFYES_NBYTES(x)
#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
#define	DMA_NBYTES_MLOFFYES_MLOFF(x)
#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
#define	DMA_NBYTES_MLOFFYES_DMLOE(x)
#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
#define	DMA_NBYTES_MLOFFYES_SMLOE(x)
#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
#define	DMA_NBYTES_MLOFFYES_NBYTES(x)
#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
#define	DMA_NBYTES_MLOFFYES_MLOFF(x)
#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
#define	DMA_NBYTES_MLOFFYES_DMLOE(x)
#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
#define	DMA_NBYTES_MLOFFYES_SMLOE(x)

SLAST - TCD Last Source Address Adjustment
#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
#define	DMA_SLAST_SLAST_SHIFT (0U)
#define	DMA_SLAST_SLAST(x)
#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
#define	DMA_SLAST_SLAST_SHIFT (0U)
#define	DMA_SLAST_SLAST(x)
#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
#define	DMA_SLAST_SLAST_SHIFT (0U)
#define	DMA_SLAST_SLAST(x)

DADDR - TCD Destination Address
#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define	DMA_DADDR_DADDR_SHIFT (0U)
#define	DMA_DADDR_DADDR(x)
#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define	DMA_DADDR_DADDR_SHIFT (0U)
#define	DMA_DADDR_DADDR(x)
#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define	DMA_DADDR_DADDR_SHIFT (0U)
#define	DMA_DADDR_DADDR(x)

DOFF - TCD Signed Destination Address Offset
#define	DMA_DOFF_DOFF_MASK (0xFFFFU)
#define	DMA_DOFF_DOFF_SHIFT (0U)
#define	DMA_DOFF_DOFF(x)
#define	DMA_DOFF_DOFF_MASK (0xFFFFU)
#define	DMA_DOFF_DOFF_SHIFT (0U)
#define	DMA_DOFF_DOFF(x)
#define	DMA_DOFF_DOFF_MASK (0xFFFFU)
#define	DMA_DOFF_DOFF_SHIFT (0U)
#define	DMA_DOFF_DOFF(x)

CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)
#define	DMA_CITER_ELINKNO_CITER(x)
#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
#define	DMA_CITER_ELINKNO_ELINK(x)
#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)
#define	DMA_CITER_ELINKNO_CITER(x)
#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
#define	DMA_CITER_ELINKNO_ELINK(x)
#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)
#define	DMA_CITER_ELINKNO_CITER(x)
#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
#define	DMA_CITER_ELINKNO_ELINK(x)

CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)
#define	DMA_CITER_ELINKYES_CITER(x)
#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
#define	DMA_CITER_ELINKYES_LINKCH(x)
#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
#define	DMA_CITER_ELINKYES_ELINK(x)
#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)
#define	DMA_CITER_ELINKYES_CITER(x)
#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
#define	DMA_CITER_ELINKYES_LINKCH(x)
#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
#define	DMA_CITER_ELINKYES_ELINK(x)
#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)
#define	DMA_CITER_ELINKYES_CITER(x)
#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
#define	DMA_CITER_ELINKYES_LINKCH(x)
#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
#define	DMA_CITER_ELINKYES_ELINK(x)

DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
#define	DMA_DLAST_SGA_DLASTSGA(x)
#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
#define	DMA_DLAST_SGA_DLASTSGA(x)
#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
#define	DMA_DLAST_SGA_DLASTSGA(x)

CSR - TCD Control and Status
#define	DMA_CSR_START_MASK (0x1U)
#define	DMA_CSR_START_SHIFT (0U)
#define	DMA_CSR_START(x)
#define	DMA_CSR_INTMAJOR_MASK (0x2U)
#define	DMA_CSR_INTMAJOR_SHIFT (1U)
#define	DMA_CSR_INTMAJOR(x)
#define	DMA_CSR_INTHALF_MASK (0x4U)
#define	DMA_CSR_INTHALF_SHIFT (2U)
#define	DMA_CSR_INTHALF(x)
#define	DMA_CSR_DREQ_MASK (0x8U)
#define	DMA_CSR_DREQ_SHIFT (3U)
#define	DMA_CSR_DREQ(x)
#define	DMA_CSR_ESG_MASK (0x10U)
#define	DMA_CSR_ESG_SHIFT (4U)
#define	DMA_CSR_ESG(x)
#define	DMA_CSR_MAJORELINK_MASK (0x20U)
#define	DMA_CSR_MAJORELINK_SHIFT (5U)
#define	DMA_CSR_MAJORELINK(x)
#define	DMA_CSR_ACTIVE_MASK (0x40U)
#define	DMA_CSR_ACTIVE_SHIFT (6U)
#define	DMA_CSR_ACTIVE(x)
#define	DMA_CSR_DONE_MASK (0x80U)
#define	DMA_CSR_DONE_SHIFT (7U)
#define	DMA_CSR_DONE(x)
#define	DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)
#define	DMA_CSR_MAJORLINKCH(x)
#define	DMA_CSR_BWC_MASK (0xC000U)
#define	DMA_CSR_BWC_SHIFT (14U)
#define	DMA_CSR_BWC(x)
#define	DMA_CSR_START_MASK (0x1U)
#define	DMA_CSR_START_SHIFT (0U)
#define	DMA_CSR_START(x)
#define	DMA_CSR_INTMAJOR_MASK (0x2U)
#define	DMA_CSR_INTMAJOR_SHIFT (1U)
#define	DMA_CSR_INTMAJOR(x)
#define	DMA_CSR_INTHALF_MASK (0x4U)
#define	DMA_CSR_INTHALF_SHIFT (2U)
#define	DMA_CSR_INTHALF(x)
#define	DMA_CSR_DREQ_MASK (0x8U)
#define	DMA_CSR_DREQ_SHIFT (3U)
#define	DMA_CSR_DREQ(x)
#define	DMA_CSR_ESG_MASK (0x10U)
#define	DMA_CSR_ESG_SHIFT (4U)
#define	DMA_CSR_ESG(x)
#define	DMA_CSR_MAJORELINK_MASK (0x20U)
#define	DMA_CSR_MAJORELINK_SHIFT (5U)
#define	DMA_CSR_MAJORELINK(x)
#define	DMA_CSR_ACTIVE_MASK (0x40U)
#define	DMA_CSR_ACTIVE_SHIFT (6U)
#define	DMA_CSR_ACTIVE(x)
#define	DMA_CSR_DONE_MASK (0x80U)
#define	DMA_CSR_DONE_SHIFT (7U)
#define	DMA_CSR_DONE(x)
#define	DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)
#define	DMA_CSR_MAJORLINKCH(x)
#define	DMA_CSR_BWC_MASK (0xC000U)
#define	DMA_CSR_BWC_SHIFT (14U)
#define	DMA_CSR_BWC(x)
#define	DMA_CSR_START_MASK (0x1U)
#define	DMA_CSR_START_SHIFT (0U)
#define	DMA_CSR_START(x)
#define	DMA_CSR_INTMAJOR_MASK (0x2U)
#define	DMA_CSR_INTMAJOR_SHIFT (1U)
#define	DMA_CSR_INTMAJOR(x)
#define	DMA_CSR_INTHALF_MASK (0x4U)
#define	DMA_CSR_INTHALF_SHIFT (2U)
#define	DMA_CSR_INTHALF(x)
#define	DMA_CSR_DREQ_MASK (0x8U)
#define	DMA_CSR_DREQ_SHIFT (3U)
#define	DMA_CSR_DREQ(x)
#define	DMA_CSR_ESG_MASK (0x10U)
#define	DMA_CSR_ESG_SHIFT (4U)
#define	DMA_CSR_ESG(x)
#define	DMA_CSR_MAJORELINK_MASK (0x20U)
#define	DMA_CSR_MAJORELINK_SHIFT (5U)
#define	DMA_CSR_MAJORELINK(x)
#define	DMA_CSR_ACTIVE_MASK (0x40U)
#define	DMA_CSR_ACTIVE_SHIFT (6U)
#define	DMA_CSR_ACTIVE(x)
#define	DMA_CSR_DONE_MASK (0x80U)
#define	DMA_CSR_DONE_SHIFT (7U)
#define	DMA_CSR_DONE(x)
#define	DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)
#define	DMA_CSR_MAJORLINKCH(x)
#define	DMA_CSR_BWC_MASK (0xC000U)
#define	DMA_CSR_BWC_SHIFT (14U)
#define	DMA_CSR_BWC(x)

BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)
#define	DMA_BITER_ELINKNO_BITER(x)
#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
#define	DMA_BITER_ELINKNO_ELINK(x)
#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)
#define	DMA_BITER_ELINKNO_BITER(x)
#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
#define	DMA_BITER_ELINKNO_ELINK(x)
#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)
#define	DMA_BITER_ELINKNO_BITER(x)
#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
#define	DMA_BITER_ELINKNO_ELINK(x)

BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)
#define	DMA_BITER_ELINKYES_BITER(x)
#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
#define	DMA_BITER_ELINKYES_LINKCH(x)
#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
#define	DMA_BITER_ELINKYES_ELINK(x)
#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)
#define	DMA_BITER_ELINKYES_BITER(x)
#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
#define	DMA_BITER_ELINKYES_LINKCH(x)
#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
#define	DMA_BITER_ELINKYES_ELINK(x)
#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)
#define	DMA_BITER_ELINKYES_BITER(x)
#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
#define	DMA_BITER_ELINKYES_LINKCH(x)
#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
#define	DMA_BITER_ELINKYES_ELINK(x)

Detailed Description

Macro Definition Documentation

◆ DMA_ATTR_DMOD [1/3]

#define DMA_ATTR_DMOD ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

DMOD - Destination Address Modulo

◆ DMA_ATTR_DMOD [2/3]

#define DMA_ATTR_DMOD ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

DMOD - Destination Address Modulo

◆ DMA_ATTR_DMOD [3/3]

#define DMA_ATTR_DMOD ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

DMOD - Destination Address Modulo

◆ DMA_ATTR_DSIZE [1/3]

#define DMA_ATTR_DSIZE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

DSIZE - Destination data transfer size

◆ DMA_ATTR_DSIZE [2/3]

#define DMA_ATTR_DSIZE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

DSIZE - Destination data transfer size

◆ DMA_ATTR_DSIZE [3/3]

#define DMA_ATTR_DSIZE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

DSIZE - Destination data transfer size

◆ DMA_ATTR_SMOD [1/3]

#define DMA_ATTR_SMOD ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled 0b00001-0b11111..Value defines address range used to set up circular data queue

◆ DMA_ATTR_SMOD [2/3]

#define DMA_ATTR_SMOD ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled 0b00001-0b11111..Value defines address range used to set up circular data queue

◆ DMA_ATTR_SMOD [3/3]

#define DMA_ATTR_SMOD ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled 0b00001-0b11111..Value defines address range used to set up circular data queue

◆ DMA_ATTR_SSIZE [1/3]

#define DMA_ATTR_SSIZE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..64-bit 0b100..Reserved 0b101..32-byte burst (4 beats of 64 bits) 0b110..Reserved 0b111..Reserved

◆ DMA_ATTR_SSIZE [2/3]

#define DMA_ATTR_SSIZE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..64-bit 0b100..Reserved 0b101..32-byte burst (4 beats of 64 bits) 0b110..Reserved 0b111..Reserved

◆ DMA_ATTR_SSIZE [3/3]

#define DMA_ATTR_SSIZE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..64-bit 0b100..Reserved 0b101..32-byte burst (4 beats of 64 bits) 0b110..Reserved 0b111..Reserved

◆ DMA_BITER_ELINKNO_BITER [1/3]

#define DMA_BITER_ELINKNO_BITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

BITER - Starting Major Iteration Count

◆ DMA_BITER_ELINKNO_BITER [2/3]

#define DMA_BITER_ELINKNO_BITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

BITER - Starting Major Iteration Count

◆ DMA_BITER_ELINKNO_BITER [3/3]

#define DMA_BITER_ELINKNO_BITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

BITER - Starting Major Iteration Count

◆ DMA_BITER_ELINKNO_ELINK [1/3]

#define DMA_BITER_ELINKNO_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_BITER_ELINKNO_ELINK [2/3]

#define DMA_BITER_ELINKNO_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_BITER_ELINKNO_ELINK [3/3]

#define DMA_BITER_ELINKNO_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_BITER [1/3]

#define DMA_BITER_ELINKYES_BITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

BITER - Starting major iteration count

◆ DMA_BITER_ELINKYES_BITER [2/3]

#define DMA_BITER_ELINKYES_BITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

BITER - Starting major iteration count

◆ DMA_BITER_ELINKYES_BITER [3/3]

#define DMA_BITER_ELINKYES_BITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

BITER - Starting major iteration count

◆ DMA_BITER_ELINKYES_ELINK [1/3]

#define DMA_BITER_ELINKYES_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_ELINK [2/3]

#define DMA_BITER_ELINKYES_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_ELINK [3/3]

#define DMA_BITER_ELINKYES_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_LINKCH [1/3]

#define DMA_BITER_ELINKYES_LINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

LINKCH - Link Channel Number

◆ DMA_BITER_ELINKYES_LINKCH [2/3]

#define DMA_BITER_ELINKYES_LINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

LINKCH - Link Channel Number

◆ DMA_BITER_ELINKYES_LINKCH [3/3]

#define DMA_BITER_ELINKYES_LINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

LINKCH - Link Channel Number

◆ DMA_CDNE_CADN [1/3]

#define DMA_CDNE_CADN ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE fields 0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field 0b1..Writes 0 to all bits in TCDn_CSR[DONE]

◆ DMA_CDNE_CADN [2/3]

#define DMA_CDNE_CADN ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE fields 0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field 0b1..Writes 0 to all bits in TCDn_CSR[DONE]

◆ DMA_CDNE_CADN [3/3]

#define DMA_CDNE_CADN ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE fields 0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field 0b1..Writes 0 to all bits in TCDn_CSR[DONE]

◆ DMA_CDNE_CDNE [1/3]

#define DMA_CDNE_CDNE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

CDNE - Clear DONE field

◆ DMA_CDNE_CDNE [2/3]

#define DMA_CDNE_CDNE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

CDNE - Clear DONE field

◆ DMA_CDNE_CDNE [3/3]

#define DMA_CDNE_CDNE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

CDNE - Clear DONE field

◆ DMA_CDNE_NOP [1/3]

#define DMA_CDNE_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CDNE_NOP [2/3]

#define DMA_CDNE_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CDNE_NOP [3/3]

#define DMA_CDNE_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CEEI_CAEE [1/3]

#define DMA_CEEI_CAEE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Write 0 only to the EEI field specified in the CEEI field 0b1..Write 0 to all fields in EEI

◆ DMA_CEEI_CAEE [2/3]

#define DMA_CEEI_CAEE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Write 0 only to the EEI field specified in the CEEI field 0b1..Write 0 to all fields in EEI

◆ DMA_CEEI_CAEE [3/3]

#define DMA_CEEI_CAEE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Write 0 only to the EEI field specified in the CEEI field 0b1..Write 0 to all fields in EEI

◆ DMA_CEEI_CEEI [1/3]

#define DMA_CEEI_CEEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

CEEI - Clear Enable Error Interrupt

◆ DMA_CEEI_CEEI [2/3]

#define DMA_CEEI_CEEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

CEEI - Clear Enable Error Interrupt

◆ DMA_CEEI_CEEI [3/3]

#define DMA_CEEI_CEEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

CEEI - Clear Enable Error Interrupt

◆ DMA_CEEI_NOP [1/3]

#define DMA_CEEI_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_CEEI_NOP [2/3]

#define DMA_CEEI_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_CEEI_NOP [3/3]

#define DMA_CEEI_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_CERQ_CAER [1/3]

#define DMA_CERQ_CAER ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Write 0 to only the ERQ field specified in the CERQ field 0b1..Write 0 to all fields in ERQ

◆ DMA_CERQ_CAER [2/3]

#define DMA_CERQ_CAER ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Write 0 to only the ERQ field specified in the CERQ field 0b1..Write 0 to all fields in ERQ

◆ DMA_CERQ_CAER [3/3]

#define DMA_CERQ_CAER ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Write 0 to only the ERQ field specified in the CERQ field 0b1..Write 0 to all fields in ERQ

◆ DMA_CERQ_CERQ [1/3]

#define DMA_CERQ_CERQ ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

CERQ - Clear Enable Request

◆ DMA_CERQ_CERQ [2/3]

#define DMA_CERQ_CERQ ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

CERQ - Clear Enable Request

◆ DMA_CERQ_CERQ [3/3]

#define DMA_CERQ_CERQ ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

CERQ - Clear Enable Request

◆ DMA_CERQ_NOP [1/3]

#define DMA_CERQ_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_CERQ_NOP [2/3]

#define DMA_CERQ_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_CERQ_NOP [3/3]

#define DMA_CERQ_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_CERR_CAEI [1/3]

#define DMA_CERR_CAEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Write 0 to only the ERR field specified in the CERR field 0b1..Write 0 to all fields in ERR

◆ DMA_CERR_CAEI [2/3]

#define DMA_CERR_CAEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Write 0 to only the ERR field specified in the CERR field 0b1..Write 0 to all fields in ERR

◆ DMA_CERR_CAEI [3/3]

#define DMA_CERR_CAEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Write 0 to only the ERR field specified in the CERR field 0b1..Write 0 to all fields in ERR

◆ DMA_CERR_CERR [1/3]

#define DMA_CERR_CERR ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

CERR - Clear Error Indicator

◆ DMA_CERR_CERR [2/3]

#define DMA_CERR_CERR ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

CERR - Clear Error Indicator

◆ DMA_CERR_CERR [3/3]

#define DMA_CERR_CERR ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

CERR - Clear Error Indicator

◆ DMA_CERR_NOP [1/3]

#define DMA_CERR_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CERR_NOP [2/3]

#define DMA_CERR_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CERR_NOP [3/3]

#define DMA_CERR_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CINT_CAIR [1/3]

#define DMA_CINT_CAIR ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT field specified in the CINT field 0b1..Clear all bits in INT

◆ DMA_CINT_CAIR [2/3]

#define DMA_CINT_CAIR ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT field specified in the CINT field 0b1..Clear all bits in INT

◆ DMA_CINT_CAIR [3/3]

#define DMA_CINT_CAIR ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT field specified in the CINT field 0b1..Clear all bits in INT

◆ DMA_CINT_CINT [1/3]

#define DMA_CINT_CINT ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

CINT - Clear Interrupt Request

◆ DMA_CINT_CINT [2/3]

#define DMA_CINT_CINT ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

CINT - Clear Interrupt Request

◆ DMA_CINT_CINT [3/3]

#define DMA_CINT_CINT ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

CINT - Clear Interrupt Request

◆ DMA_CINT_NOP [1/3]

#define DMA_CINT_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CINT_NOP [2/3]

#define DMA_CINT_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CINT_NOP [3/3]

#define DMA_CINT_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_CITER_ELINKNO_CITER [1/3]

#define DMA_CITER_ELINKNO_CITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

CITER - Current Major Iteration Count

◆ DMA_CITER_ELINKNO_CITER [2/3]

#define DMA_CITER_ELINKNO_CITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

CITER - Current Major Iteration Count

◆ DMA_CITER_ELINKNO_CITER [3/3]

#define DMA_CITER_ELINKNO_CITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

CITER - Current Major Iteration Count

◆ DMA_CITER_ELINKNO_ELINK [1/3]

#define DMA_CITER_ELINKNO_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CITER_ELINKNO_ELINK [2/3]

#define DMA_CITER_ELINKNO_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CITER_ELINKNO_ELINK [3/3]

#define DMA_CITER_ELINKNO_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_CITER [1/3]

#define DMA_CITER_ELINKYES_CITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

CITER - Current Major Iteration Count

◆ DMA_CITER_ELINKYES_CITER [2/3]

#define DMA_CITER_ELINKYES_CITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

CITER - Current Major Iteration Count

◆ DMA_CITER_ELINKYES_CITER [3/3]

#define DMA_CITER_ELINKYES_CITER ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

CITER - Current Major Iteration Count

◆ DMA_CITER_ELINKYES_ELINK [1/3]

#define DMA_CITER_ELINKYES_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_ELINK [2/3]

#define DMA_CITER_ELINKYES_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_ELINK [3/3]

#define DMA_CITER_ELINKYES_ELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_LINKCH [1/3]

#define DMA_CITER_ELINKYES_LINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

LINKCH - Minor Loop Link Channel Number

◆ DMA_CITER_ELINKYES_LINKCH [2/3]

#define DMA_CITER_ELINKYES_LINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

LINKCH - Minor Loop Link Channel Number

◆ DMA_CITER_ELINKYES_LINKCH [3/3]

#define DMA_CITER_ELINKYES_LINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

LINKCH - Minor Loop Link Channel Number

◆ DMA_CR_ACTIVE [1/3]

#define DMA_CR_ACTIVE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)

ACTIVE - eDMA Active Status 0b0..eDMA is idle 0b1..eDMA is executing a channel

◆ DMA_CR_ACTIVE [2/3]

#define DMA_CR_ACTIVE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)

ACTIVE - eDMA Active Status 0b0..eDMA is idle 0b1..eDMA is executing a channel

◆ DMA_CR_ACTIVE [3/3]

#define DMA_CR_ACTIVE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)

ACTIVE - eDMA Active Status 0b0..eDMA is idle 0b1..eDMA is executing a channel

◆ DMA_CR_CLM [1/3]

#define DMA_CR_CLM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..Continuous link mode is off 0b1..Continuous link mode is on

◆ DMA_CR_CLM [2/3]

#define DMA_CR_CLM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..Continuous link mode is off 0b1..Continuous link mode is on

◆ DMA_CR_CLM [3/3]

#define DMA_CR_CLM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..Continuous link mode is off 0b1..Continuous link mode is on

◆ DMA_CR_CX [1/3]

#define DMA_CR_CX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer

◆ DMA_CR_CX [2/3]

#define DMA_CR_CX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer

◆ DMA_CR_CX [3/3]

#define DMA_CR_CX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer

◆ DMA_CR_ECX [1/3]

#define DMA_CR_ECX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer

◆ DMA_CR_ECX [2/3]

#define DMA_CR_ECX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer

◆ DMA_CR_ECX [3/3]

#define DMA_CR_ECX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer

◆ DMA_CR_EDBG [1/3]

#define DMA_CR_EDBG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When the chip is in Debug mode, the eDMA continues to operate. 0b1..Entry of the chip into Debug mode is effective

EDBG - Enable Debug 0b0..When the chip is in Debug mode, the eDMA continues to operate. 0b1..When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete.

◆ DMA_CR_EDBG [2/3]

#define DMA_CR_EDBG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When the chip is in Debug mode, the eDMA continues to operate. 0b1..When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete.

◆ DMA_CR_EDBG [3/3]

#define DMA_CR_EDBG ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When the chip is in Debug mode, the eDMA continues to operate. 0b1..When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete.

◆ DMA_CR_EMLM [1/3]

#define DMA_CR_EMLM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled 0b1..Enabled

◆ DMA_CR_EMLM [2/3]

#define DMA_CR_EMLM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled 0b1..Enabled

◆ DMA_CR_EMLM [3/3]

#define DMA_CR_EMLM ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled 0b1..Enabled

◆ DMA_CR_ERCA [1/3]

#define DMA_CR_ERCA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration within each group 0b1..Round robin arbitration within each group

◆ DMA_CR_ERCA [2/3]

#define DMA_CR_ERCA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration within each group 0b1..Round robin arbitration within each group

◆ DMA_CR_ERCA [3/3]

#define DMA_CR_ERCA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration within each group 0b1..Round robin arbitration within each group

◆ DMA_CR_ERGA [1/3]

#define DMA_CR_ERGA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

ERGA - Enable Round Robin Group Arbitration 0b0..Fixed priority arbitration 0b1..Round robin arbitration

◆ DMA_CR_ERGA [2/3]

#define DMA_CR_ERGA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

ERGA - Enable Round Robin Group Arbitration 0b0..Fixed priority arbitration 0b1..Round robin arbitration

◆ DMA_CR_ERGA [3/3]

#define DMA_CR_ERGA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

ERGA - Enable Round Robin Group Arbitration 0b0..Fixed priority arbitration 0b1..Round robin arbitration

◆ DMA_CR_GRP0PRI [1/3]

#define DMA_CR_GRP0PRI ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

GRP0PRI - Channel Group 0 Priority

◆ DMA_CR_GRP0PRI [2/3]

#define DMA_CR_GRP0PRI ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

GRP0PRI - Channel Group 0 Priority

◆ DMA_CR_GRP0PRI [3/3]

#define DMA_CR_GRP0PRI ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

GRP0PRI - Channel Group 0 Priority

◆ DMA_CR_GRP1PRI [1/3]

#define DMA_CR_GRP1PRI ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

GRP1PRI - Channel Group 1 Priority

◆ DMA_CR_GRP1PRI [2/3]

#define DMA_CR_GRP1PRI ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

GRP1PRI - Channel Group 1 Priority

◆ DMA_CR_GRP1PRI [3/3]

#define DMA_CR_GRP1PRI ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

GRP1PRI - Channel Group 1 Priority

◆ DMA_CR_HALT [1/3]

#define DMA_CR_HALT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt eDMA Operations 0b0..Normal operation 0b1..eDMA operations halted

◆ DMA_CR_HALT [2/3]

#define DMA_CR_HALT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt eDMA Operations 0b0..Normal operation 0b1..eDMA operations halted

◆ DMA_CR_HALT [3/3]

#define DMA_CR_HALT ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt eDMA Operations 0b0..Normal operation 0b1..eDMA operations halted

◆ DMA_CR_HOE [1/3]

#define DMA_CR_HOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Error causes HALT field to be automatically set to 1

◆ DMA_CR_HOE [2/3]

#define DMA_CR_HOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Error causes HALT field to be automatically set to 1

◆ DMA_CR_HOE [3/3]

#define DMA_CR_HOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Error causes HALT field to be automatically set to 1

◆ DMA_CR_VERSION [1/3]

#define DMA_CR_VERSION ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)

VERSION - eDMA version number

◆ DMA_CR_VERSION [2/3]

#define DMA_CR_VERSION ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)

VERSION - eDMA version number

◆ DMA_CR_VERSION [3/3]

#define DMA_CR_VERSION ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)

VERSION - eDMA version number

◆ DMA_CSR_ACTIVE [1/3]

#define DMA_CSR_ACTIVE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

ACTIVE - Channel Active

◆ DMA_CSR_ACTIVE [2/3]

#define DMA_CSR_ACTIVE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

ACTIVE - Channel Active

◆ DMA_CSR_ACTIVE [3/3]

#define DMA_CSR_ACTIVE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

ACTIVE - Channel Active

◆ DMA_CSR_BWC [1/3]

#define DMA_CSR_BWC ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W 0b11..eDMA engine stalls for 8 cycles after each R/W

◆ DMA_CSR_BWC [2/3]

#define DMA_CSR_BWC ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W 0b11..eDMA engine stalls for 8 cycles after each R/W

◆ DMA_CSR_BWC [3/3]

#define DMA_CSR_BWC ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W 0b11..eDMA engine stalls for 8 cycles after each R/W

◆ DMA_CSR_DONE [1/3]

#define DMA_CSR_DONE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

DONE - Channel Done

◆ DMA_CSR_DONE [2/3]

#define DMA_CSR_DONE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

DONE - Channel Done

◆ DMA_CSR_DONE [3/3]

#define DMA_CSR_DONE ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

DONE - Channel Done

◆ DMA_CSR_DREQ [1/3]

#define DMA_CSR_DREQ ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ field is not affected 0b1..The channel's ERQ field value changes to 0 when the major loop is complete

◆ DMA_CSR_DREQ [2/3]

#define DMA_CSR_DREQ ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ field is not affected 0b1..The channel's ERQ field value changes to 0 when the major loop is complete

◆ DMA_CSR_DREQ [3/3]

#define DMA_CSR_DREQ ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ field is not affected 0b1..The channel's ERQ field value changes to 0 when the major loop is complete

◆ DMA_CSR_ESG [1/3]

#define DMA_CSR_ESG ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format 0b1..The current channel's TCD specifies a scatter gather format

◆ DMA_CSR_ESG [2/3]

#define DMA_CSR_ESG ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format 0b1..The current channel's TCD specifies a scatter gather format

◆ DMA_CSR_ESG [3/3]

#define DMA_CSR_ESG ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format 0b1..The current channel's TCD specifies a scatter gather format

◆ DMA_CSR_INTHALF [1/3]

#define DMA_CSR_INTHALF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..Half-point interrupt is disabled 0b1..Half-point interrupt is enabled

◆ DMA_CSR_INTHALF [2/3]

#define DMA_CSR_INTHALF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..Half-point interrupt is disabled 0b1..Half-point interrupt is enabled

◆ DMA_CSR_INTHALF [3/3]

#define DMA_CSR_INTHALF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..Half-point interrupt is disabled 0b1..Half-point interrupt is enabled

◆ DMA_CSR_INTMAJOR [1/3]

#define DMA_CSR_INTMAJOR ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..End of major loop interrupt is disabled 0b1..End of major loop interrupt is enabled

◆ DMA_CSR_INTMAJOR [2/3]

#define DMA_CSR_INTMAJOR ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..End of major loop interrupt is disabled 0b1..End of major loop interrupt is enabled

◆ DMA_CSR_INTMAJOR [3/3]

#define DMA_CSR_INTMAJOR ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..End of major loop interrupt is disabled 0b1..End of major loop interrupt is enabled

◆ DMA_CSR_MAJORELINK [1/3]

#define DMA_CSR_MAJORELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CSR_MAJORELINK [2/3]

#define DMA_CSR_MAJORELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CSR_MAJORELINK [3/3]

#define DMA_CSR_MAJORELINK ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..Channel-to-channel linking is disabled 0b1..Channel-to-channel linking is enabled

◆ DMA_CSR_MAJORLINKCH [1/3]

#define DMA_CSR_MAJORLINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

MAJORLINKCH - Major Loop Link Channel Number

◆ DMA_CSR_MAJORLINKCH [2/3]

#define DMA_CSR_MAJORLINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

MAJORLINKCH - Major Loop Link Channel Number

◆ DMA_CSR_MAJORLINKCH [3/3]

#define DMA_CSR_MAJORLINKCH ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

MAJORLINKCH - Major Loop Link Channel Number

◆ DMA_CSR_START [1/3]

#define DMA_CSR_START ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..Channel is not explicitly started 0b1..Channel is explicitly started via a software initiated service request

◆ DMA_CSR_START [2/3]

#define DMA_CSR_START ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..Channel is not explicitly started 0b1..Channel is explicitly started via a software initiated service request

◆ DMA_CSR_START [3/3]

#define DMA_CSR_START ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..Channel is not explicitly started 0b1..Channel is explicitly started via a software initiated service request

◆ DMA_DADDR_DADDR [1/3]

#define DMA_DADDR_DADDR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

DADDR - Destination Address

◆ DMA_DADDR_DADDR [2/3]

#define DMA_DADDR_DADDR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

DADDR - Destination Address

◆ DMA_DADDR_DADDR [3/3]

#define DMA_DADDR_DADDR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

DADDR - Destination Address

◆ DMA_DCHPRI0_CHPRI [1/3]

#define DMA_DCHPRI0_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI0_CHPRI [2/3]

#define DMA_DCHPRI0_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI0_CHPRI [3/3]

#define DMA_DCHPRI0_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI0_DPA [1/3]

#define DMA_DCHPRI0_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI0_DPA [2/3]

#define DMA_DCHPRI0_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI0_DPA [3/3]

#define DMA_DCHPRI0_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI0_ECP [1/3]

#define DMA_DCHPRI0_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI0_ECP [2/3]

#define DMA_DCHPRI0_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI0_ECP [3/3]

#define DMA_DCHPRI0_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI0_GRPPRI [1/3]

#define DMA_DCHPRI0_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI0_GRPPRI [2/3]

#define DMA_DCHPRI0_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI0_GRPPRI [3/3]

#define DMA_DCHPRI0_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI10_CHPRI [1/3]

#define DMA_DCHPRI10_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI10_CHPRI [2/3]

#define DMA_DCHPRI10_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI10_CHPRI [3/3]

#define DMA_DCHPRI10_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI10_DPA [1/3]

#define DMA_DCHPRI10_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI10_DPA [2/3]

#define DMA_DCHPRI10_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI10_DPA [3/3]

#define DMA_DCHPRI10_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI10_ECP [1/3]

#define DMA_DCHPRI10_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI10_ECP [2/3]

#define DMA_DCHPRI10_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI10_ECP [3/3]

#define DMA_DCHPRI10_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI10_GRPPRI [1/3]

#define DMA_DCHPRI10_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI10_GRPPRI [2/3]

#define DMA_DCHPRI10_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI10_GRPPRI [3/3]

#define DMA_DCHPRI10_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI11_CHPRI [1/3]

#define DMA_DCHPRI11_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI11_CHPRI [2/3]

#define DMA_DCHPRI11_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI11_CHPRI [3/3]

#define DMA_DCHPRI11_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI11_DPA [1/3]

#define DMA_DCHPRI11_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI11_DPA [2/3]

#define DMA_DCHPRI11_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI11_DPA [3/3]

#define DMA_DCHPRI11_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI11_ECP [1/3]

#define DMA_DCHPRI11_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI11_ECP [2/3]

#define DMA_DCHPRI11_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI11_ECP [3/3]

#define DMA_DCHPRI11_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI11_GRPPRI [1/3]

#define DMA_DCHPRI11_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI11_GRPPRI [2/3]

#define DMA_DCHPRI11_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI11_GRPPRI [3/3]

#define DMA_DCHPRI11_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI12_CHPRI [1/3]

#define DMA_DCHPRI12_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI12_CHPRI [2/3]

#define DMA_DCHPRI12_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI12_CHPRI [3/3]

#define DMA_DCHPRI12_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI12_DPA [1/3]

#define DMA_DCHPRI12_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI12_DPA [2/3]

#define DMA_DCHPRI12_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI12_DPA [3/3]

#define DMA_DCHPRI12_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI12_ECP [1/3]

#define DMA_DCHPRI12_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI12_ECP [2/3]

#define DMA_DCHPRI12_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI12_ECP [3/3]

#define DMA_DCHPRI12_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI12_GRPPRI [1/3]

#define DMA_DCHPRI12_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI12_GRPPRI [2/3]

#define DMA_DCHPRI12_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI12_GRPPRI [3/3]

#define DMA_DCHPRI12_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI13_CHPRI [1/3]

#define DMA_DCHPRI13_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI13_CHPRI [2/3]

#define DMA_DCHPRI13_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI13_CHPRI [3/3]

#define DMA_DCHPRI13_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI13_DPA [1/3]

#define DMA_DCHPRI13_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI13_DPA [2/3]

#define DMA_DCHPRI13_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI13_DPA [3/3]

#define DMA_DCHPRI13_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI13_ECP [1/3]

#define DMA_DCHPRI13_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI13_ECP [2/3]

#define DMA_DCHPRI13_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI13_ECP [3/3]

#define DMA_DCHPRI13_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI13_GRPPRI [1/3]

#define DMA_DCHPRI13_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI13_GRPPRI [2/3]

#define DMA_DCHPRI13_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI13_GRPPRI [3/3]

#define DMA_DCHPRI13_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI14_CHPRI [1/3]

#define DMA_DCHPRI14_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI14_CHPRI [2/3]

#define DMA_DCHPRI14_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI14_CHPRI [3/3]

#define DMA_DCHPRI14_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI14_DPA [1/3]

#define DMA_DCHPRI14_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI14_DPA [2/3]

#define DMA_DCHPRI14_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI14_DPA [3/3]

#define DMA_DCHPRI14_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI14_ECP [1/3]

#define DMA_DCHPRI14_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI14_ECP [2/3]

#define DMA_DCHPRI14_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI14_ECP [3/3]

#define DMA_DCHPRI14_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI14_GRPPRI [1/3]

#define DMA_DCHPRI14_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI14_GRPPRI [2/3]

#define DMA_DCHPRI14_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI14_GRPPRI [3/3]

#define DMA_DCHPRI14_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI15_CHPRI [1/3]

#define DMA_DCHPRI15_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI15_CHPRI [2/3]

#define DMA_DCHPRI15_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI15_CHPRI [3/3]

#define DMA_DCHPRI15_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI15_DPA [1/3]

#define DMA_DCHPRI15_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI15_DPA [2/3]

#define DMA_DCHPRI15_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI15_DPA [3/3]

#define DMA_DCHPRI15_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI15_ECP [1/3]

#define DMA_DCHPRI15_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI15_ECP [2/3]

#define DMA_DCHPRI15_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI15_ECP [3/3]

#define DMA_DCHPRI15_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI15_GRPPRI [1/3]

#define DMA_DCHPRI15_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI15_GRPPRI [2/3]

#define DMA_DCHPRI15_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI15_GRPPRI [3/3]

#define DMA_DCHPRI15_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI16_CHPRI [1/3]

#define DMA_DCHPRI16_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI16_CHPRI [2/3]

#define DMA_DCHPRI16_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI16_CHPRI [3/3]

#define DMA_DCHPRI16_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI16_DPA [1/3]

#define DMA_DCHPRI16_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI16_DPA [2/3]

#define DMA_DCHPRI16_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI16_DPA [3/3]

#define DMA_DCHPRI16_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI16_ECP [1/3]

#define DMA_DCHPRI16_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI16_ECP [2/3]

#define DMA_DCHPRI16_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI16_ECP [3/3]

#define DMA_DCHPRI16_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI16_GRPPRI [1/3]

#define DMA_DCHPRI16_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI16_GRPPRI [2/3]

#define DMA_DCHPRI16_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI16_GRPPRI [3/3]

#define DMA_DCHPRI16_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI17_CHPRI [1/3]

#define DMA_DCHPRI17_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI17_CHPRI [2/3]

#define DMA_DCHPRI17_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI17_CHPRI [3/3]

#define DMA_DCHPRI17_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI17_DPA [1/3]

#define DMA_DCHPRI17_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI17_DPA [2/3]

#define DMA_DCHPRI17_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI17_DPA [3/3]

#define DMA_DCHPRI17_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI17_ECP [1/3]

#define DMA_DCHPRI17_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI17_ECP [2/3]

#define DMA_DCHPRI17_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI17_ECP [3/3]

#define DMA_DCHPRI17_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI17_GRPPRI [1/3]

#define DMA_DCHPRI17_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI17_GRPPRI [2/3]

#define DMA_DCHPRI17_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI17_GRPPRI [3/3]

#define DMA_DCHPRI17_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI18_CHPRI [1/3]

#define DMA_DCHPRI18_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI18_CHPRI [2/3]

#define DMA_DCHPRI18_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI18_CHPRI [3/3]

#define DMA_DCHPRI18_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI18_DPA [1/3]

#define DMA_DCHPRI18_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI18_DPA [2/3]

#define DMA_DCHPRI18_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI18_DPA [3/3]

#define DMA_DCHPRI18_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI18_ECP [1/3]

#define DMA_DCHPRI18_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI18_ECP [2/3]

#define DMA_DCHPRI18_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI18_ECP [3/3]

#define DMA_DCHPRI18_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI18_GRPPRI [1/3]

#define DMA_DCHPRI18_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI18_GRPPRI [2/3]

#define DMA_DCHPRI18_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI18_GRPPRI [3/3]

#define DMA_DCHPRI18_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI19_CHPRI [1/3]

#define DMA_DCHPRI19_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI19_CHPRI [2/3]

#define DMA_DCHPRI19_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI19_CHPRI [3/3]

#define DMA_DCHPRI19_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI19_DPA [1/3]

#define DMA_DCHPRI19_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI19_DPA [2/3]

#define DMA_DCHPRI19_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI19_DPA [3/3]

#define DMA_DCHPRI19_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI19_ECP [1/3]

#define DMA_DCHPRI19_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI19_ECP [2/3]

#define DMA_DCHPRI19_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI19_ECP [3/3]

#define DMA_DCHPRI19_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI19_GRPPRI [1/3]

#define DMA_DCHPRI19_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI19_GRPPRI [2/3]

#define DMA_DCHPRI19_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI19_GRPPRI [3/3]

#define DMA_DCHPRI19_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI1_CHPRI [1/3]

#define DMA_DCHPRI1_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI1_CHPRI [2/3]

#define DMA_DCHPRI1_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI1_CHPRI [3/3]

#define DMA_DCHPRI1_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI1_DPA [1/3]

#define DMA_DCHPRI1_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI1_DPA [2/3]

#define DMA_DCHPRI1_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI1_DPA [3/3]

#define DMA_DCHPRI1_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI1_ECP [1/3]

#define DMA_DCHPRI1_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI1_ECP [2/3]

#define DMA_DCHPRI1_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI1_ECP [3/3]

#define DMA_DCHPRI1_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI1_GRPPRI [1/3]

#define DMA_DCHPRI1_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI1_GRPPRI [2/3]

#define DMA_DCHPRI1_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI1_GRPPRI [3/3]

#define DMA_DCHPRI1_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI20_CHPRI [1/3]

#define DMA_DCHPRI20_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI20_CHPRI [2/3]

#define DMA_DCHPRI20_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI20_CHPRI [3/3]

#define DMA_DCHPRI20_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI20_DPA [1/3]

#define DMA_DCHPRI20_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI20_DPA [2/3]

#define DMA_DCHPRI20_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI20_DPA [3/3]

#define DMA_DCHPRI20_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI20_ECP [1/3]

#define DMA_DCHPRI20_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI20_ECP [2/3]

#define DMA_DCHPRI20_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI20_ECP [3/3]

#define DMA_DCHPRI20_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI20_GRPPRI [1/3]

#define DMA_DCHPRI20_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI20_GRPPRI [2/3]

#define DMA_DCHPRI20_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI20_GRPPRI [3/3]

#define DMA_DCHPRI20_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI21_CHPRI [1/3]

#define DMA_DCHPRI21_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI21_CHPRI [2/3]

#define DMA_DCHPRI21_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI21_CHPRI [3/3]

#define DMA_DCHPRI21_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI21_DPA [1/3]

#define DMA_DCHPRI21_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI21_DPA [2/3]

#define DMA_DCHPRI21_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI21_DPA [3/3]

#define DMA_DCHPRI21_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI21_ECP [1/3]

#define DMA_DCHPRI21_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI21_ECP [2/3]

#define DMA_DCHPRI21_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI21_ECP [3/3]

#define DMA_DCHPRI21_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI21_GRPPRI [1/3]

#define DMA_DCHPRI21_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI21_GRPPRI [2/3]

#define DMA_DCHPRI21_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI21_GRPPRI [3/3]

#define DMA_DCHPRI21_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI22_CHPRI [1/3]

#define DMA_DCHPRI22_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI22_CHPRI [2/3]

#define DMA_DCHPRI22_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI22_CHPRI [3/3]

#define DMA_DCHPRI22_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI22_DPA [1/3]

#define DMA_DCHPRI22_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI22_DPA [2/3]

#define DMA_DCHPRI22_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI22_DPA [3/3]

#define DMA_DCHPRI22_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI22_ECP [1/3]

#define DMA_DCHPRI22_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI22_ECP [2/3]

#define DMA_DCHPRI22_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI22_ECP [3/3]

#define DMA_DCHPRI22_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI22_GRPPRI [1/3]

#define DMA_DCHPRI22_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI22_GRPPRI [2/3]

#define DMA_DCHPRI22_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI22_GRPPRI [3/3]

#define DMA_DCHPRI22_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI23_CHPRI [1/3]

#define DMA_DCHPRI23_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI23_CHPRI [2/3]

#define DMA_DCHPRI23_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI23_CHPRI [3/3]

#define DMA_DCHPRI23_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI23_DPA [1/3]

#define DMA_DCHPRI23_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI23_DPA [2/3]

#define DMA_DCHPRI23_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI23_DPA [3/3]

#define DMA_DCHPRI23_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI23_ECP [1/3]

#define DMA_DCHPRI23_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI23_ECP [2/3]

#define DMA_DCHPRI23_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI23_ECP [3/3]

#define DMA_DCHPRI23_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI23_GRPPRI [1/3]

#define DMA_DCHPRI23_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI23_GRPPRI [2/3]

#define DMA_DCHPRI23_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI23_GRPPRI [3/3]

#define DMA_DCHPRI23_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI24_CHPRI [1/3]

#define DMA_DCHPRI24_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI24_CHPRI [2/3]

#define DMA_DCHPRI24_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI24_CHPRI [3/3]

#define DMA_DCHPRI24_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI24_DPA [1/3]

#define DMA_DCHPRI24_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI24_DPA [2/3]

#define DMA_DCHPRI24_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI24_DPA [3/3]

#define DMA_DCHPRI24_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI24_ECP [1/3]

#define DMA_DCHPRI24_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI24_ECP [2/3]

#define DMA_DCHPRI24_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI24_ECP [3/3]

#define DMA_DCHPRI24_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI24_GRPPRI [1/3]

#define DMA_DCHPRI24_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI24_GRPPRI [2/3]

#define DMA_DCHPRI24_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI24_GRPPRI [3/3]

#define DMA_DCHPRI24_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI25_CHPRI [1/3]

#define DMA_DCHPRI25_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI25_CHPRI [2/3]

#define DMA_DCHPRI25_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI25_CHPRI [3/3]

#define DMA_DCHPRI25_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI25_DPA [1/3]

#define DMA_DCHPRI25_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI25_DPA [2/3]

#define DMA_DCHPRI25_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI25_DPA [3/3]

#define DMA_DCHPRI25_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI25_ECP [1/3]

#define DMA_DCHPRI25_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI25_ECP [2/3]

#define DMA_DCHPRI25_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI25_ECP [3/3]

#define DMA_DCHPRI25_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI25_GRPPRI [1/3]

#define DMA_DCHPRI25_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI25_GRPPRI [2/3]

#define DMA_DCHPRI25_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI25_GRPPRI [3/3]

#define DMA_DCHPRI25_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI26_CHPRI [1/3]

#define DMA_DCHPRI26_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI26_CHPRI [2/3]

#define DMA_DCHPRI26_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI26_CHPRI [3/3]

#define DMA_DCHPRI26_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI26_DPA [1/3]

#define DMA_DCHPRI26_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI26_DPA [2/3]

#define DMA_DCHPRI26_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI26_DPA [3/3]

#define DMA_DCHPRI26_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI26_ECP [1/3]

#define DMA_DCHPRI26_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI26_ECP [2/3]

#define DMA_DCHPRI26_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI26_ECP [3/3]

#define DMA_DCHPRI26_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI26_GRPPRI [1/3]

#define DMA_DCHPRI26_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI26_GRPPRI [2/3]

#define DMA_DCHPRI26_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI26_GRPPRI [3/3]

#define DMA_DCHPRI26_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI27_CHPRI [1/3]

#define DMA_DCHPRI27_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI27_CHPRI [2/3]

#define DMA_DCHPRI27_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI27_CHPRI [3/3]

#define DMA_DCHPRI27_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI27_DPA [1/3]

#define DMA_DCHPRI27_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI27_DPA [2/3]

#define DMA_DCHPRI27_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI27_DPA [3/3]

#define DMA_DCHPRI27_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI27_ECP [1/3]

#define DMA_DCHPRI27_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI27_ECP [2/3]

#define DMA_DCHPRI27_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI27_ECP [3/3]

#define DMA_DCHPRI27_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI27_GRPPRI [1/3]

#define DMA_DCHPRI27_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI27_GRPPRI [2/3]

#define DMA_DCHPRI27_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI27_GRPPRI [3/3]

#define DMA_DCHPRI27_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI28_CHPRI [1/3]

#define DMA_DCHPRI28_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI28_CHPRI [2/3]

#define DMA_DCHPRI28_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI28_CHPRI [3/3]

#define DMA_DCHPRI28_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI28_DPA [1/3]

#define DMA_DCHPRI28_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI28_DPA [2/3]

#define DMA_DCHPRI28_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI28_DPA [3/3]

#define DMA_DCHPRI28_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI28_ECP [1/3]

#define DMA_DCHPRI28_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI28_ECP [2/3]

#define DMA_DCHPRI28_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI28_ECP [3/3]

#define DMA_DCHPRI28_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI28_GRPPRI [1/3]

#define DMA_DCHPRI28_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI28_GRPPRI [2/3]

#define DMA_DCHPRI28_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI28_GRPPRI [3/3]

#define DMA_DCHPRI28_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI29_CHPRI [1/3]

#define DMA_DCHPRI29_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI29_CHPRI [2/3]

#define DMA_DCHPRI29_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI29_CHPRI [3/3]

#define DMA_DCHPRI29_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI29_DPA [1/3]

#define DMA_DCHPRI29_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI29_DPA [2/3]

#define DMA_DCHPRI29_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI29_DPA [3/3]

#define DMA_DCHPRI29_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI29_ECP [1/3]

#define DMA_DCHPRI29_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI29_ECP [2/3]

#define DMA_DCHPRI29_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI29_ECP [3/3]

#define DMA_DCHPRI29_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI29_GRPPRI [1/3]

#define DMA_DCHPRI29_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI29_GRPPRI [2/3]

#define DMA_DCHPRI29_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI29_GRPPRI [3/3]

#define DMA_DCHPRI29_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI2_CHPRI [1/3]

#define DMA_DCHPRI2_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI2_CHPRI [2/3]

#define DMA_DCHPRI2_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI2_CHPRI [3/3]

#define DMA_DCHPRI2_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI2_DPA [1/3]

#define DMA_DCHPRI2_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI2_DPA [2/3]

#define DMA_DCHPRI2_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI2_DPA [3/3]

#define DMA_DCHPRI2_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI2_ECP [1/3]

#define DMA_DCHPRI2_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI2_ECP [2/3]

#define DMA_DCHPRI2_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI2_ECP [3/3]

#define DMA_DCHPRI2_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI2_GRPPRI [1/3]

#define DMA_DCHPRI2_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI2_GRPPRI [2/3]

#define DMA_DCHPRI2_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI2_GRPPRI [3/3]

#define DMA_DCHPRI2_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI30_CHPRI [1/3]

#define DMA_DCHPRI30_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI30_CHPRI [2/3]

#define DMA_DCHPRI30_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI30_CHPRI [3/3]

#define DMA_DCHPRI30_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI30_DPA [1/3]

#define DMA_DCHPRI30_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI30_DPA [2/3]

#define DMA_DCHPRI30_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI30_DPA [3/3]

#define DMA_DCHPRI30_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI30_ECP [1/3]

#define DMA_DCHPRI30_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI30_ECP [2/3]

#define DMA_DCHPRI30_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI30_ECP [3/3]

#define DMA_DCHPRI30_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI30_GRPPRI [1/3]

#define DMA_DCHPRI30_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI30_GRPPRI [2/3]

#define DMA_DCHPRI30_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI30_GRPPRI [3/3]

#define DMA_DCHPRI30_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI31_CHPRI [1/3]

#define DMA_DCHPRI31_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI31_CHPRI [2/3]

#define DMA_DCHPRI31_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI31_CHPRI [3/3]

#define DMA_DCHPRI31_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI31_DPA [1/3]

#define DMA_DCHPRI31_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI31_DPA [2/3]

#define DMA_DCHPRI31_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI31_DPA [3/3]

#define DMA_DCHPRI31_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI31_ECP [1/3]

#define DMA_DCHPRI31_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI31_ECP [2/3]

#define DMA_DCHPRI31_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI31_ECP [3/3]

#define DMA_DCHPRI31_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI31_GRPPRI [1/3]

#define DMA_DCHPRI31_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI31_GRPPRI [2/3]

#define DMA_DCHPRI31_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI31_GRPPRI [3/3]

#define DMA_DCHPRI31_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI3_CHPRI [1/3]

#define DMA_DCHPRI3_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI3_CHPRI [2/3]

#define DMA_DCHPRI3_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI3_CHPRI [3/3]

#define DMA_DCHPRI3_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI3_DPA [1/3]

#define DMA_DCHPRI3_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI3_DPA [2/3]

#define DMA_DCHPRI3_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI3_DPA [3/3]

#define DMA_DCHPRI3_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI3_ECP [1/3]

#define DMA_DCHPRI3_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI3_ECP [2/3]

#define DMA_DCHPRI3_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI3_ECP [3/3]

#define DMA_DCHPRI3_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI3_GRPPRI [1/3]

#define DMA_DCHPRI3_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI3_GRPPRI [2/3]

#define DMA_DCHPRI3_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI3_GRPPRI [3/3]

#define DMA_DCHPRI3_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI4_CHPRI [1/3]

#define DMA_DCHPRI4_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI4_CHPRI [2/3]

#define DMA_DCHPRI4_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI4_CHPRI [3/3]

#define DMA_DCHPRI4_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI4_DPA [1/3]

#define DMA_DCHPRI4_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI4_DPA [2/3]

#define DMA_DCHPRI4_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI4_DPA [3/3]

#define DMA_DCHPRI4_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI4_ECP [1/3]

#define DMA_DCHPRI4_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI4_ECP [2/3]

#define DMA_DCHPRI4_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI4_ECP [3/3]

#define DMA_DCHPRI4_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI4_GRPPRI [1/3]

#define DMA_DCHPRI4_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI4_GRPPRI [2/3]

#define DMA_DCHPRI4_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI4_GRPPRI [3/3]

#define DMA_DCHPRI4_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI5_CHPRI [1/3]

#define DMA_DCHPRI5_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI5_CHPRI [2/3]

#define DMA_DCHPRI5_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI5_CHPRI [3/3]

#define DMA_DCHPRI5_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI5_DPA [1/3]

#define DMA_DCHPRI5_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI5_DPA [2/3]

#define DMA_DCHPRI5_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI5_DPA [3/3]

#define DMA_DCHPRI5_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI5_ECP [1/3]

#define DMA_DCHPRI5_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI5_ECP [2/3]

#define DMA_DCHPRI5_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI5_ECP [3/3]

#define DMA_DCHPRI5_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI5_GRPPRI [1/3]

#define DMA_DCHPRI5_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI5_GRPPRI [2/3]

#define DMA_DCHPRI5_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI5_GRPPRI [3/3]

#define DMA_DCHPRI5_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI6_CHPRI [1/3]

#define DMA_DCHPRI6_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI6_CHPRI [2/3]

#define DMA_DCHPRI6_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI6_CHPRI [3/3]

#define DMA_DCHPRI6_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI6_DPA [1/3]

#define DMA_DCHPRI6_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI6_DPA [2/3]

#define DMA_DCHPRI6_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI6_DPA [3/3]

#define DMA_DCHPRI6_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI6_ECP [1/3]

#define DMA_DCHPRI6_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI6_ECP [2/3]

#define DMA_DCHPRI6_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI6_ECP [3/3]

#define DMA_DCHPRI6_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI6_GRPPRI [1/3]

#define DMA_DCHPRI6_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI6_GRPPRI [2/3]

#define DMA_DCHPRI6_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI6_GRPPRI [3/3]

#define DMA_DCHPRI6_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI7_CHPRI [1/3]

#define DMA_DCHPRI7_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI7_CHPRI [2/3]

#define DMA_DCHPRI7_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI7_CHPRI [3/3]

#define DMA_DCHPRI7_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI7_DPA [1/3]

#define DMA_DCHPRI7_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI7_DPA [2/3]

#define DMA_DCHPRI7_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI7_DPA [3/3]

#define DMA_DCHPRI7_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI7_ECP [1/3]

#define DMA_DCHPRI7_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI7_ECP [2/3]

#define DMA_DCHPRI7_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI7_ECP [3/3]

#define DMA_DCHPRI7_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI7_GRPPRI [1/3]

#define DMA_DCHPRI7_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI7_GRPPRI [2/3]

#define DMA_DCHPRI7_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI7_GRPPRI [3/3]

#define DMA_DCHPRI7_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI8_CHPRI [1/3]

#define DMA_DCHPRI8_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI8_CHPRI [2/3]

#define DMA_DCHPRI8_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI8_CHPRI [3/3]

#define DMA_DCHPRI8_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI8_DPA [1/3]

#define DMA_DCHPRI8_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI8_DPA [2/3]

#define DMA_DCHPRI8_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI8_DPA [3/3]

#define DMA_DCHPRI8_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI8_ECP [1/3]

#define DMA_DCHPRI8_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI8_ECP [2/3]

#define DMA_DCHPRI8_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI8_ECP [3/3]

#define DMA_DCHPRI8_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI8_GRPPRI [1/3]

#define DMA_DCHPRI8_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI8_GRPPRI [2/3]

#define DMA_DCHPRI8_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI8_GRPPRI [3/3]

#define DMA_DCHPRI8_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI9_CHPRI [1/3]

#define DMA_DCHPRI9_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI9_CHPRI [2/3]

#define DMA_DCHPRI9_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI9_CHPRI [3/3]

#define DMA_DCHPRI9_CHPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

CHPRI - Channel n Arbitration Priority

◆ DMA_DCHPRI9_DPA [1/3]

#define DMA_DCHPRI9_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI9_DPA [2/3]

#define DMA_DCHPRI9_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI9_DPA [3/3]

#define DMA_DCHPRI9_DPA ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability. This field resets to 0. 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

◆ DMA_DCHPRI9_ECP [1/3]

#define DMA_DCHPRI9_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI9_ECP [2/3]

#define DMA_DCHPRI9_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI9_ECP [3/3]

#define DMA_DCHPRI9_ECP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption. This field resets to 0. 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

◆ DMA_DCHPRI9_GRPPRI [1/3]

#define DMA_DCHPRI9_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI9_GRPPRI [2/3]

#define DMA_DCHPRI9_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DCHPRI9_GRPPRI [3/3]

#define DMA_DCHPRI9_GRPPRI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

GRPPRI - Channel n Current Group Priority

◆ DMA_DLAST_SGA_DLASTSGA [1/3]

#define DMA_DLAST_SGA_DLASTSGA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather)

◆ DMA_DLAST_SGA_DLASTSGA [2/3]

#define DMA_DLAST_SGA_DLASTSGA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather)

◆ DMA_DLAST_SGA_DLASTSGA [3/3]

#define DMA_DLAST_SGA_DLASTSGA ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather)

◆ DMA_DOFF_DOFF [1/3]

#define DMA_DOFF_DOFF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

DOFF - Destination Address Signed Offset

◆ DMA_DOFF_DOFF [2/3]

#define DMA_DOFF_DOFF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

DOFF - Destination Address Signed Offset

◆ DMA_DOFF_DOFF [3/3]

#define DMA_DOFF_DOFF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

DOFF - Destination Address Signed Offset

◆ DMA_EARS_EDREQ_0 [1/3]

#define DMA_EARS_EDREQ_0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 0b0..Disable asynchronous DMA request for channel 0 0b1..Enable asynchronous DMA request for channel 0

◆ DMA_EARS_EDREQ_0 [2/3]

#define DMA_EARS_EDREQ_0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 0b0..Disable asynchronous DMA request for channel 0 0b1..Enable asynchronous DMA request for channel 0

◆ DMA_EARS_EDREQ_0 [3/3]

#define DMA_EARS_EDREQ_0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 0b0..Disable asynchronous DMA request for channel 0 0b1..Enable asynchronous DMA request for channel 0

◆ DMA_EARS_EDREQ_1 [1/3]

#define DMA_EARS_EDREQ_1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 0b0..Disable asynchronous DMA request for channel 1 0b1..Enable asynchronous DMA request for channel 1

◆ DMA_EARS_EDREQ_1 [2/3]

#define DMA_EARS_EDREQ_1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 0b0..Disable asynchronous DMA request for channel 1 0b1..Enable asynchronous DMA request for channel 1

◆ DMA_EARS_EDREQ_1 [3/3]

#define DMA_EARS_EDREQ_1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 0b0..Disable asynchronous DMA request for channel 1 0b1..Enable asynchronous DMA request for channel 1

◆ DMA_EARS_EDREQ_10 [1/3]

#define DMA_EARS_EDREQ_10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10. 0b0..Disable asynchronous DMA request for channel 10 0b1..Enable asynchronous DMA request for channel 10

◆ DMA_EARS_EDREQ_10 [2/3]

#define DMA_EARS_EDREQ_10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10. 0b0..Disable asynchronous DMA request for channel 10 0b1..Enable asynchronous DMA request for channel 10

◆ DMA_EARS_EDREQ_10 [3/3]

#define DMA_EARS_EDREQ_10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10. 0b0..Disable asynchronous DMA request for channel 10 0b1..Enable asynchronous DMA request for channel 10

◆ DMA_EARS_EDREQ_11 [1/3]

#define DMA_EARS_EDREQ_11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11. 0b0..Disable asynchronous DMA request for channel 11 0b1..Enable asynchronous DMA request for channel 11

◆ DMA_EARS_EDREQ_11 [2/3]

#define DMA_EARS_EDREQ_11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11. 0b0..Disable asynchronous DMA request for channel 11 0b1..Enable asynchronous DMA request for channel 11

◆ DMA_EARS_EDREQ_11 [3/3]

#define DMA_EARS_EDREQ_11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11. 0b0..Disable asynchronous DMA request for channel 11 0b1..Enable asynchronous DMA request for channel 11

◆ DMA_EARS_EDREQ_12 [1/3]

#define DMA_EARS_EDREQ_12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12. 0b0..Disable asynchronous DMA request for channel 12 0b1..Enable asynchronous DMA request for channel 12

◆ DMA_EARS_EDREQ_12 [2/3]

#define DMA_EARS_EDREQ_12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12. 0b0..Disable asynchronous DMA request for channel 12 0b1..Enable asynchronous DMA request for channel 12

◆ DMA_EARS_EDREQ_12 [3/3]

#define DMA_EARS_EDREQ_12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12. 0b0..Disable asynchronous DMA request for channel 12 0b1..Enable asynchronous DMA request for channel 12

◆ DMA_EARS_EDREQ_13 [1/3]

#define DMA_EARS_EDREQ_13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13. 0b0..Disable asynchronous DMA request for channel 13 0b1..Enable asynchronous DMA request for channel 13

◆ DMA_EARS_EDREQ_13 [2/3]

#define DMA_EARS_EDREQ_13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13. 0b0..Disable asynchronous DMA request for channel 13 0b1..Enable asynchronous DMA request for channel 13

◆ DMA_EARS_EDREQ_13 [3/3]

#define DMA_EARS_EDREQ_13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13. 0b0..Disable asynchronous DMA request for channel 13 0b1..Enable asynchronous DMA request for channel 13

◆ DMA_EARS_EDREQ_14 [1/3]

#define DMA_EARS_EDREQ_14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14. 0b0..Disable asynchronous DMA request for channel 14 0b1..Enable asynchronous DMA request for channel 14

◆ DMA_EARS_EDREQ_14 [2/3]

#define DMA_EARS_EDREQ_14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14. 0b0..Disable asynchronous DMA request for channel 14 0b1..Enable asynchronous DMA request for channel 14

◆ DMA_EARS_EDREQ_14 [3/3]

#define DMA_EARS_EDREQ_14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14. 0b0..Disable asynchronous DMA request for channel 14 0b1..Enable asynchronous DMA request for channel 14

◆ DMA_EARS_EDREQ_15 [1/3]

#define DMA_EARS_EDREQ_15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15. 0b0..Disable asynchronous DMA request for channel 15 0b1..Enable asynchronous DMA request for channel 15

◆ DMA_EARS_EDREQ_15 [2/3]

#define DMA_EARS_EDREQ_15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15. 0b0..Disable asynchronous DMA request for channel 15 0b1..Enable asynchronous DMA request for channel 15

◆ DMA_EARS_EDREQ_15 [3/3]

#define DMA_EARS_EDREQ_15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15. 0b0..Disable asynchronous DMA request for channel 15 0b1..Enable asynchronous DMA request for channel 15

◆ DMA_EARS_EDREQ_16 [1/3]

#define DMA_EARS_EDREQ_16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16. 0b0..Disable asynchronous DMA request for channel 16 0b1..Enable asynchronous DMA request for channel 16

◆ DMA_EARS_EDREQ_16 [2/3]

#define DMA_EARS_EDREQ_16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16. 0b0..Disable asynchronous DMA request for channel 16 0b1..Enable asynchronous DMA request for channel 16

◆ DMA_EARS_EDREQ_16 [3/3]

#define DMA_EARS_EDREQ_16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16. 0b0..Disable asynchronous DMA request for channel 16 0b1..Enable asynchronous DMA request for channel 16

◆ DMA_EARS_EDREQ_17 [1/3]

#define DMA_EARS_EDREQ_17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17. 0b0..Disable asynchronous DMA request for channel 17 0b1..Enable asynchronous DMA request for channel 17

◆ DMA_EARS_EDREQ_17 [2/3]

#define DMA_EARS_EDREQ_17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17. 0b0..Disable asynchronous DMA request for channel 17 0b1..Enable asynchronous DMA request for channel 17

◆ DMA_EARS_EDREQ_17 [3/3]

#define DMA_EARS_EDREQ_17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17. 0b0..Disable asynchronous DMA request for channel 17 0b1..Enable asynchronous DMA request for channel 17

◆ DMA_EARS_EDREQ_18 [1/3]

#define DMA_EARS_EDREQ_18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18. 0b0..Disable asynchronous DMA request for channel 18 0b1..Enable asynchronous DMA request for channel 18

◆ DMA_EARS_EDREQ_18 [2/3]

#define DMA_EARS_EDREQ_18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18. 0b0..Disable asynchronous DMA request for channel 18 0b1..Enable asynchronous DMA request for channel 18

◆ DMA_EARS_EDREQ_18 [3/3]

#define DMA_EARS_EDREQ_18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18. 0b0..Disable asynchronous DMA request for channel 18 0b1..Enable asynchronous DMA request for channel 18

◆ DMA_EARS_EDREQ_19 [1/3]

#define DMA_EARS_EDREQ_19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19. 0b0..Disable asynchronous DMA request for channel 19 0b1..Enable asynchronous DMA request for channel 19

◆ DMA_EARS_EDREQ_19 [2/3]

#define DMA_EARS_EDREQ_19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19. 0b0..Disable asynchronous DMA request for channel 19 0b1..Enable asynchronous DMA request for channel 19

◆ DMA_EARS_EDREQ_19 [3/3]

#define DMA_EARS_EDREQ_19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19. 0b0..Disable asynchronous DMA request for channel 19 0b1..Enable asynchronous DMA request for channel 19

◆ DMA_EARS_EDREQ_2 [1/3]

#define DMA_EARS_EDREQ_2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 0b0..Disable asynchronous DMA request for channel 2 0b1..Enable asynchronous DMA request for channel 2

◆ DMA_EARS_EDREQ_2 [2/3]

#define DMA_EARS_EDREQ_2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 0b0..Disable asynchronous DMA request for channel 2 0b1..Enable asynchronous DMA request for channel 2

◆ DMA_EARS_EDREQ_2 [3/3]

#define DMA_EARS_EDREQ_2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 0b0..Disable asynchronous DMA request for channel 2 0b1..Enable asynchronous DMA request for channel 2

◆ DMA_EARS_EDREQ_20 [1/3]

#define DMA_EARS_EDREQ_20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20. 0b0..Disable asynchronous DMA request for channel 20 0b1..Enable asynchronous DMA request for channel 20

◆ DMA_EARS_EDREQ_20 [2/3]

#define DMA_EARS_EDREQ_20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20. 0b0..Disable asynchronous DMA request for channel 20 0b1..Enable asynchronous DMA request for channel 20

◆ DMA_EARS_EDREQ_20 [3/3]

#define DMA_EARS_EDREQ_20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20. 0b0..Disable asynchronous DMA request for channel 20 0b1..Enable asynchronous DMA request for channel 20

◆ DMA_EARS_EDREQ_21 [1/3]

#define DMA_EARS_EDREQ_21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21. 0b0..Disable asynchronous DMA request for channel 21 0b1..Enable asynchronous DMA request for channel 21

◆ DMA_EARS_EDREQ_21 [2/3]

#define DMA_EARS_EDREQ_21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21. 0b0..Disable asynchronous DMA request for channel 21 0b1..Enable asynchronous DMA request for channel 21

◆ DMA_EARS_EDREQ_21 [3/3]

#define DMA_EARS_EDREQ_21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21. 0b0..Disable asynchronous DMA request for channel 21 0b1..Enable asynchronous DMA request for channel 21

◆ DMA_EARS_EDREQ_22 [1/3]

#define DMA_EARS_EDREQ_22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22. 0b0..Disable asynchronous DMA request for channel 22 0b1..Enable asynchronous DMA request for channel 22

◆ DMA_EARS_EDREQ_22 [2/3]

#define DMA_EARS_EDREQ_22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22. 0b0..Disable asynchronous DMA request for channel 22 0b1..Enable asynchronous DMA request for channel 22

◆ DMA_EARS_EDREQ_22 [3/3]

#define DMA_EARS_EDREQ_22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22. 0b0..Disable asynchronous DMA request for channel 22 0b1..Enable asynchronous DMA request for channel 22

◆ DMA_EARS_EDREQ_23 [1/3]

#define DMA_EARS_EDREQ_23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23. 0b0..Disable asynchronous DMA request for channel 23 0b1..Enable asynchronous DMA request for channel 23

◆ DMA_EARS_EDREQ_23 [2/3]

#define DMA_EARS_EDREQ_23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23. 0b0..Disable asynchronous DMA request for channel 23 0b1..Enable asynchronous DMA request for channel 23

◆ DMA_EARS_EDREQ_23 [3/3]

#define DMA_EARS_EDREQ_23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23. 0b0..Disable asynchronous DMA request for channel 23 0b1..Enable asynchronous DMA request for channel 23

◆ DMA_EARS_EDREQ_24 [1/3]

#define DMA_EARS_EDREQ_24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24. 0b0..Disable asynchronous DMA request for channel 24 0b1..Enable asynchronous DMA request for channel 24

◆ DMA_EARS_EDREQ_24 [2/3]

#define DMA_EARS_EDREQ_24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24. 0b0..Disable asynchronous DMA request for channel 24 0b1..Enable asynchronous DMA request for channel 24

◆ DMA_EARS_EDREQ_24 [3/3]

#define DMA_EARS_EDREQ_24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24. 0b0..Disable asynchronous DMA request for channel 24 0b1..Enable asynchronous DMA request for channel 24

◆ DMA_EARS_EDREQ_25 [1/3]

#define DMA_EARS_EDREQ_25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25. 0b0..Disable asynchronous DMA request for channel 25 0b1..Enable asynchronous DMA request for channel 25

◆ DMA_EARS_EDREQ_25 [2/3]

#define DMA_EARS_EDREQ_25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25. 0b0..Disable asynchronous DMA request for channel 25 0b1..Enable asynchronous DMA request for channel 25

◆ DMA_EARS_EDREQ_25 [3/3]

#define DMA_EARS_EDREQ_25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25. 0b0..Disable asynchronous DMA request for channel 25 0b1..Enable asynchronous DMA request for channel 25

◆ DMA_EARS_EDREQ_26 [1/3]

#define DMA_EARS_EDREQ_26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26. 0b0..Disable asynchronous DMA request for channel 26 0b1..Enable asynchronous DMA request for channel 26

◆ DMA_EARS_EDREQ_26 [2/3]

#define DMA_EARS_EDREQ_26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26. 0b0..Disable asynchronous DMA request for channel 26 0b1..Enable asynchronous DMA request for channel 26

◆ DMA_EARS_EDREQ_26 [3/3]

#define DMA_EARS_EDREQ_26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26. 0b0..Disable asynchronous DMA request for channel 26 0b1..Enable asynchronous DMA request for channel 26

◆ DMA_EARS_EDREQ_27 [1/3]

#define DMA_EARS_EDREQ_27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27. 0b0..Disable asynchronous DMA request for channel 27 0b1..Enable asynchronous DMA request for channel 27

◆ DMA_EARS_EDREQ_27 [2/3]

#define DMA_EARS_EDREQ_27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27. 0b0..Disable asynchronous DMA request for channel 27 0b1..Enable asynchronous DMA request for channel 27

◆ DMA_EARS_EDREQ_27 [3/3]

#define DMA_EARS_EDREQ_27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27. 0b0..Disable asynchronous DMA request for channel 27 0b1..Enable asynchronous DMA request for channel 27

◆ DMA_EARS_EDREQ_28 [1/3]

#define DMA_EARS_EDREQ_28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28. 0b0..Disable asynchronous DMA request for channel 28 0b1..Enable asynchronous DMA request for channel 28

◆ DMA_EARS_EDREQ_28 [2/3]

#define DMA_EARS_EDREQ_28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28. 0b0..Disable asynchronous DMA request for channel 28 0b1..Enable asynchronous DMA request for channel 28

◆ DMA_EARS_EDREQ_28 [3/3]

#define DMA_EARS_EDREQ_28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28. 0b0..Disable asynchronous DMA request for channel 28 0b1..Enable asynchronous DMA request for channel 28

◆ DMA_EARS_EDREQ_29 [1/3]

#define DMA_EARS_EDREQ_29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29. 0b0..Disable asynchronous DMA request for channel 29 0b1..Enable asynchronous DMA request for channel 29

◆ DMA_EARS_EDREQ_29 [2/3]

#define DMA_EARS_EDREQ_29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29. 0b0..Disable asynchronous DMA request for channel 29 0b1..Enable asynchronous DMA request for channel 29

◆ DMA_EARS_EDREQ_29 [3/3]

#define DMA_EARS_EDREQ_29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29. 0b0..Disable asynchronous DMA request for channel 29 0b1..Enable asynchronous DMA request for channel 29

◆ DMA_EARS_EDREQ_3 [1/3]

#define DMA_EARS_EDREQ_3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 0b0..Disable asynchronous DMA request for channel 3 0b1..Enable asynchronous DMA request for channel 3

◆ DMA_EARS_EDREQ_3 [2/3]

#define DMA_EARS_EDREQ_3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 0b0..Disable asynchronous DMA request for channel 3 0b1..Enable asynchronous DMA request for channel 3

◆ DMA_EARS_EDREQ_3 [3/3]

#define DMA_EARS_EDREQ_3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 0b0..Disable asynchronous DMA request for channel 3 0b1..Enable asynchronous DMA request for channel 3

◆ DMA_EARS_EDREQ_30 [1/3]

#define DMA_EARS_EDREQ_30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30. 0b0..Disable asynchronous DMA request for channel 30 0b1..Enable asynchronous DMA request for channel 30

◆ DMA_EARS_EDREQ_30 [2/3]

#define DMA_EARS_EDREQ_30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30. 0b0..Disable asynchronous DMA request for channel 30 0b1..Enable asynchronous DMA request for channel 30

◆ DMA_EARS_EDREQ_30 [3/3]

#define DMA_EARS_EDREQ_30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30. 0b0..Disable asynchronous DMA request for channel 30 0b1..Enable asynchronous DMA request for channel 30

◆ DMA_EARS_EDREQ_31 [1/3]

#define DMA_EARS_EDREQ_31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31. 0b0..Disable asynchronous DMA request for channel 31 0b1..Enable asynchronous DMA request for channel 31

◆ DMA_EARS_EDREQ_31 [2/3]

#define DMA_EARS_EDREQ_31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31. 0b0..Disable asynchronous DMA request for channel 31 0b1..Enable asynchronous DMA request for channel 31

◆ DMA_EARS_EDREQ_31 [3/3]

#define DMA_EARS_EDREQ_31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31. 0b0..Disable asynchronous DMA request for channel 31 0b1..Enable asynchronous DMA request for channel 31

◆ DMA_EARS_EDREQ_4 [1/3]

#define DMA_EARS_EDREQ_4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4. 0b0..Disable asynchronous DMA request for channel 4 0b1..Enable asynchronous DMA request for channel 4

◆ DMA_EARS_EDREQ_4 [2/3]

#define DMA_EARS_EDREQ_4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4. 0b0..Disable asynchronous DMA request for channel 4 0b1..Enable asynchronous DMA request for channel 4

◆ DMA_EARS_EDREQ_4 [3/3]

#define DMA_EARS_EDREQ_4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4. 0b0..Disable asynchronous DMA request for channel 4 0b1..Enable asynchronous DMA request for channel 4

◆ DMA_EARS_EDREQ_5 [1/3]

#define DMA_EARS_EDREQ_5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5. 0b0..Disable asynchronous DMA request for channel 5 0b1..Enable asynchronous DMA request for channel 5

◆ DMA_EARS_EDREQ_5 [2/3]

#define DMA_EARS_EDREQ_5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5. 0b0..Disable asynchronous DMA request for channel 5 0b1..Enable asynchronous DMA request for channel 5

◆ DMA_EARS_EDREQ_5 [3/3]

#define DMA_EARS_EDREQ_5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5. 0b0..Disable asynchronous DMA request for channel 5 0b1..Enable asynchronous DMA request for channel 5

◆ DMA_EARS_EDREQ_6 [1/3]

#define DMA_EARS_EDREQ_6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6. 0b0..Disable asynchronous DMA request for channel 6 0b1..Enable asynchronous DMA request for channel 6

◆ DMA_EARS_EDREQ_6 [2/3]

#define DMA_EARS_EDREQ_6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6. 0b0..Disable asynchronous DMA request for channel 6 0b1..Enable asynchronous DMA request for channel 6

◆ DMA_EARS_EDREQ_6 [3/3]

#define DMA_EARS_EDREQ_6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6. 0b0..Disable asynchronous DMA request for channel 6 0b1..Enable asynchronous DMA request for channel 6

◆ DMA_EARS_EDREQ_7 [1/3]

#define DMA_EARS_EDREQ_7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7. 0b0..Disable asynchronous DMA request for channel 7 0b1..Enable asynchronous DMA request for channel 7

◆ DMA_EARS_EDREQ_7 [2/3]

#define DMA_EARS_EDREQ_7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7. 0b0..Disable asynchronous DMA request for channel 7 0b1..Enable asynchronous DMA request for channel 7

◆ DMA_EARS_EDREQ_7 [3/3]

#define DMA_EARS_EDREQ_7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7. 0b0..Disable asynchronous DMA request for channel 7 0b1..Enable asynchronous DMA request for channel 7

◆ DMA_EARS_EDREQ_8 [1/3]

#define DMA_EARS_EDREQ_8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8. 0b0..Disable asynchronous DMA request for channel 8 0b1..Enable asynchronous DMA request for channel 8

◆ DMA_EARS_EDREQ_8 [2/3]

#define DMA_EARS_EDREQ_8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8. 0b0..Disable asynchronous DMA request for channel 8 0b1..Enable asynchronous DMA request for channel 8

◆ DMA_EARS_EDREQ_8 [3/3]

#define DMA_EARS_EDREQ_8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8. 0b0..Disable asynchronous DMA request for channel 8 0b1..Enable asynchronous DMA request for channel 8

◆ DMA_EARS_EDREQ_9 [1/3]

#define DMA_EARS_EDREQ_9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9. 0b0..Disable asynchronous DMA request for channel 9 0b1..Enable asynchronous DMA request for channel 9

◆ DMA_EARS_EDREQ_9 [2/3]

#define DMA_EARS_EDREQ_9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9. 0b0..Disable asynchronous DMA request for channel 9 0b1..Enable asynchronous DMA request for channel 9

◆ DMA_EARS_EDREQ_9 [3/3]

#define DMA_EARS_EDREQ_9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9. 0b0..Disable asynchronous DMA request for channel 9 0b1..Enable asynchronous DMA request for channel 9

◆ DMA_EEI_EEI0 [1/3]

#define DMA_EEI_EEI0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..An error on channel 0 does not generate an error interrupt 0b1..An error on channel 0 generates an error interrupt request

◆ DMA_EEI_EEI0 [2/3]

#define DMA_EEI_EEI0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..An error on channel 0 does not generate an error interrupt 0b1..An error on channel 0 generates an error interrupt request

◆ DMA_EEI_EEI0 [3/3]

#define DMA_EEI_EEI0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..An error on channel 0 does not generate an error interrupt 0b1..An error on channel 0 generates an error interrupt request

◆ DMA_EEI_EEI1 [1/3]

#define DMA_EEI_EEI1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..An error on channel 1 does not generate an error interrupt 0b1..An error on channel 1 generates an error interrupt request

◆ DMA_EEI_EEI1 [2/3]

#define DMA_EEI_EEI1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..An error on channel 1 does not generate an error interrupt 0b1..An error on channel 1 generates an error interrupt request

◆ DMA_EEI_EEI1 [3/3]

#define DMA_EEI_EEI1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..An error on channel 1 does not generate an error interrupt 0b1..An error on channel 1 generates an error interrupt request

◆ DMA_EEI_EEI10 [1/3]

#define DMA_EEI_EEI10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..An error on channel 10 does not generate an error interrupt 0b1..An error on channel 10 generates an error interrupt request

◆ DMA_EEI_EEI10 [2/3]

#define DMA_EEI_EEI10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..An error on channel 10 does not generate an error interrupt 0b1..An error on channel 10 generates an error interrupt request

◆ DMA_EEI_EEI10 [3/3]

#define DMA_EEI_EEI10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..An error on channel 10 does not generate an error interrupt 0b1..An error on channel 10 generates an error interrupt request

◆ DMA_EEI_EEI11 [1/3]

#define DMA_EEI_EEI11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..An error on channel 11 does not generate an error interrupt 0b1..An error on channel 11 generates an error interrupt request

◆ DMA_EEI_EEI11 [2/3]

#define DMA_EEI_EEI11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..An error on channel 11 does not generate an error interrupt 0b1..An error on channel 11 generates an error interrupt request

◆ DMA_EEI_EEI11 [3/3]

#define DMA_EEI_EEI11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..An error on channel 11 does not generate an error interrupt 0b1..An error on channel 11 generates an error interrupt request

◆ DMA_EEI_EEI12 [1/3]

#define DMA_EEI_EEI12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..An error on channel 12 does not generate an error interrupt 0b1..An error on channel 12 generates an error interrupt request

◆ DMA_EEI_EEI12 [2/3]

#define DMA_EEI_EEI12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..An error on channel 12 does not generate an error interrupt 0b1..An error on channel 12 generates an error interrupt request

◆ DMA_EEI_EEI12 [3/3]

#define DMA_EEI_EEI12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..An error on channel 12 does not generate an error interrupt 0b1..An error on channel 12 generates an error interrupt request

◆ DMA_EEI_EEI13 [1/3]

#define DMA_EEI_EEI13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..An error on channel 13 does not generate an error interrupt 0b1..An error on channel 13 generates an error interrupt request

◆ DMA_EEI_EEI13 [2/3]

#define DMA_EEI_EEI13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..An error on channel 13 does not generate an error interrupt 0b1..An error on channel 13 generates an error interrupt request

◆ DMA_EEI_EEI13 [3/3]

#define DMA_EEI_EEI13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..An error on channel 13 does not generate an error interrupt 0b1..An error on channel 13 generates an error interrupt request

◆ DMA_EEI_EEI14 [1/3]

#define DMA_EEI_EEI14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..An error on channel 14 does not generate an error interrupt 0b1..An error on channel 14 generates an error interrupt request

◆ DMA_EEI_EEI14 [2/3]

#define DMA_EEI_EEI14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..An error on channel 14 does not generate an error interrupt 0b1..An error on channel 14 generates an error interrupt request

◆ DMA_EEI_EEI14 [3/3]

#define DMA_EEI_EEI14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..An error on channel 14 does not generate an error interrupt 0b1..An error on channel 14 generates an error interrupt request

◆ DMA_EEI_EEI15 [1/3]

#define DMA_EEI_EEI15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..An error on channel 15 does not generate an error interrupt 0b1..An error on channel 15 generates an error interrupt request

◆ DMA_EEI_EEI15 [2/3]

#define DMA_EEI_EEI15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..An error on channel 15 does not generate an error interrupt 0b1..An error on channel 15 generates an error interrupt request

◆ DMA_EEI_EEI15 [3/3]

#define DMA_EEI_EEI15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..An error on channel 15 does not generate an error interrupt 0b1..An error on channel 15 generates an error interrupt request

◆ DMA_EEI_EEI16 [1/3]

#define DMA_EEI_EEI16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

EEI16 - Enable Error Interrupt 16 0b0..An error on channel 16 does not generate an error interrupt 0b1..An error on channel 16 generates an error interrupt request

◆ DMA_EEI_EEI16 [2/3]

#define DMA_EEI_EEI16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

EEI16 - Enable Error Interrupt 16 0b0..An error on channel 16 does not generate an error interrupt 0b1..An error on channel 16 generates an error interrupt request

◆ DMA_EEI_EEI16 [3/3]

#define DMA_EEI_EEI16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

EEI16 - Enable Error Interrupt 16 0b0..An error on channel 16 does not generate an error interrupt 0b1..An error on channel 16 generates an error interrupt request

◆ DMA_EEI_EEI17 [1/3]

#define DMA_EEI_EEI17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

EEI17 - Enable Error Interrupt 17 0b0..An error on channel 17 does not generate an error interrupt 0b1..An error on channel 17 generates an error interrupt request

◆ DMA_EEI_EEI17 [2/3]

#define DMA_EEI_EEI17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

EEI17 - Enable Error Interrupt 17 0b0..An error on channel 17 does not generate an error interrupt 0b1..An error on channel 17 generates an error interrupt request

◆ DMA_EEI_EEI17 [3/3]

#define DMA_EEI_EEI17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

EEI17 - Enable Error Interrupt 17 0b0..An error on channel 17 does not generate an error interrupt 0b1..An error on channel 17 generates an error interrupt request

◆ DMA_EEI_EEI18 [1/3]

#define DMA_EEI_EEI18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

EEI18 - Enable Error Interrupt 18 0b0..An error on channel 18 does not generate an error interrupt 0b1..An error on channel 18 generates an error interrupt request

◆ DMA_EEI_EEI18 [2/3]

#define DMA_EEI_EEI18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

EEI18 - Enable Error Interrupt 18 0b0..An error on channel 18 does not generate an error interrupt 0b1..An error on channel 18 generates an error interrupt request

◆ DMA_EEI_EEI18 [3/3]

#define DMA_EEI_EEI18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

EEI18 - Enable Error Interrupt 18 0b0..An error on channel 18 does not generate an error interrupt 0b1..An error on channel 18 generates an error interrupt request

◆ DMA_EEI_EEI19 [1/3]

#define DMA_EEI_EEI19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

EEI19 - Enable Error Interrupt 19 0b0..An error on channel 19 does not generate an error interrupt 0b1..An error on channel 19 generates an error interrupt request

◆ DMA_EEI_EEI19 [2/3]

#define DMA_EEI_EEI19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

EEI19 - Enable Error Interrupt 19 0b0..An error on channel 19 does not generate an error interrupt 0b1..An error on channel 19 generates an error interrupt request

◆ DMA_EEI_EEI19 [3/3]

#define DMA_EEI_EEI19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

EEI19 - Enable Error Interrupt 19 0b0..An error on channel 19 does not generate an error interrupt 0b1..An error on channel 19 generates an error interrupt request

◆ DMA_EEI_EEI2 [1/3]

#define DMA_EEI_EEI2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..An error on channel 2 does not generate an error interrupt 0b1..An error on channel 2 generates an error interrupt request

◆ DMA_EEI_EEI2 [2/3]

#define DMA_EEI_EEI2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..An error on channel 2 does not generate an error interrupt 0b1..An error on channel 2 generates an error interrupt request

◆ DMA_EEI_EEI2 [3/3]

#define DMA_EEI_EEI2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..An error on channel 2 does not generate an error interrupt 0b1..An error on channel 2 generates an error interrupt request

◆ DMA_EEI_EEI20 [1/3]

#define DMA_EEI_EEI20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

EEI20 - Enable Error Interrupt 20 0b0..An error on channel 20 does not generate an error interrupt 0b1..An error on channel 20 generates an error interrupt request

◆ DMA_EEI_EEI20 [2/3]

#define DMA_EEI_EEI20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

EEI20 - Enable Error Interrupt 20 0b0..An error on channel 20 does not generate an error interrupt 0b1..An error on channel 20 generates an error interrupt request

◆ DMA_EEI_EEI20 [3/3]

#define DMA_EEI_EEI20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

EEI20 - Enable Error Interrupt 20 0b0..An error on channel 20 does not generate an error interrupt 0b1..An error on channel 20 generates an error interrupt request

◆ DMA_EEI_EEI21 [1/3]

#define DMA_EEI_EEI21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

EEI21 - Enable Error Interrupt 21 0b0..An error on channel 21 does not generate an error interrupt 0b1..An error on channel 21 generates an error interrupt request

◆ DMA_EEI_EEI21 [2/3]

#define DMA_EEI_EEI21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

EEI21 - Enable Error Interrupt 21 0b0..An error on channel 21 does not generate an error interrupt 0b1..An error on channel 21 generates an error interrupt request

◆ DMA_EEI_EEI21 [3/3]

#define DMA_EEI_EEI21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

EEI21 - Enable Error Interrupt 21 0b0..An error on channel 21 does not generate an error interrupt 0b1..An error on channel 21 generates an error interrupt request

◆ DMA_EEI_EEI22 [1/3]

#define DMA_EEI_EEI22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

EEI22 - Enable Error Interrupt 22 0b0..An error on channel 22 does not generate an error interrupt 0b1..An error on channel 22 generates an error interrupt request

◆ DMA_EEI_EEI22 [2/3]

#define DMA_EEI_EEI22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

EEI22 - Enable Error Interrupt 22 0b0..An error on channel 22 does not generate an error interrupt 0b1..An error on channel 22 generates an error interrupt request

◆ DMA_EEI_EEI22 [3/3]

#define DMA_EEI_EEI22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

EEI22 - Enable Error Interrupt 22 0b0..An error on channel 22 does not generate an error interrupt 0b1..An error on channel 22 generates an error interrupt request

◆ DMA_EEI_EEI23 [1/3]

#define DMA_EEI_EEI23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

EEI23 - Enable Error Interrupt 23 0b0..An error on channel 23 does not generate an error interrupt 0b1..An error on channel 23 generates an error interrupt request

◆ DMA_EEI_EEI23 [2/3]

#define DMA_EEI_EEI23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

EEI23 - Enable Error Interrupt 23 0b0..An error on channel 23 does not generate an error interrupt 0b1..An error on channel 23 generates an error interrupt request

◆ DMA_EEI_EEI23 [3/3]

#define DMA_EEI_EEI23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

EEI23 - Enable Error Interrupt 23 0b0..An error on channel 23 does not generate an error interrupt 0b1..An error on channel 23 generates an error interrupt request

◆ DMA_EEI_EEI24 [1/3]

#define DMA_EEI_EEI24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

EEI24 - Enable Error Interrupt 24 0b0..An error on channel 24 does not generate an error interrupt 0b1..An error on channel 24 generates an error interrupt request

◆ DMA_EEI_EEI24 [2/3]

#define DMA_EEI_EEI24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

EEI24 - Enable Error Interrupt 24 0b0..An error on channel 24 does not generate an error interrupt 0b1..An error on channel 24 generates an error interrupt request

◆ DMA_EEI_EEI24 [3/3]

#define DMA_EEI_EEI24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

EEI24 - Enable Error Interrupt 24 0b0..An error on channel 24 does not generate an error interrupt 0b1..An error on channel 24 generates an error interrupt request

◆ DMA_EEI_EEI25 [1/3]

#define DMA_EEI_EEI25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

EEI25 - Enable Error Interrupt 25 0b0..An error on channel 25 does not generate an error interrupt 0b1..An error on channel 25 generates an error interrupt request

◆ DMA_EEI_EEI25 [2/3]

#define DMA_EEI_EEI25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

EEI25 - Enable Error Interrupt 25 0b0..An error on channel 25 does not generate an error interrupt 0b1..An error on channel 25 generates an error interrupt request

◆ DMA_EEI_EEI25 [3/3]

#define DMA_EEI_EEI25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

EEI25 - Enable Error Interrupt 25 0b0..An error on channel 25 does not generate an error interrupt 0b1..An error on channel 25 generates an error interrupt request

◆ DMA_EEI_EEI26 [1/3]

#define DMA_EEI_EEI26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

EEI26 - Enable Error Interrupt 26 0b0..An error on channel 26 does not generate an error interrupt 0b1..An error on channel 26 generates an error interrupt request

◆ DMA_EEI_EEI26 [2/3]

#define DMA_EEI_EEI26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

EEI26 - Enable Error Interrupt 26 0b0..An error on channel 26 does not generate an error interrupt 0b1..An error on channel 26 generates an error interrupt request

◆ DMA_EEI_EEI26 [3/3]

#define DMA_EEI_EEI26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

EEI26 - Enable Error Interrupt 26 0b0..An error on channel 26 does not generate an error interrupt 0b1..An error on channel 26 generates an error interrupt request

◆ DMA_EEI_EEI27 [1/3]

#define DMA_EEI_EEI27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

EEI27 - Enable Error Interrupt 27 0b0..An error on channel 27 does not generate an error interrupt 0b1..An error on channel 27 generates an error interrupt request

◆ DMA_EEI_EEI27 [2/3]

#define DMA_EEI_EEI27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

EEI27 - Enable Error Interrupt 27 0b0..An error on channel 27 does not generate an error interrupt 0b1..An error on channel 27 generates an error interrupt request

◆ DMA_EEI_EEI27 [3/3]

#define DMA_EEI_EEI27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

EEI27 - Enable Error Interrupt 27 0b0..An error on channel 27 does not generate an error interrupt 0b1..An error on channel 27 generates an error interrupt request

◆ DMA_EEI_EEI28 [1/3]

#define DMA_EEI_EEI28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

EEI28 - Enable Error Interrupt 28 0b0..An error on channel 28 does not generate an error interrupt 0b1..An error on channel 28 generates an error interrupt request

◆ DMA_EEI_EEI28 [2/3]

#define DMA_EEI_EEI28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

EEI28 - Enable Error Interrupt 28 0b0..An error on channel 28 does not generate an error interrupt 0b1..An error on channel 28 generates an error interrupt request

◆ DMA_EEI_EEI28 [3/3]

#define DMA_EEI_EEI28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

EEI28 - Enable Error Interrupt 28 0b0..An error on channel 28 does not generate an error interrupt 0b1..An error on channel 28 generates an error interrupt request

◆ DMA_EEI_EEI29 [1/3]

#define DMA_EEI_EEI29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

EEI29 - Enable Error Interrupt 29 0b0..An error on channel 29 does not generate an error interrupt 0b1..An error on channel 29 generates an error interrupt request

◆ DMA_EEI_EEI29 [2/3]

#define DMA_EEI_EEI29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

EEI29 - Enable Error Interrupt 29 0b0..An error on channel 29 does not generate an error interrupt 0b1..An error on channel 29 generates an error interrupt request

◆ DMA_EEI_EEI29 [3/3]

#define DMA_EEI_EEI29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

EEI29 - Enable Error Interrupt 29 0b0..An error on channel 29 does not generate an error interrupt 0b1..An error on channel 29 generates an error interrupt request

◆ DMA_EEI_EEI3 [1/3]

#define DMA_EEI_EEI3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..An error on channel 3 does not generate an error interrupt 0b1..An error on channel 3 generates an error interrupt request

◆ DMA_EEI_EEI3 [2/3]

#define DMA_EEI_EEI3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..An error on channel 3 does not generate an error interrupt 0b1..An error on channel 3 generates an error interrupt request

◆ DMA_EEI_EEI3 [3/3]

#define DMA_EEI_EEI3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..An error on channel 3 does not generate an error interrupt 0b1..An error on channel 3 generates an error interrupt request

◆ DMA_EEI_EEI30 [1/3]

#define DMA_EEI_EEI30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

EEI30 - Enable Error Interrupt 30 0b0..An error on channel 30 does not generate an error interrupt 0b1..An error on channel 30 generates an error interrupt request

◆ DMA_EEI_EEI30 [2/3]

#define DMA_EEI_EEI30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

EEI30 - Enable Error Interrupt 30 0b0..An error on channel 30 does not generate an error interrupt 0b1..An error on channel 30 generates an error interrupt request

◆ DMA_EEI_EEI30 [3/3]

#define DMA_EEI_EEI30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

EEI30 - Enable Error Interrupt 30 0b0..An error on channel 30 does not generate an error interrupt 0b1..An error on channel 30 generates an error interrupt request

◆ DMA_EEI_EEI31 [1/3]

#define DMA_EEI_EEI31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

EEI31 - Enable Error Interrupt 31 0b0..An error on channel 31 does not generate an error interrupt 0b1..An error on channel 31 generates an error interrupt request

◆ DMA_EEI_EEI31 [2/3]

#define DMA_EEI_EEI31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

EEI31 - Enable Error Interrupt 31 0b0..An error on channel 31 does not generate an error interrupt 0b1..An error on channel 31 generates an error interrupt request

◆ DMA_EEI_EEI31 [3/3]

#define DMA_EEI_EEI31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

EEI31 - Enable Error Interrupt 31 0b0..An error on channel 31 does not generate an error interrupt 0b1..An error on channel 31 generates an error interrupt request

◆ DMA_EEI_EEI4 [1/3]

#define DMA_EEI_EEI4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..An error on channel 4 does not generate an error interrupt 0b1..An error on channel 4 generates an error interrupt request

◆ DMA_EEI_EEI4 [2/3]

#define DMA_EEI_EEI4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..An error on channel 4 does not generate an error interrupt 0b1..An error on channel 4 generates an error interrupt request

◆ DMA_EEI_EEI4 [3/3]

#define DMA_EEI_EEI4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..An error on channel 4 does not generate an error interrupt 0b1..An error on channel 4 generates an error interrupt request

◆ DMA_EEI_EEI5 [1/3]

#define DMA_EEI_EEI5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..An error on channel 5 does not generate an error interrupt 0b1..An error on channel 5 generates an error interrupt request

◆ DMA_EEI_EEI5 [2/3]

#define DMA_EEI_EEI5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..An error on channel 5 does not generate an error interrupt 0b1..An error on channel 5 generates an error interrupt request

◆ DMA_EEI_EEI5 [3/3]

#define DMA_EEI_EEI5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..An error on channel 5 does not generate an error interrupt 0b1..An error on channel 5 generates an error interrupt request

◆ DMA_EEI_EEI6 [1/3]

#define DMA_EEI_EEI6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..An error on channel 6 does not generate an error interrupt 0b1..An error on channel 6 generates an error interrupt request

◆ DMA_EEI_EEI6 [2/3]

#define DMA_EEI_EEI6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..An error on channel 6 does not generate an error interrupt 0b1..An error on channel 6 generates an error interrupt request

◆ DMA_EEI_EEI6 [3/3]

#define DMA_EEI_EEI6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..An error on channel 6 does not generate an error interrupt 0b1..An error on channel 6 generates an error interrupt request

◆ DMA_EEI_EEI7 [1/3]

#define DMA_EEI_EEI7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..An error on channel 7 does not generate an error interrupt 0b1..An error on channel 7 generates an error interrupt request

◆ DMA_EEI_EEI7 [2/3]

#define DMA_EEI_EEI7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..An error on channel 7 does not generate an error interrupt 0b1..An error on channel 7 generates an error interrupt request

◆ DMA_EEI_EEI7 [3/3]

#define DMA_EEI_EEI7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..An error on channel 7 does not generate an error interrupt 0b1..An error on channel 7 generates an error interrupt request

◆ DMA_EEI_EEI8 [1/3]

#define DMA_EEI_EEI8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..An error on channel 8 does not generate an error interrupt 0b1..An error on channel 8 generates an error interrupt request

◆ DMA_EEI_EEI8 [2/3]

#define DMA_EEI_EEI8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..An error on channel 8 does not generate an error interrupt 0b1..An error on channel 8 generates an error interrupt request

◆ DMA_EEI_EEI8 [3/3]

#define DMA_EEI_EEI8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..An error on channel 8 does not generate an error interrupt 0b1..An error on channel 8 generates an error interrupt request

◆ DMA_EEI_EEI9 [1/3]

#define DMA_EEI_EEI9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..An error on channel 9 does not generate an error interrupt 0b1..An error on channel 9 generates an error interrupt request

◆ DMA_EEI_EEI9 [2/3]

#define DMA_EEI_EEI9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..An error on channel 9 does not generate an error interrupt 0b1..An error on channel 9 generates an error interrupt request

◆ DMA_EEI_EEI9 [3/3]

#define DMA_EEI_EEI9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..An error on channel 9 does not generate an error interrupt 0b1..An error on channel 9 generates an error interrupt request

◆ DMA_ERQ_ERQ0 [1/3]

#define DMA_ERQ_ERQ0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for channel 0 is disabled 0b1..The DMA request signal for channel 0 is enabled

◆ DMA_ERQ_ERQ0 [2/3]

#define DMA_ERQ_ERQ0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for channel 0 is disabled 0b1..The DMA request signal for channel 0 is enabled

◆ DMA_ERQ_ERQ0 [3/3]

#define DMA_ERQ_ERQ0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for channel 0 is disabled 0b1..The DMA request signal for channel 0 is enabled

◆ DMA_ERQ_ERQ1 [1/3]

#define DMA_ERQ_ERQ1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for channel 1 is disabled 0b1..The DMA request signal for channel 1 is enabled

◆ DMA_ERQ_ERQ1 [2/3]

#define DMA_ERQ_ERQ1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for channel 1 is disabled 0b1..The DMA request signal for channel 1 is enabled

◆ DMA_ERQ_ERQ1 [3/3]

#define DMA_ERQ_ERQ1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for channel 1 is disabled 0b1..The DMA request signal for channel 1 is enabled

◆ DMA_ERQ_ERQ10 [1/3]

#define DMA_ERQ_ERQ10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for channel 10 is disabled 0b1..The DMA request signal for channel 10 is enabled

◆ DMA_ERQ_ERQ10 [2/3]

#define DMA_ERQ_ERQ10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for channel 10 is disabled 0b1..The DMA request signal for channel 10 is enabled

◆ DMA_ERQ_ERQ10 [3/3]

#define DMA_ERQ_ERQ10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for channel 10 is disabled 0b1..The DMA request signal for channel 10 is enabled

◆ DMA_ERQ_ERQ11 [1/3]

#define DMA_ERQ_ERQ11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for channel 11 is disabled 0b1..The DMA request signal for channel 11 is enabled

◆ DMA_ERQ_ERQ11 [2/3]

#define DMA_ERQ_ERQ11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for channel 11 is disabled 0b1..The DMA request signal for channel 11 is enabled

◆ DMA_ERQ_ERQ11 [3/3]

#define DMA_ERQ_ERQ11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for channel 11 is disabled 0b1..The DMA request signal for channel 11 is enabled

◆ DMA_ERQ_ERQ12 [1/3]

#define DMA_ERQ_ERQ12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for channel 12 is disabled 0b1..The DMA request signal for channel 12 is enabled

◆ DMA_ERQ_ERQ12 [2/3]

#define DMA_ERQ_ERQ12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for channel 12 is disabled 0b1..The DMA request signal for channel 12 is enabled

◆ DMA_ERQ_ERQ12 [3/3]

#define DMA_ERQ_ERQ12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for channel 12 is disabled 0b1..The DMA request signal for channel 12 is enabled

◆ DMA_ERQ_ERQ13 [1/3]

#define DMA_ERQ_ERQ13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for channel 13 is disabled 0b1..The DMA request signal for channel 13 is enabled

◆ DMA_ERQ_ERQ13 [2/3]

#define DMA_ERQ_ERQ13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for channel 13 is disabled 0b1..The DMA request signal for channel 13 is enabled

◆ DMA_ERQ_ERQ13 [3/3]

#define DMA_ERQ_ERQ13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for channel 13 is disabled 0b1..The DMA request signal for channel 13 is enabled

◆ DMA_ERQ_ERQ14 [1/3]

#define DMA_ERQ_ERQ14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for channel 14 is disabled 0b1..The DMA request signal for channel 14 is enabled

◆ DMA_ERQ_ERQ14 [2/3]

#define DMA_ERQ_ERQ14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for channel 14 is disabled 0b1..The DMA request signal for channel 14 is enabled

◆ DMA_ERQ_ERQ14 [3/3]

#define DMA_ERQ_ERQ14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for channel 14 is disabled 0b1..The DMA request signal for channel 14 is enabled

◆ DMA_ERQ_ERQ15 [1/3]

#define DMA_ERQ_ERQ15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for channel 15 is disabled 0b1..The DMA request signal for channel 15 is enabled

◆ DMA_ERQ_ERQ15 [2/3]

#define DMA_ERQ_ERQ15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for channel 15 is disabled 0b1..The DMA request signal for channel 15 is enabled

◆ DMA_ERQ_ERQ15 [3/3]

#define DMA_ERQ_ERQ15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for channel 15 is disabled 0b1..The DMA request signal for channel 15 is enabled

◆ DMA_ERQ_ERQ16 [1/3]

#define DMA_ERQ_ERQ16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

ERQ16 - Enable DMA Request 16 0b0..The DMA request signal for channel 16 is disabled 0b1..The DMA request signal for channel 16 is enabled

◆ DMA_ERQ_ERQ16 [2/3]

#define DMA_ERQ_ERQ16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

ERQ16 - Enable DMA Request 16 0b0..The DMA request signal for channel 16 is disabled 0b1..The DMA request signal for channel 16 is enabled

◆ DMA_ERQ_ERQ16 [3/3]

#define DMA_ERQ_ERQ16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

ERQ16 - Enable DMA Request 16 0b0..The DMA request signal for channel 16 is disabled 0b1..The DMA request signal for channel 16 is enabled

◆ DMA_ERQ_ERQ17 [1/3]

#define DMA_ERQ_ERQ17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

ERQ17 - Enable DMA Request 17 0b0..The DMA request signal for channel 17 is disabled 0b1..The DMA request signal for channel 17 is enabled

◆ DMA_ERQ_ERQ17 [2/3]

#define DMA_ERQ_ERQ17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

ERQ17 - Enable DMA Request 17 0b0..The DMA request signal for channel 17 is disabled 0b1..The DMA request signal for channel 17 is enabled

◆ DMA_ERQ_ERQ17 [3/3]

#define DMA_ERQ_ERQ17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

ERQ17 - Enable DMA Request 17 0b0..The DMA request signal for channel 17 is disabled 0b1..The DMA request signal for channel 17 is enabled

◆ DMA_ERQ_ERQ18 [1/3]

#define DMA_ERQ_ERQ18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

ERQ18 - Enable DMA Request 18 0b0..The DMA request signal for channel 18 is disabled 0b1..The DMA request signal for channel 18 is enabled

◆ DMA_ERQ_ERQ18 [2/3]

#define DMA_ERQ_ERQ18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

ERQ18 - Enable DMA Request 18 0b0..The DMA request signal for channel 18 is disabled 0b1..The DMA request signal for channel 18 is enabled

◆ DMA_ERQ_ERQ18 [3/3]

#define DMA_ERQ_ERQ18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

ERQ18 - Enable DMA Request 18 0b0..The DMA request signal for channel 18 is disabled 0b1..The DMA request signal for channel 18 is enabled

◆ DMA_ERQ_ERQ19 [1/3]

#define DMA_ERQ_ERQ19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

ERQ19 - Enable DMA Request 19 0b0..The DMA request signal for channel 19 is disabled 0b1..The DMA request signal for channel 19 is enabled

◆ DMA_ERQ_ERQ19 [2/3]

#define DMA_ERQ_ERQ19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

ERQ19 - Enable DMA Request 19 0b0..The DMA request signal for channel 19 is disabled 0b1..The DMA request signal for channel 19 is enabled

◆ DMA_ERQ_ERQ19 [3/3]

#define DMA_ERQ_ERQ19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

ERQ19 - Enable DMA Request 19 0b0..The DMA request signal for channel 19 is disabled 0b1..The DMA request signal for channel 19 is enabled

◆ DMA_ERQ_ERQ2 [1/3]

#define DMA_ERQ_ERQ2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for channel 2 is disabled 0b1..The DMA request signal for channel 2 is enabled

◆ DMA_ERQ_ERQ2 [2/3]

#define DMA_ERQ_ERQ2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for channel 2 is disabled 0b1..The DMA request signal for channel 2 is enabled

◆ DMA_ERQ_ERQ2 [3/3]

#define DMA_ERQ_ERQ2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for channel 2 is disabled 0b1..The DMA request signal for channel 2 is enabled

◆ DMA_ERQ_ERQ20 [1/3]

#define DMA_ERQ_ERQ20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

ERQ20 - Enable DMA Request 20 0b0..The DMA request signal for channel 20 is disabled 0b1..The DMA request signal for channel 20 is enabled

◆ DMA_ERQ_ERQ20 [2/3]

#define DMA_ERQ_ERQ20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

ERQ20 - Enable DMA Request 20 0b0..The DMA request signal for channel 20 is disabled 0b1..The DMA request signal for channel 20 is enabled

◆ DMA_ERQ_ERQ20 [3/3]

#define DMA_ERQ_ERQ20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

ERQ20 - Enable DMA Request 20 0b0..The DMA request signal for channel 20 is disabled 0b1..The DMA request signal for channel 20 is enabled

◆ DMA_ERQ_ERQ21 [1/3]

#define DMA_ERQ_ERQ21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

ERQ21 - Enable DMA Request 21 0b0..The DMA request signal for channel 21 is disabled 0b1..The DMA request signal for channel 21 is enabled

◆ DMA_ERQ_ERQ21 [2/3]

#define DMA_ERQ_ERQ21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

ERQ21 - Enable DMA Request 21 0b0..The DMA request signal for channel 21 is disabled 0b1..The DMA request signal for channel 21 is enabled

◆ DMA_ERQ_ERQ21 [3/3]

#define DMA_ERQ_ERQ21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

ERQ21 - Enable DMA Request 21 0b0..The DMA request signal for channel 21 is disabled 0b1..The DMA request signal for channel 21 is enabled

◆ DMA_ERQ_ERQ22 [1/3]

#define DMA_ERQ_ERQ22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

ERQ22 - Enable DMA Request 22 0b0..The DMA request signal for channel 22 is disabled 0b1..The DMA request signal for channel 22 is enabled

◆ DMA_ERQ_ERQ22 [2/3]

#define DMA_ERQ_ERQ22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

ERQ22 - Enable DMA Request 22 0b0..The DMA request signal for channel 22 is disabled 0b1..The DMA request signal for channel 22 is enabled

◆ DMA_ERQ_ERQ22 [3/3]

#define DMA_ERQ_ERQ22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

ERQ22 - Enable DMA Request 22 0b0..The DMA request signal for channel 22 is disabled 0b1..The DMA request signal for channel 22 is enabled

◆ DMA_ERQ_ERQ23 [1/3]

#define DMA_ERQ_ERQ23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

ERQ23 - Enable DMA Request 23 0b0..The DMA request signal for channel 23 is disabled 0b1..The DMA request signal for channel 23 is enabled

◆ DMA_ERQ_ERQ23 [2/3]

#define DMA_ERQ_ERQ23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

ERQ23 - Enable DMA Request 23 0b0..The DMA request signal for channel 23 is disabled 0b1..The DMA request signal for channel 23 is enabled

◆ DMA_ERQ_ERQ23 [3/3]

#define DMA_ERQ_ERQ23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

ERQ23 - Enable DMA Request 23 0b0..The DMA request signal for channel 23 is disabled 0b1..The DMA request signal for channel 23 is enabled

◆ DMA_ERQ_ERQ24 [1/3]

#define DMA_ERQ_ERQ24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

ERQ24 - Enable DMA Request 24 0b0..The DMA request signal for channel 24 is disabled 0b1..The DMA request signal for channel 24 is enabled

◆ DMA_ERQ_ERQ24 [2/3]

#define DMA_ERQ_ERQ24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

ERQ24 - Enable DMA Request 24 0b0..The DMA request signal for channel 24 is disabled 0b1..The DMA request signal for channel 24 is enabled

◆ DMA_ERQ_ERQ24 [3/3]

#define DMA_ERQ_ERQ24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

ERQ24 - Enable DMA Request 24 0b0..The DMA request signal for channel 24 is disabled 0b1..The DMA request signal for channel 24 is enabled

◆ DMA_ERQ_ERQ25 [1/3]

#define DMA_ERQ_ERQ25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

ERQ25 - Enable DMA Request 25 0b0..The DMA request signal for channel 25 is disabled 0b1..The DMA request signal for channel 25 is enabled

◆ DMA_ERQ_ERQ25 [2/3]

#define DMA_ERQ_ERQ25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

ERQ25 - Enable DMA Request 25 0b0..The DMA request signal for channel 25 is disabled 0b1..The DMA request signal for channel 25 is enabled

◆ DMA_ERQ_ERQ25 [3/3]

#define DMA_ERQ_ERQ25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

ERQ25 - Enable DMA Request 25 0b0..The DMA request signal for channel 25 is disabled 0b1..The DMA request signal for channel 25 is enabled

◆ DMA_ERQ_ERQ26 [1/3]

#define DMA_ERQ_ERQ26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

ERQ26 - Enable DMA Request 26 0b0..The DMA request signal for channel 26 is disabled 0b1..The DMA request signal for channel 26 is enabled

◆ DMA_ERQ_ERQ26 [2/3]

#define DMA_ERQ_ERQ26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

ERQ26 - Enable DMA Request 26 0b0..The DMA request signal for channel 26 is disabled 0b1..The DMA request signal for channel 26 is enabled

◆ DMA_ERQ_ERQ26 [3/3]

#define DMA_ERQ_ERQ26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

ERQ26 - Enable DMA Request 26 0b0..The DMA request signal for channel 26 is disabled 0b1..The DMA request signal for channel 26 is enabled

◆ DMA_ERQ_ERQ27 [1/3]

#define DMA_ERQ_ERQ27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

ERQ27 - Enable DMA Request 27 0b0..The DMA request signal for channel 27 is disabled 0b1..The DMA request signal for channel 27 is enabled

◆ DMA_ERQ_ERQ27 [2/3]

#define DMA_ERQ_ERQ27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

ERQ27 - Enable DMA Request 27 0b0..The DMA request signal for channel 27 is disabled 0b1..The DMA request signal for channel 27 is enabled

◆ DMA_ERQ_ERQ27 [3/3]

#define DMA_ERQ_ERQ27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

ERQ27 - Enable DMA Request 27 0b0..The DMA request signal for channel 27 is disabled 0b1..The DMA request signal for channel 27 is enabled

◆ DMA_ERQ_ERQ28 [1/3]

#define DMA_ERQ_ERQ28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

ERQ28 - Enable DMA Request 28 0b0..The DMA request signal for channel 28 is disabled 0b1..The DMA request signal for channel 28 is enabled

◆ DMA_ERQ_ERQ28 [2/3]

#define DMA_ERQ_ERQ28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

ERQ28 - Enable DMA Request 28 0b0..The DMA request signal for channel 28 is disabled 0b1..The DMA request signal for channel 28 is enabled

◆ DMA_ERQ_ERQ28 [3/3]

#define DMA_ERQ_ERQ28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

ERQ28 - Enable DMA Request 28 0b0..The DMA request signal for channel 28 is disabled 0b1..The DMA request signal for channel 28 is enabled

◆ DMA_ERQ_ERQ29 [1/3]

#define DMA_ERQ_ERQ29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

ERQ29 - Enable DMA Request 29 0b0..The DMA request signal for channel 29 is disabled 0b1..The DMA request signal for channel 29 is enabled

◆ DMA_ERQ_ERQ29 [2/3]

#define DMA_ERQ_ERQ29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

ERQ29 - Enable DMA Request 29 0b0..The DMA request signal for channel 29 is disabled 0b1..The DMA request signal for channel 29 is enabled

◆ DMA_ERQ_ERQ29 [3/3]

#define DMA_ERQ_ERQ29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

ERQ29 - Enable DMA Request 29 0b0..The DMA request signal for channel 29 is disabled 0b1..The DMA request signal for channel 29 is enabled

◆ DMA_ERQ_ERQ3 [1/3]

#define DMA_ERQ_ERQ3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for channel 3 is disabled 0b1..The DMA request signal for channel 3 is enabled

◆ DMA_ERQ_ERQ3 [2/3]

#define DMA_ERQ_ERQ3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for channel 3 is disabled 0b1..The DMA request signal for channel 3 is enabled

◆ DMA_ERQ_ERQ3 [3/3]

#define DMA_ERQ_ERQ3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for channel 3 is disabled 0b1..The DMA request signal for channel 3 is enabled

◆ DMA_ERQ_ERQ30 [1/3]

#define DMA_ERQ_ERQ30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

ERQ30 - Enable DMA Request 30 0b0..The DMA request signal for channel 30 is disabled 0b1..The DMA request signal for channel 30 is enabled

◆ DMA_ERQ_ERQ30 [2/3]

#define DMA_ERQ_ERQ30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

ERQ30 - Enable DMA Request 30 0b0..The DMA request signal for channel 30 is disabled 0b1..The DMA request signal for channel 30 is enabled

◆ DMA_ERQ_ERQ30 [3/3]

#define DMA_ERQ_ERQ30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

ERQ30 - Enable DMA Request 30 0b0..The DMA request signal for channel 30 is disabled 0b1..The DMA request signal for channel 30 is enabled

◆ DMA_ERQ_ERQ31 [1/3]

#define DMA_ERQ_ERQ31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

ERQ31 - Enable DMA Request 31 0b0..The DMA request signal for channel 31 is disabled 0b1..The DMA request signal for channel 31 is enabled

◆ DMA_ERQ_ERQ31 [2/3]

#define DMA_ERQ_ERQ31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

ERQ31 - Enable DMA Request 31 0b0..The DMA request signal for channel 31 is disabled 0b1..The DMA request signal for channel 31 is enabled

◆ DMA_ERQ_ERQ31 [3/3]

#define DMA_ERQ_ERQ31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

ERQ31 - Enable DMA Request 31 0b0..The DMA request signal for channel 31 is disabled 0b1..The DMA request signal for channel 31 is enabled

◆ DMA_ERQ_ERQ4 [1/3]

#define DMA_ERQ_ERQ4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for channel 4 is disabled 0b1..The DMA request signal for channel 4 is enabled

◆ DMA_ERQ_ERQ4 [2/3]

#define DMA_ERQ_ERQ4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for channel 4 is disabled 0b1..The DMA request signal for channel 4 is enabled

◆ DMA_ERQ_ERQ4 [3/3]

#define DMA_ERQ_ERQ4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for channel 4 is disabled 0b1..The DMA request signal for channel 4 is enabled

◆ DMA_ERQ_ERQ5 [1/3]

#define DMA_ERQ_ERQ5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for channel 5 is disabled 0b1..The DMA request signal for channel 5 is enabled

◆ DMA_ERQ_ERQ5 [2/3]

#define DMA_ERQ_ERQ5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for channel 5 is disabled 0b1..The DMA request signal for channel 5 is enabled

◆ DMA_ERQ_ERQ5 [3/3]

#define DMA_ERQ_ERQ5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for channel 5 is disabled 0b1..The DMA request signal for channel 5 is enabled

◆ DMA_ERQ_ERQ6 [1/3]

#define DMA_ERQ_ERQ6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for channel 6 is disabled 0b1..The DMA request signal for channel 6 is enabled

◆ DMA_ERQ_ERQ6 [2/3]

#define DMA_ERQ_ERQ6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for channel 6 is disabled 0b1..The DMA request signal for channel 6 is enabled

◆ DMA_ERQ_ERQ6 [3/3]

#define DMA_ERQ_ERQ6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for channel 6 is disabled 0b1..The DMA request signal for channel 6 is enabled

◆ DMA_ERQ_ERQ7 [1/3]

#define DMA_ERQ_ERQ7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for channel 7 is disabled 0b1..The DMA request signal for channel 7 is enabled

◆ DMA_ERQ_ERQ7 [2/3]

#define DMA_ERQ_ERQ7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for channel 7 is disabled 0b1..The DMA request signal for channel 7 is enabled

◆ DMA_ERQ_ERQ7 [3/3]

#define DMA_ERQ_ERQ7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for channel 7 is disabled 0b1..The DMA request signal for channel 7 is enabled

◆ DMA_ERQ_ERQ8 [1/3]

#define DMA_ERQ_ERQ8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for channel 8 is disabled 0b1..The DMA request signal for channel 8 is enabled

◆ DMA_ERQ_ERQ8 [2/3]

#define DMA_ERQ_ERQ8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for channel 8 is disabled 0b1..The DMA request signal for channel 8 is enabled

◆ DMA_ERQ_ERQ8 [3/3]

#define DMA_ERQ_ERQ8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for channel 8 is disabled 0b1..The DMA request signal for channel 8 is enabled

◆ DMA_ERQ_ERQ9 [1/3]

#define DMA_ERQ_ERQ9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for channel 9 is disabled 0b1..The DMA request signal for channel 9 is enabled

◆ DMA_ERQ_ERQ9 [2/3]

#define DMA_ERQ_ERQ9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for channel 9 is disabled 0b1..The DMA request signal for channel 9 is enabled

◆ DMA_ERQ_ERQ9 [3/3]

#define DMA_ERQ_ERQ9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for channel 9 is disabled 0b1..The DMA request signal for channel 9 is enabled

◆ DMA_ERR_ERR0 [1/3]

#define DMA_ERR_ERR0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR0 [2/3]

#define DMA_ERR_ERR0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR0 [3/3]

#define DMA_ERR_ERR0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR1 [1/3]

#define DMA_ERR_ERR1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR1 [2/3]

#define DMA_ERR_ERR1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR1 [3/3]

#define DMA_ERR_ERR1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR10 [1/3]

#define DMA_ERR_ERR10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR10 [2/3]

#define DMA_ERR_ERR10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR10 [3/3]

#define DMA_ERR_ERR10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR11 [1/3]

#define DMA_ERR_ERR11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR11 [2/3]

#define DMA_ERR_ERR11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR11 [3/3]

#define DMA_ERR_ERR11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR12 [1/3]

#define DMA_ERR_ERR12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR12 [2/3]

#define DMA_ERR_ERR12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR12 [3/3]

#define DMA_ERR_ERR12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR13 [1/3]

#define DMA_ERR_ERR13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR13 [2/3]

#define DMA_ERR_ERR13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR13 [3/3]

#define DMA_ERR_ERR13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR14 [1/3]

#define DMA_ERR_ERR14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR14 [2/3]

#define DMA_ERR_ERR14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR14 [3/3]

#define DMA_ERR_ERR14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR15 [1/3]

#define DMA_ERR_ERR15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR15 [2/3]

#define DMA_ERR_ERR15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR15 [3/3]

#define DMA_ERR_ERR15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR16 [1/3]

#define DMA_ERR_ERR16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

ERR16 - Error In Channel 16 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR16 [2/3]

#define DMA_ERR_ERR16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

ERR16 - Error In Channel 16 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR16 [3/3]

#define DMA_ERR_ERR16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

ERR16 - Error In Channel 16 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR17 [1/3]

#define DMA_ERR_ERR17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

ERR17 - Error In Channel 17 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR17 [2/3]

#define DMA_ERR_ERR17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

ERR17 - Error In Channel 17 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR17 [3/3]

#define DMA_ERR_ERR17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

ERR17 - Error In Channel 17 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR18 [1/3]

#define DMA_ERR_ERR18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

ERR18 - Error In Channel 18 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR18 [2/3]

#define DMA_ERR_ERR18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

ERR18 - Error In Channel 18 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR18 [3/3]

#define DMA_ERR_ERR18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

ERR18 - Error In Channel 18 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR19 [1/3]

#define DMA_ERR_ERR19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

ERR19 - Error In Channel 19 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR19 [2/3]

#define DMA_ERR_ERR19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

ERR19 - Error In Channel 19 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR19 [3/3]

#define DMA_ERR_ERR19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

ERR19 - Error In Channel 19 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR2 [1/3]

#define DMA_ERR_ERR2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR2 [2/3]

#define DMA_ERR_ERR2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR2 [3/3]

#define DMA_ERR_ERR2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR20 [1/3]

#define DMA_ERR_ERR20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

ERR20 - Error In Channel 20 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR20 [2/3]

#define DMA_ERR_ERR20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

ERR20 - Error In Channel 20 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR20 [3/3]

#define DMA_ERR_ERR20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

ERR20 - Error In Channel 20 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR21 [1/3]

#define DMA_ERR_ERR21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

ERR21 - Error In Channel 21 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR21 [2/3]

#define DMA_ERR_ERR21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

ERR21 - Error In Channel 21 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR21 [3/3]

#define DMA_ERR_ERR21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

ERR21 - Error In Channel 21 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR22 [1/3]

#define DMA_ERR_ERR22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

ERR22 - Error In Channel 22 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR22 [2/3]

#define DMA_ERR_ERR22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

ERR22 - Error In Channel 22 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR22 [3/3]

#define DMA_ERR_ERR22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

ERR22 - Error In Channel 22 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR23 [1/3]

#define DMA_ERR_ERR23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

ERR23 - Error In Channel 23 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR23 [2/3]

#define DMA_ERR_ERR23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

ERR23 - Error In Channel 23 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR23 [3/3]

#define DMA_ERR_ERR23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

ERR23 - Error In Channel 23 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR24 [1/3]

#define DMA_ERR_ERR24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

ERR24 - Error In Channel 24 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR24 [2/3]

#define DMA_ERR_ERR24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

ERR24 - Error In Channel 24 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR24 [3/3]

#define DMA_ERR_ERR24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

ERR24 - Error In Channel 24 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR25 [1/3]

#define DMA_ERR_ERR25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

ERR25 - Error In Channel 25 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR25 [2/3]

#define DMA_ERR_ERR25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

ERR25 - Error In Channel 25 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR25 [3/3]

#define DMA_ERR_ERR25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

ERR25 - Error In Channel 25 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR26 [1/3]

#define DMA_ERR_ERR26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

ERR26 - Error In Channel 26 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR26 [2/3]

#define DMA_ERR_ERR26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

ERR26 - Error In Channel 26 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR26 [3/3]

#define DMA_ERR_ERR26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

ERR26 - Error In Channel 26 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR27 [1/3]

#define DMA_ERR_ERR27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

ERR27 - Error In Channel 27 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR27 [2/3]

#define DMA_ERR_ERR27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

ERR27 - Error In Channel 27 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR27 [3/3]

#define DMA_ERR_ERR27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

ERR27 - Error In Channel 27 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR28 [1/3]

#define DMA_ERR_ERR28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

ERR28 - Error In Channel 28 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR28 [2/3]

#define DMA_ERR_ERR28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

ERR28 - Error In Channel 28 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR28 [3/3]

#define DMA_ERR_ERR28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

ERR28 - Error In Channel 28 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR29 [1/3]

#define DMA_ERR_ERR29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

ERR29 - Error In Channel 29 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR29 [2/3]

#define DMA_ERR_ERR29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

ERR29 - Error In Channel 29 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR29 [3/3]

#define DMA_ERR_ERR29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

ERR29 - Error In Channel 29 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR3 [1/3]

#define DMA_ERR_ERR3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR3 [2/3]

#define DMA_ERR_ERR3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR3 [3/3]

#define DMA_ERR_ERR3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR30 [1/3]

#define DMA_ERR_ERR30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

ERR30 - Error In Channel 30 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR30 [2/3]

#define DMA_ERR_ERR30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

ERR30 - Error In Channel 30 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR30 [3/3]

#define DMA_ERR_ERR30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

ERR30 - Error In Channel 30 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR31 [1/3]

#define DMA_ERR_ERR31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

ERR31 - Error In Channel 31 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR31 [2/3]

#define DMA_ERR_ERR31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

ERR31 - Error In Channel 31 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR31 [3/3]

#define DMA_ERR_ERR31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

ERR31 - Error In Channel 31 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR4 [1/3]

#define DMA_ERR_ERR4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR4 [2/3]

#define DMA_ERR_ERR4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR4 [3/3]

#define DMA_ERR_ERR4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR5 [1/3]

#define DMA_ERR_ERR5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR5 [2/3]

#define DMA_ERR_ERR5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR5 [3/3]

#define DMA_ERR_ERR5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR6 [1/3]

#define DMA_ERR_ERR6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR6 [2/3]

#define DMA_ERR_ERR6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR6 [3/3]

#define DMA_ERR_ERR6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR7 [1/3]

#define DMA_ERR_ERR7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR7 [2/3]

#define DMA_ERR_ERR7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR7 [3/3]

#define DMA_ERR_ERR7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR8 [1/3]

#define DMA_ERR_ERR8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR8 [2/3]

#define DMA_ERR_ERR8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR8 [3/3]

#define DMA_ERR_ERR8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR9 [1/3]

#define DMA_ERR_ERR9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR9 [2/3]

#define DMA_ERR_ERR9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR9 [3/3]

#define DMA_ERR_ERR9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..No error in this channel has occurred 0b1..An error in this channel has occurred

◆ DMA_ES_CPE [1/3]

#define DMA_ES_CPE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error. 0b1..The most-recently recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

◆ DMA_ES_CPE [2/3]

#define DMA_ES_CPE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error. 0b1..The most-recently recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

◆ DMA_ES_CPE [3/3]

#define DMA_ES_CPE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error. 0b1..The most-recently recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

◆ DMA_ES_DAE [1/3]

#define DMA_ES_DAE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DAE [2/3]

#define DMA_ES_DAE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DAE [3/3]

#define DMA_ES_DAE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DBE [1/3]

#define DMA_ES_DBE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error. 0b1..The most-recently recorded error was a bus error on a destination write.

◆ DMA_ES_DBE [2/3]

#define DMA_ES_DBE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error. 0b1..The most-recently recorded error was a bus error on a destination write.

◆ DMA_ES_DBE [3/3]

#define DMA_ES_DBE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error. 0b1..The most-recently recorded error was a bus error on a destination write.

◆ DMA_ES_DOE [1/3]

#define DMA_ES_DOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DOE [2/3]

#define DMA_ES_DOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DOE [3/3]

#define DMA_ES_DOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_ECX [1/3]

#define DMA_ES_ECX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field

◆ DMA_ES_ECX [2/3]

#define DMA_ES_ECX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field

◆ DMA_ES_ECX [3/3]

#define DMA_ES_ECX ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field

◆ DMA_ES_ERRCHN [1/3]

#define DMA_ES_ERRCHN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

ERRCHN - Error Channel Number or Canceled Channel Number

◆ DMA_ES_ERRCHN [2/3]

#define DMA_ES_ERRCHN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

ERRCHN - Error Channel Number or Canceled Channel Number

◆ DMA_ES_ERRCHN [3/3]

#define DMA_ES_ERRCHN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

ERRCHN - Error Channel Number or Canceled Channel Number

◆ DMA_ES_GPE [1/3]

#define DMA_ES_GPE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

GPE - Group Priority Error 0b0..No group priority error. 0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique.

◆ DMA_ES_GPE [2/3]

#define DMA_ES_GPE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

GPE - Group Priority Error 0b0..No group priority error. 0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique.

◆ DMA_ES_GPE [3/3]

#define DMA_ES_GPE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

GPE - Group Priority Error 0b0..No group priority error. 0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique.

◆ DMA_ES_NCE [1/3]

#define DMA_ES_NCE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].

◆ DMA_ES_NCE [2/3]

#define DMA_ES_NCE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].

◆ DMA_ES_NCE [3/3]

#define DMA_ES_NCE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].

◆ DMA_ES_SAE [1/3]

#define DMA_ES_SAE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SAE [2/3]

#define DMA_ES_SAE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SAE [3/3]

#define DMA_ES_SAE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SBE [1/3]

#define DMA_ES_SBE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error. 0b1..The most-recently recorded error was a bus error on a source read.

◆ DMA_ES_SBE [2/3]

#define DMA_ES_SBE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error. 0b1..The most-recently recorded error was a bus error on a source read.

◆ DMA_ES_SBE [3/3]

#define DMA_ES_SBE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error. 0b1..The most-recently recorded error was a bus error on a source read.

◆ DMA_ES_SGE [1/3]

#define DMA_ES_SGE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.

◆ DMA_ES_SGE [2/3]

#define DMA_ES_SGE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.

◆ DMA_ES_SGE [3/3]

#define DMA_ES_SGE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.

◆ DMA_ES_SOE [1/3]

#define DMA_ES_SOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SOE [2/3]

#define DMA_ES_SOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SOE [3/3]

#define DMA_ES_SOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error. 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_VLD [1/3]

#define DMA_ES_VLD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD - Logical OR of all ERR status fields 0b0..No ERR fields are 1 0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared

◆ DMA_ES_VLD [2/3]

#define DMA_ES_VLD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD - Logical OR of all ERR status fields 0b0..No ERR fields are 1 0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared

◆ DMA_ES_VLD [3/3]

#define DMA_ES_VLD ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD - Logical OR of all ERR status fields 0b0..No ERR fields are 1 0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared

◆ DMA_HRS_HRS0 [1/3]

#define DMA_HRS_HRS0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

◆ DMA_HRS_HRS0 [2/3]

#define DMA_HRS_HRS0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

◆ DMA_HRS_HRS0 [3/3]

#define DMA_HRS_HRS0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

◆ DMA_HRS_HRS1 [1/3]

#define DMA_HRS_HRS1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

◆ DMA_HRS_HRS1 [2/3]

#define DMA_HRS_HRS1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

◆ DMA_HRS_HRS1 [3/3]

#define DMA_HRS_HRS1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

◆ DMA_HRS_HRS10 [1/3]

#define DMA_HRS_HRS10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

◆ DMA_HRS_HRS10 [2/3]

#define DMA_HRS_HRS10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

◆ DMA_HRS_HRS10 [3/3]

#define DMA_HRS_HRS10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

◆ DMA_HRS_HRS11 [1/3]

#define DMA_HRS_HRS11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

◆ DMA_HRS_HRS11 [2/3]

#define DMA_HRS_HRS11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

◆ DMA_HRS_HRS11 [3/3]

#define DMA_HRS_HRS11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

◆ DMA_HRS_HRS12 [1/3]

#define DMA_HRS_HRS12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

◆ DMA_HRS_HRS12 [2/3]

#define DMA_HRS_HRS12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

◆ DMA_HRS_HRS12 [3/3]

#define DMA_HRS_HRS12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

◆ DMA_HRS_HRS13 [1/3]

#define DMA_HRS_HRS13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

◆ DMA_HRS_HRS13 [2/3]

#define DMA_HRS_HRS13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

◆ DMA_HRS_HRS13 [3/3]

#define DMA_HRS_HRS13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

◆ DMA_HRS_HRS14 [1/3]

#define DMA_HRS_HRS14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

◆ DMA_HRS_HRS14 [2/3]

#define DMA_HRS_HRS14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

◆ DMA_HRS_HRS14 [3/3]

#define DMA_HRS_HRS14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

◆ DMA_HRS_HRS15 [1/3]

#define DMA_HRS_HRS15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

◆ DMA_HRS_HRS15 [2/3]

#define DMA_HRS_HRS15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

◆ DMA_HRS_HRS15 [3/3]

#define DMA_HRS_HRS15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

◆ DMA_HRS_HRS16 [1/3]

#define DMA_HRS_HRS16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

HRS16 - Hardware Request Status Channel 16 0b0..A hardware service request for channel 16 is not present 0b1..A hardware service request for channel 16 is present

◆ DMA_HRS_HRS16 [2/3]

#define DMA_HRS_HRS16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

HRS16 - Hardware Request Status Channel 16 0b0..A hardware service request for channel 16 is not present 0b1..A hardware service request for channel 16 is present

◆ DMA_HRS_HRS16 [3/3]

#define DMA_HRS_HRS16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

HRS16 - Hardware Request Status Channel 16 0b0..A hardware service request for channel 16 is not present 0b1..A hardware service request for channel 16 is present

◆ DMA_HRS_HRS17 [1/3]

#define DMA_HRS_HRS17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

HRS17 - Hardware Request Status Channel 17 0b0..A hardware service request for channel 17 is not present 0b1..A hardware service request for channel 17 is present

◆ DMA_HRS_HRS17 [2/3]

#define DMA_HRS_HRS17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

HRS17 - Hardware Request Status Channel 17 0b0..A hardware service request for channel 17 is not present 0b1..A hardware service request for channel 17 is present

◆ DMA_HRS_HRS17 [3/3]

#define DMA_HRS_HRS17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

HRS17 - Hardware Request Status Channel 17 0b0..A hardware service request for channel 17 is not present 0b1..A hardware service request for channel 17 is present

◆ DMA_HRS_HRS18 [1/3]

#define DMA_HRS_HRS18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

HRS18 - Hardware Request Status Channel 18 0b0..A hardware service request for channel 18 is not present 0b1..A hardware service request for channel 18 is present

◆ DMA_HRS_HRS18 [2/3]

#define DMA_HRS_HRS18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

HRS18 - Hardware Request Status Channel 18 0b0..A hardware service request for channel 18 is not present 0b1..A hardware service request for channel 18 is present

◆ DMA_HRS_HRS18 [3/3]

#define DMA_HRS_HRS18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

HRS18 - Hardware Request Status Channel 18 0b0..A hardware service request for channel 18 is not present 0b1..A hardware service request for channel 18 is present

◆ DMA_HRS_HRS19 [1/3]

#define DMA_HRS_HRS19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

HRS19 - Hardware Request Status Channel 19 0b0..A hardware service request for channel 19 is not present 0b1..A hardware service request for channel 19 is present

◆ DMA_HRS_HRS19 [2/3]

#define DMA_HRS_HRS19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

HRS19 - Hardware Request Status Channel 19 0b0..A hardware service request for channel 19 is not present 0b1..A hardware service request for channel 19 is present

◆ DMA_HRS_HRS19 [3/3]

#define DMA_HRS_HRS19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

HRS19 - Hardware Request Status Channel 19 0b0..A hardware service request for channel 19 is not present 0b1..A hardware service request for channel 19 is present

◆ DMA_HRS_HRS2 [1/3]

#define DMA_HRS_HRS2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

◆ DMA_HRS_HRS2 [2/3]

#define DMA_HRS_HRS2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

◆ DMA_HRS_HRS2 [3/3]

#define DMA_HRS_HRS2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

◆ DMA_HRS_HRS20 [1/3]

#define DMA_HRS_HRS20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

HRS20 - Hardware Request Status Channel 20 0b0..A hardware service request for channel 20 is not present 0b1..A hardware service request for channel 20 is present

◆ DMA_HRS_HRS20 [2/3]

#define DMA_HRS_HRS20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

HRS20 - Hardware Request Status Channel 20 0b0..A hardware service request for channel 20 is not present 0b1..A hardware service request for channel 20 is present

◆ DMA_HRS_HRS20 [3/3]

#define DMA_HRS_HRS20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

HRS20 - Hardware Request Status Channel 20 0b0..A hardware service request for channel 20 is not present 0b1..A hardware service request for channel 20 is present

◆ DMA_HRS_HRS21 [1/3]

#define DMA_HRS_HRS21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

HRS21 - Hardware Request Status Channel 21 0b0..A hardware service request for channel 21 is not present 0b1..A hardware service request for channel 21 is present

◆ DMA_HRS_HRS21 [2/3]

#define DMA_HRS_HRS21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

HRS21 - Hardware Request Status Channel 21 0b0..A hardware service request for channel 21 is not present 0b1..A hardware service request for channel 21 is present

◆ DMA_HRS_HRS21 [3/3]

#define DMA_HRS_HRS21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

HRS21 - Hardware Request Status Channel 21 0b0..A hardware service request for channel 21 is not present 0b1..A hardware service request for channel 21 is present

◆ DMA_HRS_HRS22 [1/3]

#define DMA_HRS_HRS22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

HRS22 - Hardware Request Status Channel 22 0b0..A hardware service request for channel 22 is not present 0b1..A hardware service request for channel 22 is present

◆ DMA_HRS_HRS22 [2/3]

#define DMA_HRS_HRS22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

HRS22 - Hardware Request Status Channel 22 0b0..A hardware service request for channel 22 is not present 0b1..A hardware service request for channel 22 is present

◆ DMA_HRS_HRS22 [3/3]

#define DMA_HRS_HRS22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

HRS22 - Hardware Request Status Channel 22 0b0..A hardware service request for channel 22 is not present 0b1..A hardware service request for channel 22 is present

◆ DMA_HRS_HRS23 [1/3]

#define DMA_HRS_HRS23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

HRS23 - Hardware Request Status Channel 23 0b0..A hardware service request for channel 23 is not present 0b1..A hardware service request for channel 23 is present

◆ DMA_HRS_HRS23 [2/3]

#define DMA_HRS_HRS23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

HRS23 - Hardware Request Status Channel 23 0b0..A hardware service request for channel 23 is not present 0b1..A hardware service request for channel 23 is present

◆ DMA_HRS_HRS23 [3/3]

#define DMA_HRS_HRS23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

HRS23 - Hardware Request Status Channel 23 0b0..A hardware service request for channel 23 is not present 0b1..A hardware service request for channel 23 is present

◆ DMA_HRS_HRS24 [1/3]

#define DMA_HRS_HRS24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

HRS24 - Hardware Request Status Channel 24 0b0..A hardware service request for channel 24 is not present 0b1..A hardware service request for channel 24 is present

◆ DMA_HRS_HRS24 [2/3]

#define DMA_HRS_HRS24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

HRS24 - Hardware Request Status Channel 24 0b0..A hardware service request for channel 24 is not present 0b1..A hardware service request for channel 24 is present

◆ DMA_HRS_HRS24 [3/3]

#define DMA_HRS_HRS24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

HRS24 - Hardware Request Status Channel 24 0b0..A hardware service request for channel 24 is not present 0b1..A hardware service request for channel 24 is present

◆ DMA_HRS_HRS25 [1/3]

#define DMA_HRS_HRS25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

HRS25 - Hardware Request Status Channel 25 0b0..A hardware service request for channel 25 is not present 0b1..A hardware service request for channel 25 is present

◆ DMA_HRS_HRS25 [2/3]

#define DMA_HRS_HRS25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

HRS25 - Hardware Request Status Channel 25 0b0..A hardware service request for channel 25 is not present 0b1..A hardware service request for channel 25 is present

◆ DMA_HRS_HRS25 [3/3]

#define DMA_HRS_HRS25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

HRS25 - Hardware Request Status Channel 25 0b0..A hardware service request for channel 25 is not present 0b1..A hardware service request for channel 25 is present

◆ DMA_HRS_HRS26 [1/3]

#define DMA_HRS_HRS26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

HRS26 - Hardware Request Status Channel 26 0b0..A hardware service request for channel 26 is not present 0b1..A hardware service request for channel 26 is present

◆ DMA_HRS_HRS26 [2/3]

#define DMA_HRS_HRS26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

HRS26 - Hardware Request Status Channel 26 0b0..A hardware service request for channel 26 is not present 0b1..A hardware service request for channel 26 is present

◆ DMA_HRS_HRS26 [3/3]

#define DMA_HRS_HRS26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

HRS26 - Hardware Request Status Channel 26 0b0..A hardware service request for channel 26 is not present 0b1..A hardware service request for channel 26 is present

◆ DMA_HRS_HRS27 [1/3]

#define DMA_HRS_HRS27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

HRS27 - Hardware Request Status Channel 27 0b0..A hardware service request for channel 27 is not present 0b1..A hardware service request for channel 27 is present

◆ DMA_HRS_HRS27 [2/3]

#define DMA_HRS_HRS27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

HRS27 - Hardware Request Status Channel 27 0b0..A hardware service request for channel 27 is not present 0b1..A hardware service request for channel 27 is present

◆ DMA_HRS_HRS27 [3/3]

#define DMA_HRS_HRS27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

HRS27 - Hardware Request Status Channel 27 0b0..A hardware service request for channel 27 is not present 0b1..A hardware service request for channel 27 is present

◆ DMA_HRS_HRS28 [1/3]

#define DMA_HRS_HRS28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

HRS28 - Hardware Request Status Channel 28 0b0..A hardware service request for channel 28 is not present 0b1..A hardware service request for channel 28 is present

◆ DMA_HRS_HRS28 [2/3]

#define DMA_HRS_HRS28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

HRS28 - Hardware Request Status Channel 28 0b0..A hardware service request for channel 28 is not present 0b1..A hardware service request for channel 28 is present

◆ DMA_HRS_HRS28 [3/3]

#define DMA_HRS_HRS28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

HRS28 - Hardware Request Status Channel 28 0b0..A hardware service request for channel 28 is not present 0b1..A hardware service request for channel 28 is present

◆ DMA_HRS_HRS29 [1/3]

#define DMA_HRS_HRS29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

HRS29 - Hardware Request Status Channel 29 0b0..A hardware service request for channel 29 is not preset 0b1..A hardware service request for channel 29 is present

◆ DMA_HRS_HRS29 [2/3]

#define DMA_HRS_HRS29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

HRS29 - Hardware Request Status Channel 29 0b0..A hardware service request for channel 29 is not preset 0b1..A hardware service request for channel 29 is present

◆ DMA_HRS_HRS29 [3/3]

#define DMA_HRS_HRS29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

HRS29 - Hardware Request Status Channel 29 0b0..A hardware service request for channel 29 is not preset 0b1..A hardware service request for channel 29 is present

◆ DMA_HRS_HRS3 [1/3]

#define DMA_HRS_HRS3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

◆ DMA_HRS_HRS3 [2/3]

#define DMA_HRS_HRS3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

◆ DMA_HRS_HRS3 [3/3]

#define DMA_HRS_HRS3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

◆ DMA_HRS_HRS30 [1/3]

#define DMA_HRS_HRS30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

HRS30 - Hardware Request Status Channel 30 0b0..A hardware service request for channel 30 is not present 0b1..A hardware service request for channel 30 is present

◆ DMA_HRS_HRS30 [2/3]

#define DMA_HRS_HRS30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

HRS30 - Hardware Request Status Channel 30 0b0..A hardware service request for channel 30 is not present 0b1..A hardware service request for channel 30 is present

◆ DMA_HRS_HRS30 [3/3]

#define DMA_HRS_HRS30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

HRS30 - Hardware Request Status Channel 30 0b0..A hardware service request for channel 30 is not present 0b1..A hardware service request for channel 30 is present

◆ DMA_HRS_HRS31 [1/3]

#define DMA_HRS_HRS31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

HRS31 - Hardware Request Status Channel 31 0b0..A hardware service request for channel 31 is not present 0b1..A hardware service request for channel 31 is present

◆ DMA_HRS_HRS31 [2/3]

#define DMA_HRS_HRS31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

HRS31 - Hardware Request Status Channel 31 0b0..A hardware service request for channel 31 is not present 0b1..A hardware service request for channel 31 is present

◆ DMA_HRS_HRS31 [3/3]

#define DMA_HRS_HRS31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

HRS31 - Hardware Request Status Channel 31 0b0..A hardware service request for channel 31 is not present 0b1..A hardware service request for channel 31 is present

◆ DMA_HRS_HRS4 [1/3]

#define DMA_HRS_HRS4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

◆ DMA_HRS_HRS4 [2/3]

#define DMA_HRS_HRS4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

◆ DMA_HRS_HRS4 [3/3]

#define DMA_HRS_HRS4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

◆ DMA_HRS_HRS5 [1/3]

#define DMA_HRS_HRS5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

◆ DMA_HRS_HRS5 [2/3]

#define DMA_HRS_HRS5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

◆ DMA_HRS_HRS5 [3/3]

#define DMA_HRS_HRS5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

◆ DMA_HRS_HRS6 [1/3]

#define DMA_HRS_HRS6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

◆ DMA_HRS_HRS6 [2/3]

#define DMA_HRS_HRS6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

◆ DMA_HRS_HRS6 [3/3]

#define DMA_HRS_HRS6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

◆ DMA_HRS_HRS7 [1/3]

#define DMA_HRS_HRS7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

◆ DMA_HRS_HRS7 [2/3]

#define DMA_HRS_HRS7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

◆ DMA_HRS_HRS7 [3/3]

#define DMA_HRS_HRS7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

◆ DMA_HRS_HRS8 [1/3]

#define DMA_HRS_HRS8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

◆ DMA_HRS_HRS8 [2/3]

#define DMA_HRS_HRS8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

◆ DMA_HRS_HRS8 [3/3]

#define DMA_HRS_HRS8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

◆ DMA_HRS_HRS9 [1/3]

#define DMA_HRS_HRS9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

◆ DMA_HRS_HRS9 [2/3]

#define DMA_HRS_HRS9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

◆ DMA_HRS_HRS9 [3/3]

#define DMA_HRS_HRS9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

◆ DMA_INT_INT0 [1/3]

#define DMA_INT_INT0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for channel 0 is cleared 0b1..The interrupt request for channel 0 is active

◆ DMA_INT_INT0 [2/3]

#define DMA_INT_INT0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for channel 0 is cleared 0b1..The interrupt request for channel 0 is active

◆ DMA_INT_INT0 [3/3]

#define DMA_INT_INT0 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for channel 0 is cleared 0b1..The interrupt request for channel 0 is active

◆ DMA_INT_INT1 [1/3]

#define DMA_INT_INT1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for channel 1 is cleared 0b1..The interrupt request for channel 1 is active

◆ DMA_INT_INT1 [2/3]

#define DMA_INT_INT1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for channel 1 is cleared 0b1..The interrupt request for channel 1 is active

◆ DMA_INT_INT1 [3/3]

#define DMA_INT_INT1 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for channel 1 is cleared 0b1..The interrupt request for channel 1 is active

◆ DMA_INT_INT10 [1/3]

#define DMA_INT_INT10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for channel 10 is cleared 0b1..The interrupt request for channel 10 is active

◆ DMA_INT_INT10 [2/3]

#define DMA_INT_INT10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for channel 10 is cleared 0b1..The interrupt request for channel 10 is active

◆ DMA_INT_INT10 [3/3]

#define DMA_INT_INT10 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for channel 10 is cleared 0b1..The interrupt request for channel 10 is active

◆ DMA_INT_INT11 [1/3]

#define DMA_INT_INT11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for channel 11 is cleared 0b1..The interrupt request for channel 11 is active

◆ DMA_INT_INT11 [2/3]

#define DMA_INT_INT11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for channel 11 is cleared 0b1..The interrupt request for channel 11 is active

◆ DMA_INT_INT11 [3/3]

#define DMA_INT_INT11 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for channel 11 is cleared 0b1..The interrupt request for channel 11 is active

◆ DMA_INT_INT12 [1/3]

#define DMA_INT_INT12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for channel 12 is cleared 0b1..The interrupt request for channel 12 is active

◆ DMA_INT_INT12 [2/3]

#define DMA_INT_INT12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for channel 12 is cleared 0b1..The interrupt request for channel 12 is active

◆ DMA_INT_INT12 [3/3]

#define DMA_INT_INT12 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for channel 12 is cleared 0b1..The interrupt request for channel 12 is active

◆ DMA_INT_INT13 [1/3]

#define DMA_INT_INT13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for channel 13 is cleared 0b1..The interrupt request for channel 13 is active

◆ DMA_INT_INT13 [2/3]

#define DMA_INT_INT13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for channel 13 is cleared 0b1..The interrupt request for channel 13 is active

◆ DMA_INT_INT13 [3/3]

#define DMA_INT_INT13 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for channel 13 is cleared 0b1..The interrupt request for channel 13 is active

◆ DMA_INT_INT14 [1/3]

#define DMA_INT_INT14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for channel 14 is cleared 0b1..The interrupt request for channel 14 is active

◆ DMA_INT_INT14 [2/3]

#define DMA_INT_INT14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for channel 14 is cleared 0b1..The interrupt request for channel 14 is active

◆ DMA_INT_INT14 [3/3]

#define DMA_INT_INT14 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for channel 14 is cleared 0b1..The interrupt request for channel 14 is active

◆ DMA_INT_INT15 [1/3]

#define DMA_INT_INT15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for channel 15 is cleared 0b1..The interrupt request for channel 15 is active

◆ DMA_INT_INT15 [2/3]

#define DMA_INT_INT15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for channel 15 is cleared 0b1..The interrupt request for channel 15 is active

◆ DMA_INT_INT15 [3/3]

#define DMA_INT_INT15 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for channel 15 is cleared 0b1..The interrupt request for channel 15 is active

◆ DMA_INT_INT16 [1/3]

#define DMA_INT_INT16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

INT16 - Interrupt Request 16 0b0..The interrupt request for channel 16 is cleared 0b1..The interrupt request for channel 16 is active

◆ DMA_INT_INT16 [2/3]

#define DMA_INT_INT16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

INT16 - Interrupt Request 16 0b0..The interrupt request for channel 16 is cleared 0b1..The interrupt request for channel 16 is active

◆ DMA_INT_INT16 [3/3]

#define DMA_INT_INT16 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

INT16 - Interrupt Request 16 0b0..The interrupt request for channel 16 is cleared 0b1..The interrupt request for channel 16 is active

◆ DMA_INT_INT17 [1/3]

#define DMA_INT_INT17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

INT17 - Interrupt Request 17 0b0..The interrupt request for channel 17 is cleared 0b1..The interrupt request for channel 17 is active

◆ DMA_INT_INT17 [2/3]

#define DMA_INT_INT17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

INT17 - Interrupt Request 17 0b0..The interrupt request for channel 17 is cleared 0b1..The interrupt request for channel 17 is active

◆ DMA_INT_INT17 [3/3]

#define DMA_INT_INT17 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

INT17 - Interrupt Request 17 0b0..The interrupt request for channel 17 is cleared 0b1..The interrupt request for channel 17 is active

◆ DMA_INT_INT18 [1/3]

#define DMA_INT_INT18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

INT18 - Interrupt Request 18 0b0..The interrupt request for channel 18 is cleared 0b1..The interrupt request for channel 18 is active

◆ DMA_INT_INT18 [2/3]

#define DMA_INT_INT18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

INT18 - Interrupt Request 18 0b0..The interrupt request for channel 18 is cleared 0b1..The interrupt request for channel 18 is active

◆ DMA_INT_INT18 [3/3]

#define DMA_INT_INT18 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

INT18 - Interrupt Request 18 0b0..The interrupt request for channel 18 is cleared 0b1..The interrupt request for channel 18 is active

◆ DMA_INT_INT19 [1/3]

#define DMA_INT_INT19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

INT19 - Interrupt Request 19 0b0..The interrupt request for channel 19 is cleared 0b1..The interrupt request for channel 19 is active

◆ DMA_INT_INT19 [2/3]

#define DMA_INT_INT19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

INT19 - Interrupt Request 19 0b0..The interrupt request for channel 19 is cleared 0b1..The interrupt request for channel 19 is active

◆ DMA_INT_INT19 [3/3]

#define DMA_INT_INT19 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

INT19 - Interrupt Request 19 0b0..The interrupt request for channel 19 is cleared 0b1..The interrupt request for channel 19 is active

◆ DMA_INT_INT2 [1/3]

#define DMA_INT_INT2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for channel 2 is cleared 0b1..The interrupt request for channel 2 is active

◆ DMA_INT_INT2 [2/3]

#define DMA_INT_INT2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for channel 2 is cleared 0b1..The interrupt request for channel 2 is active

◆ DMA_INT_INT2 [3/3]

#define DMA_INT_INT2 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for channel 2 is cleared 0b1..The interrupt request for channel 2 is active

◆ DMA_INT_INT20 [1/3]

#define DMA_INT_INT20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

INT20 - Interrupt Request 20 0b0..The interrupt request for channel 20 is cleared 0b1..The interrupt request for channel 20 is active

◆ DMA_INT_INT20 [2/3]

#define DMA_INT_INT20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

INT20 - Interrupt Request 20 0b0..The interrupt request for channel 20 is cleared 0b1..The interrupt request for channel 20 is active

◆ DMA_INT_INT20 [3/3]

#define DMA_INT_INT20 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

INT20 - Interrupt Request 20 0b0..The interrupt request for channel 20 is cleared 0b1..The interrupt request for channel 20 is active

◆ DMA_INT_INT21 [1/3]

#define DMA_INT_INT21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

INT21 - Interrupt Request 21 0b0..The interrupt request for channel 21 is cleared 0b1..The interrupt request for channel 21 is active

◆ DMA_INT_INT21 [2/3]

#define DMA_INT_INT21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

INT21 - Interrupt Request 21 0b0..The interrupt request for channel 21 is cleared 0b1..The interrupt request for channel 21 is active

◆ DMA_INT_INT21 [3/3]

#define DMA_INT_INT21 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

INT21 - Interrupt Request 21 0b0..The interrupt request for channel 21 is cleared 0b1..The interrupt request for channel 21 is active

◆ DMA_INT_INT22 [1/3]

#define DMA_INT_INT22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

INT22 - Interrupt Request 22 0b0..The interrupt request for channel 22 is cleared 0b1..The interrupt request for channel 22 is active

◆ DMA_INT_INT22 [2/3]

#define DMA_INT_INT22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

INT22 - Interrupt Request 22 0b0..The interrupt request for channel 22 is cleared 0b1..The interrupt request for channel 22 is active

◆ DMA_INT_INT22 [3/3]

#define DMA_INT_INT22 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

INT22 - Interrupt Request 22 0b0..The interrupt request for channel 22 is cleared 0b1..The interrupt request for channel 22 is active

◆ DMA_INT_INT23 [1/3]

#define DMA_INT_INT23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

INT23 - Interrupt Request 23 0b0..The interrupt request for channel 23 is cleared 0b1..The interrupt request for channel 23 is active

◆ DMA_INT_INT23 [2/3]

#define DMA_INT_INT23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

INT23 - Interrupt Request 23 0b0..The interrupt request for channel 23 is cleared 0b1..The interrupt request for channel 23 is active

◆ DMA_INT_INT23 [3/3]

#define DMA_INT_INT23 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

INT23 - Interrupt Request 23 0b0..The interrupt request for channel 23 is cleared 0b1..The interrupt request for channel 23 is active

◆ DMA_INT_INT24 [1/3]

#define DMA_INT_INT24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

INT24 - Interrupt Request 24 0b0..The interrupt request for channel 24 is cleared 0b1..The interrupt request for channel 24 is active

◆ DMA_INT_INT24 [2/3]

#define DMA_INT_INT24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

INT24 - Interrupt Request 24 0b0..The interrupt request for channel 24 is cleared 0b1..The interrupt request for channel 24 is active

◆ DMA_INT_INT24 [3/3]

#define DMA_INT_INT24 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

INT24 - Interrupt Request 24 0b0..The interrupt request for channel 24 is cleared 0b1..The interrupt request for channel 24 is active

◆ DMA_INT_INT25 [1/3]

#define DMA_INT_INT25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

INT25 - Interrupt Request 25 0b0..The interrupt request for channel 25 is cleared 0b1..The interrupt request for channel 25 is active

◆ DMA_INT_INT25 [2/3]

#define DMA_INT_INT25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

INT25 - Interrupt Request 25 0b0..The interrupt request for channel 25 is cleared 0b1..The interrupt request for channel 25 is active

◆ DMA_INT_INT25 [3/3]

#define DMA_INT_INT25 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

INT25 - Interrupt Request 25 0b0..The interrupt request for channel 25 is cleared 0b1..The interrupt request for channel 25 is active

◆ DMA_INT_INT26 [1/3]

#define DMA_INT_INT26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

INT26 - Interrupt Request 26 0b0..The interrupt request for channel 26 is cleared 0b1..The interrupt request for channel 26 is active

◆ DMA_INT_INT26 [2/3]

#define DMA_INT_INT26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

INT26 - Interrupt Request 26 0b0..The interrupt request for channel 26 is cleared 0b1..The interrupt request for channel 26 is active

◆ DMA_INT_INT26 [3/3]

#define DMA_INT_INT26 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

INT26 - Interrupt Request 26 0b0..The interrupt request for channel 26 is cleared 0b1..The interrupt request for channel 26 is active

◆ DMA_INT_INT27 [1/3]

#define DMA_INT_INT27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

INT27 - Interrupt Request 27 0b0..The interrupt request for channel 27 is cleared 0b1..The interrupt request for channel 27 is active

◆ DMA_INT_INT27 [2/3]

#define DMA_INT_INT27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

INT27 - Interrupt Request 27 0b0..The interrupt request for channel 27 is cleared 0b1..The interrupt request for channel 27 is active

◆ DMA_INT_INT27 [3/3]

#define DMA_INT_INT27 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

INT27 - Interrupt Request 27 0b0..The interrupt request for channel 27 is cleared 0b1..The interrupt request for channel 27 is active

◆ DMA_INT_INT28 [1/3]

#define DMA_INT_INT28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

INT28 - Interrupt Request 28 0b0..The interrupt request for channel 28 is cleared 0b1..The interrupt request for channel 28 is active

◆ DMA_INT_INT28 [2/3]

#define DMA_INT_INT28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

INT28 - Interrupt Request 28 0b0..The interrupt request for channel 28 is cleared 0b1..The interrupt request for channel 28 is active

◆ DMA_INT_INT28 [3/3]

#define DMA_INT_INT28 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

INT28 - Interrupt Request 28 0b0..The interrupt request for channel 28 is cleared 0b1..The interrupt request for channel 28 is active

◆ DMA_INT_INT29 [1/3]

#define DMA_INT_INT29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

INT29 - Interrupt Request 29 0b0..The interrupt request for channel 29 is cleared 0b1..The interrupt request for channel 29 is active

◆ DMA_INT_INT29 [2/3]

#define DMA_INT_INT29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

INT29 - Interrupt Request 29 0b0..The interrupt request for channel 29 is cleared 0b1..The interrupt request for channel 29 is active

◆ DMA_INT_INT29 [3/3]

#define DMA_INT_INT29 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

INT29 - Interrupt Request 29 0b0..The interrupt request for channel 29 is cleared 0b1..The interrupt request for channel 29 is active

◆ DMA_INT_INT3 [1/3]

#define DMA_INT_INT3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for channel 3 is cleared 0b1..The interrupt request for channel 3 is active

◆ DMA_INT_INT3 [2/3]

#define DMA_INT_INT3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for channel 3 is cleared 0b1..The interrupt request for channel 3 is active

◆ DMA_INT_INT3 [3/3]

#define DMA_INT_INT3 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for channel 3 is cleared 0b1..The interrupt request for channel 3 is active

◆ DMA_INT_INT30 [1/3]

#define DMA_INT_INT30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

INT30 - Interrupt Request 30 0b0..The interrupt request for channel 30 is cleared 0b1..The interrupt request for channel 30 is active

◆ DMA_INT_INT30 [2/3]

#define DMA_INT_INT30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

INT30 - Interrupt Request 30 0b0..The interrupt request for channel 30 is cleared 0b1..The interrupt request for channel 30 is active

◆ DMA_INT_INT30 [3/3]

#define DMA_INT_INT30 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

INT30 - Interrupt Request 30 0b0..The interrupt request for channel 30 is cleared 0b1..The interrupt request for channel 30 is active

◆ DMA_INT_INT31 [1/3]

#define DMA_INT_INT31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

INT31 - Interrupt Request 31 0b0..The interrupt request for channel 31 is cleared 0b1..The interrupt request for channel 31 is active

◆ DMA_INT_INT31 [2/3]

#define DMA_INT_INT31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

INT31 - Interrupt Request 31 0b0..The interrupt request for channel 31 is cleared 0b1..The interrupt request for channel 31 is active

◆ DMA_INT_INT31 [3/3]

#define DMA_INT_INT31 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

INT31 - Interrupt Request 31 0b0..The interrupt request for channel 31 is cleared 0b1..The interrupt request for channel 31 is active

◆ DMA_INT_INT4 [1/3]

#define DMA_INT_INT4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for channel 4 is cleared 0b1..The interrupt request for channel 4 is active

◆ DMA_INT_INT4 [2/3]

#define DMA_INT_INT4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for channel 4 is cleared 0b1..The interrupt request for channel 4 is active

◆ DMA_INT_INT4 [3/3]

#define DMA_INT_INT4 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for channel 4 is cleared 0b1..The interrupt request for channel 4 is active

◆ DMA_INT_INT5 [1/3]

#define DMA_INT_INT5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for channel 5 is cleared 0b1..The interrupt request for channel 5 is active

◆ DMA_INT_INT5 [2/3]

#define DMA_INT_INT5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for channel 5 is cleared 0b1..The interrupt request for channel 5 is active

◆ DMA_INT_INT5 [3/3]

#define DMA_INT_INT5 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for channel 5 is cleared 0b1..The interrupt request for channel 5 is active

◆ DMA_INT_INT6 [1/3]

#define DMA_INT_INT6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for channel 6 is cleared 0b1..The interrupt request for channel 6 is active

◆ DMA_INT_INT6 [2/3]

#define DMA_INT_INT6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for channel 6 is cleared 0b1..The interrupt request for channel 6 is active

◆ DMA_INT_INT6 [3/3]

#define DMA_INT_INT6 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for channel 6 is cleared 0b1..The interrupt request for channel 6 is active

◆ DMA_INT_INT7 [1/3]

#define DMA_INT_INT7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for channel 7 is cleared 0b1..The interrupt request for channel 7 is active

◆ DMA_INT_INT7 [2/3]

#define DMA_INT_INT7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for channel 7 is cleared 0b1..The interrupt request for channel 7 is active

◆ DMA_INT_INT7 [3/3]

#define DMA_INT_INT7 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for channel 7 is cleared 0b1..The interrupt request for channel 7 is active

◆ DMA_INT_INT8 [1/3]

#define DMA_INT_INT8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for channel 8 is cleared 0b1..The interrupt request for channel 8 is active

◆ DMA_INT_INT8 [2/3]

#define DMA_INT_INT8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for channel 8 is cleared 0b1..The interrupt request for channel 8 is active

◆ DMA_INT_INT8 [3/3]

#define DMA_INT_INT8 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for channel 8 is cleared 0b1..The interrupt request for channel 8 is active

◆ DMA_INT_INT9 [1/3]

#define DMA_INT_INT9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for channel 9 is cleared 0b1..The interrupt request for channel 9 is active

◆ DMA_INT_INT9 [2/3]

#define DMA_INT_INT9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for channel 9 is cleared 0b1..The interrupt request for channel 9 is active

◆ DMA_INT_INT9 [3/3]

#define DMA_INT_INT9 ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for channel 9 is cleared 0b1..The interrupt request for channel 9 is active

◆ DMA_NBYTES_MLNO_NBYTES [1/3]

#define DMA_NBYTES_MLNO_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLNO_NBYTES [2/3]

#define DMA_NBYTES_MLNO_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLNO_NBYTES [3/3]

#define DMA_NBYTES_MLNO_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLOFFNO_DMLOE [1/3]

#define DMA_NBYTES_MLOFFNO_DMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFNO_DMLOE [2/3]

#define DMA_NBYTES_MLOFFNO_DMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFNO_DMLOE [3/3]

#define DMA_NBYTES_MLOFFNO_DMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFNO_NBYTES [1/3]

#define DMA_NBYTES_MLOFFNO_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLOFFNO_NBYTES [2/3]

#define DMA_NBYTES_MLOFFNO_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLOFFNO_NBYTES [3/3]

#define DMA_NBYTES_MLOFFNO_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLOFFNO_SMLOE [1/3]

#define DMA_NBYTES_MLOFFNO_SMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFNO_SMLOE [2/3]

#define DMA_NBYTES_MLOFFNO_SMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFNO_SMLOE [3/3]

#define DMA_NBYTES_MLOFFNO_SMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFYES_DMLOE [1/3]

#define DMA_NBYTES_MLOFFYES_DMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFYES_DMLOE [2/3]

#define DMA_NBYTES_MLOFFYES_DMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFYES_DMLOE [3/3]

#define DMA_NBYTES_MLOFFYES_DMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFYES_MLOFF [1/3]

#define DMA_NBYTES_MLOFFYES_MLOFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

◆ DMA_NBYTES_MLOFFYES_MLOFF [2/3]

#define DMA_NBYTES_MLOFFYES_MLOFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

◆ DMA_NBYTES_MLOFFYES_MLOFF [3/3]

#define DMA_NBYTES_MLOFFYES_MLOFF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

◆ DMA_NBYTES_MLOFFYES_NBYTES [1/3]

#define DMA_NBYTES_MLOFFYES_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLOFFYES_NBYTES [2/3]

#define DMA_NBYTES_MLOFFYES_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLOFFYES_NBYTES [3/3]

#define DMA_NBYTES_MLOFFYES_NBYTES ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

NBYTES - Minor Byte Transfer Count

◆ DMA_NBYTES_MLOFFYES_SMLOE [1/3]

#define DMA_NBYTES_MLOFFYES_SMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFYES_SMLOE [2/3]

#define DMA_NBYTES_MLOFFYES_SMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFYES_SMLOE [3/3]

#define DMA_NBYTES_MLOFFYES_SMLOE ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_SADDR_SADDR [1/3]

#define DMA_SADDR_SADDR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

SADDR - Source Address

◆ DMA_SADDR_SADDR [2/3]

#define DMA_SADDR_SADDR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

SADDR - Source Address

◆ DMA_SADDR_SADDR [3/3]

#define DMA_SADDR_SADDR ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

SADDR - Source Address

◆ DMA_SEEI_NOP [1/3]

#define DMA_SEEI_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_SEEI_NOP [2/3]

#define DMA_SEEI_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_SEEI_NOP [3/3]

#define DMA_SEEI_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_SEEI_SAEE [1/3]

#define DMA_SEEI_SAEE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Set All Enable Error Interrupts 0b0..Write 1 only to the EEI field specified in the SEEI field 0b1..Writes 1 to all fields in EEI

◆ DMA_SEEI_SAEE [2/3]

#define DMA_SEEI_SAEE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Set All Enable Error Interrupts 0b0..Write 1 only to the EEI field specified in the SEEI field 0b1..Writes 1 to all fields in EEI

◆ DMA_SEEI_SAEE [3/3]

#define DMA_SEEI_SAEE ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Set All Enable Error Interrupts 0b0..Write 1 only to the EEI field specified in the SEEI field 0b1..Writes 1 to all fields in EEI

◆ DMA_SEEI_SEEI [1/3]

#define DMA_SEEI_SEEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

SEEI - Set Enable Error Interrupt

◆ DMA_SEEI_SEEI [2/3]

#define DMA_SEEI_SEEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

SEEI - Set Enable Error Interrupt

◆ DMA_SEEI_SEEI [3/3]

#define DMA_SEEI_SEEI ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

SEEI - Set Enable Error Interrupt

◆ DMA_SERQ_NOP [1/3]

#define DMA_SERQ_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_SERQ_NOP [2/3]

#define DMA_SERQ_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_SERQ_NOP [3/3]

#define DMA_SERQ_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation, ignore the other fields in this register

◆ DMA_SERQ_SAER [1/3]

#define DMA_SERQ_SAER ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Write 1 to only the ERQ field specified in the SERQ field 0b1..Write 1 to all fields in ERQ

◆ DMA_SERQ_SAER [2/3]

#define DMA_SERQ_SAER ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Write 1 to only the ERQ field specified in the SERQ field 0b1..Write 1 to all fields in ERQ

◆ DMA_SERQ_SAER [3/3]

#define DMA_SERQ_SAER ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Write 1 to only the ERQ field specified in the SERQ field 0b1..Write 1 to all fields in ERQ

◆ DMA_SERQ_SERQ [1/3]

#define DMA_SERQ_SERQ ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

SERQ - Set Enable Request

◆ DMA_SERQ_SERQ [2/3]

#define DMA_SERQ_SERQ ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

SERQ - Set Enable Request

◆ DMA_SERQ_SERQ [3/3]

#define DMA_SERQ_SERQ ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

SERQ - Set Enable Request

◆ DMA_SLAST_SLAST [1/3]

#define DMA_SLAST_SLAST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

SLAST - Last Source Address Adjustment

◆ DMA_SLAST_SLAST [2/3]

#define DMA_SLAST_SLAST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

SLAST - Last Source Address Adjustment

◆ DMA_SLAST_SLAST [3/3]

#define DMA_SLAST_SLAST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

SLAST - Last Source Address Adjustment

◆ DMA_SOFF_SOFF [1/3]

#define DMA_SOFF_SOFF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

SOFF - Source address signed offset

◆ DMA_SOFF_SOFF [2/3]

#define DMA_SOFF_SOFF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

SOFF - Source address signed offset

◆ DMA_SOFF_SOFF [3/3]

#define DMA_SOFF_SOFF ( x )

Value:

(((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

SOFF - Source address signed offset

◆ DMA_SSRT_NOP [1/3]

#define DMA_SSRT_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_SSRT_NOP [2/3]

#define DMA_SSRT_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_SSRT_NOP [3/3]

#define DMA_SSRT_NOP ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op Enable 0b0..Normal operation 0b1..No operation; all other fields in this register are ignored.

◆ DMA_SSRT_SAST [1/3]

#define DMA_SSRT_SAST ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START fields (activates all channels) 0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field 0b1..Write 1 to all bits in TCDn_CSR[START]

◆ DMA_SSRT_SAST [2/3]

#define DMA_SSRT_SAST ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START fields (activates all channels) 0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field 0b1..Write 1 to all bits in TCDn_CSR[START]

◆ DMA_SSRT_SAST [3/3]

#define DMA_SSRT_SAST ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START fields (activates all channels) 0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field 0b1..Write 1 to all bits in TCDn_CSR[START]

◆ DMA_SSRT_SSRT [1/3]

#define DMA_SSRT_SSRT ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

SSRT - Set START field

◆ DMA_SSRT_SSRT [2/3]

#define DMA_SSRT_SSRT ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

SSRT - Set START field

◆ DMA_SSRT_SSRT [3/3]

#define DMA_SSRT_SSRT ( x )

Value:

(((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

SSRT - Set START field

◆ LPSPI_CR_DBGEN [1/3]

#define LPSPI_CR_DBGEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..LPSPI module is disabled in debug mode 0b1..LPSPI module is enabled in debug mode

◆ LPSPI_CR_DBGEN [2/3]

#define LPSPI_CR_DBGEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..LPSPI module is disabled in debug mode 0b1..LPSPI module is enabled in debug mode

◆ LPSPI_CR_DBGEN [3/3]

#define LPSPI_CR_DBGEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..LPSPI module is disabled in debug mode 0b1..LPSPI module is enabled in debug mode

◆ LPSPI_CR_DOZEN [1/3]

#define LPSPI_CR_DOZEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

DOZEN - Doze Mode Enable 0b0..LPSPI module is enabled in Doze mode 0b1..LPSPI module is disabled in Doze mode

◆ LPSPI_CR_DOZEN [2/3]

#define LPSPI_CR_DOZEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

DOZEN - Doze Mode Enable 0b0..LPSPI module is enabled in Doze mode 0b1..LPSPI module is disabled in Doze mode

◆ LPSPI_CR_DOZEN [3/3]

#define LPSPI_CR_DOZEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

DOZEN - Doze Mode Enable 0b0..LPSPI module is enabled in Doze mode 0b1..LPSPI module is disabled in Doze mode

◆ LPSPI_CR_MEN [1/3]

#define LPSPI_CR_MEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

MEN - Module Enable 0b0..Module is disabled 0b1..Module is enabled

◆ LPSPI_CR_MEN [2/3]

#define LPSPI_CR_MEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

MEN - Module Enable 0b0..Module is disabled 0b1..Module is enabled

◆ LPSPI_CR_MEN [3/3]

#define LPSPI_CR_MEN ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

MEN - Module Enable 0b0..Module is disabled 0b1..Module is enabled

◆ LPSPI_CR_RRF [1/3]

#define LPSPI_CR_RRF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Receive FIFO is reset

RRF - Reset Receive FIFO 0b0..No effect 0b1..Reset the Receive FIFO. The register bit always reads zero.

◆ LPSPI_CR_RRF [2/3]

#define LPSPI_CR_RRF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Reset the Receive FIFO. The register bit always reads zero.

◆ LPSPI_CR_RRF [3/3]

#define LPSPI_CR_RRF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)

RRF - Reset Receive FIFO 0b0..No effect 0b1..Reset the Receive FIFO. The register bit always reads zero.

◆ LPSPI_CR_RST [1/3]

#define LPSPI_CR_RST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

RST - Software Reset 0b0..Module is not reset 0b1..Module is reset

◆ LPSPI_CR_RST [2/3]

#define LPSPI_CR_RST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

RST - Software Reset 0b0..Module is not reset 0b1..Module is reset

◆ LPSPI_CR_RST [3/3]

#define LPSPI_CR_RST ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

RST - Software Reset 0b0..Module is not reset 0b1..Module is reset

◆ LPSPI_CR_RTF [1/3]

#define LPSPI_CR_RTF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Transmit FIFO is reset

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Reset the Transmit FIFO. The register bit always reads zero.

◆ LPSPI_CR_RTF [2/3]

#define LPSPI_CR_RTF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Reset the Transmit FIFO. The register bit always reads zero.

◆ LPSPI_CR_RTF [3/3]

#define LPSPI_CR_RTF ( x )

Value:

(((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

RTF - Reset Transmit FIFO 0b0..No effect 0b1..Reset the Transmit FIFO. The register bit always reads zero.

Macros

CR - Control

ES - Error Status

ERQ - Enable Request

EEI - Enable Error Interrupt

CEEI - Clear Enable Error Interrupt

SEEI - Set Enable Error Interrupt

CERQ - Clear Enable Request

SERQ - Set Enable Request

CDNE - Clear DONE Status Bit

SSRT - Set START Bit

CERR - Clear Error

CINT - Clear Interrupt Request

INT - Interrupt Request

ERR - Error

HRS - Hardware Request Status

EARS - Enable Asynchronous Request in Stop

DCHPRI3 - Channel Priority

DCHPRI2 - Channel Priority

DCHPRI1 - Channel Priority

DCHPRI0 - Channel Priority

DCHPRI7 - Channel Priority

DCHPRI6 - Channel Priority

DCHPRI5 - Channel Priority

DCHPRI4 - Channel Priority

DCHPRI11 - Channel Priority

DCHPRI10 - Channel Priority

DCHPRI9 - Channel Priority

DCHPRI8 - Channel Priority

DCHPRI15 - Channel Priority

DCHPRI14 - Channel Priority

DCHPRI13 - Channel Priority

DCHPRI12 - Channel Priority

DCHPRI19 - Channel Priority

DCHPRI18 - Channel Priority

DCHPRI17 - Channel Priority

DCHPRI16 - Channel Priority

DCHPRI23 - Channel Priority

DCHPRI22 - Channel Priority

DCHPRI21 - Channel Priority

DCHPRI20 - Channel Priority

DCHPRI27 - Channel Priority

DCHPRI26 - Channel Priority

DCHPRI25 - Channel Priority

DCHPRI24 - Channel Priority

DCHPRI31 - Channel Priority

DCHPRI30 - Channel Priority

DCHPRI29 - Channel Priority

DCHPRI28 - Channel Priority

SADDR - TCD Source Address

SOFF - TCD Signed Source Address Offset

ATTR - TCD Transfer Attributes

NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)

NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)

NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)

SLAST - TCD Last Source Address Adjustment

DADDR - TCD Destination Address

DOFF - TCD Signed Destination Address Offset

CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address

CSR - TCD Control and Status

BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

Detailed Description

Macro Definition Documentation

◆ DMA_ATTR_DMOD [1/3]

◆ DMA_ATTR_DMOD [2/3]

◆ DMA_ATTR_DMOD [3/3]

◆ DMA_ATTR_DSIZE [1/3]

◆ DMA_ATTR_DSIZE [2/3]

◆ DMA_ATTR_DSIZE [3/3]

◆ DMA_ATTR_SMOD [1/3]

◆ DMA_ATTR_SMOD [2/3]

◆ DMA_ATTR_SMOD [3/3]

◆ DMA_ATTR_SSIZE [1/3]

◆ DMA_ATTR_SSIZE [2/3]

◆ DMA_ATTR_SSIZE [3/3]

◆ DMA_BITER_ELINKNO_BITER [1/3]

◆ DMA_BITER_ELINKNO_BITER [2/3]