DFSDM Private Macros

Macros
#define	IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)
#define	IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER)
#define	IS_DFSDM_CHANNEL_INPUT(INPUT)
#define	IS_DFSDM_CHANNEL_DATA_PACKING(MODE)
#define	IS_DFSDM_CHANNEL_INPUT_PINS(PINS)
#define	IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)
#define	IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)
#define	IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)
#define	IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)
#define	IS_DFSDM_CHANNEL_OFFSET(VALUE)
#define	IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)
#define	IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)
#define	IS_DFSDM_FILTER_REG_TRIGGER(TRIG)
#define	IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)
#define	IS_DFSDM_FILTER_EXT_TRIG(TRIG)
#define	IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)
#define	IS_DFSDM_FILTER_SINC_ORDER(ORDER)
#define	IS_DFSDM_FILTER_OVS_RATIO(RATIO)
#define	IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)
#define	IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)
#define	IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)
#define	IS_DFSDM_BREAK_SIGNALS(VALUE)
#define	IS_DFSDM_REGULAR_CHANNEL(CHANNEL)
#define	IS_DFSDM_INJECTED_CHANNEL(CHANNEL)
#define	IS_DFSDM_CONTINUOUS_MODE(MODE)

Detailed Description

Macro Definition Documentation

IS_DFSDM_BREAK_SIGNALS

#define IS_DFSDM_BREAK_SIGNALS

(

VALUE

)

Value:

((VALUE) <= 0xFU)

IS_DFSDM_CHANNEL_DATA_PACKING

#define IS_DFSDM_CHANNEL_DATA_PACKING

(

MODE

)

Value:

(((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
((MODE) == DFSDM_CHANNEL_DUAL_MODE))

IS_DFSDM_CHANNEL_FILTER_ORDER

#define IS_DFSDM_CHANNEL_FILTER_ORDER

(

ORDER

)

Value:

(((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))

IS_DFSDM_CHANNEL_FILTER_OVS_RATIO

#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO

(

RATIO

)

Value:

((1U <= (RATIO)) && ((RATIO) <= 32U))

IS_DFSDM_CHANNEL_INPUT

#define IS_DFSDM_CHANNEL_INPUT

(

INPUT

)

Value:

(((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))

IS_DFSDM_CHANNEL_INPUT_PINS

#define IS_DFSDM_CHANNEL_INPUT_PINS

(

PINS

)

Value:

(((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))

IS_DFSDM_CHANNEL_OFFSET

#define IS_DFSDM_CHANNEL_OFFSET

(

VALUE

)

Value:

((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

IS_DFSDM_CHANNEL_OUTPUT_CLOCK

#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK

(

CLOCK

)

Value:

(((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))

IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER

#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER

(

DIVIDER

)

Value:

((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))

IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT

#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT

(

VALUE

)

Value:

((VALUE) <= 0x1FU)

IS_DFSDM_CHANNEL_SCD_THRESHOLD

#define IS_DFSDM_CHANNEL_SCD_THRESHOLD

(

VALUE

)

Value:

((VALUE) <= 0xFFU)

IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE

#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE

(

MODE

)

Value:

(((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))

IS_DFSDM_CHANNEL_SPI_CLOCK

#define IS_DFSDM_CHANNEL_SPI_CLOCK

(

TYPE

)

Value:

(((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))

IS_DFSDM_CONTINUOUS_MODE

#define IS_DFSDM_CONTINUOUS_MODE

(

MODE

)

Value:

(((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
((MODE) == DFSDM_CONTINUOUS_CONV_ON))

IS_DFSDM_FILTER_AWD_DATA_SOURCE

#define IS_DFSDM_FILTER_AWD_DATA_SOURCE

(

DATA

)

Value:

(((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))

IS_DFSDM_FILTER_AWD_THRESHOLD

#define IS_DFSDM_FILTER_AWD_THRESHOLD

(

VALUE

)

Value:

((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

IS_DFSDM_FILTER_EXT_TRIG

#define IS_DFSDM_FILTER_EXT_TRIG

(

TRIG

)

Value:

(((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT))

IS_DFSDM_FILTER_EXT_TRIG_EDGE

#define IS_DFSDM_FILTER_EXT_TRIG_EDGE

(

EDGE

)

Value:

(((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))

IS_DFSDM_FILTER_INJ_TRIGGER

#define IS_DFSDM_FILTER_INJ_TRIGGER

(

TRIG

)

Value:

(((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
((TRIG) == DFSDM_FILTER_EXT_TRIGGER))

IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO

#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO

(

RATIO

)

Value:

((1U <= (RATIO)) && ((RATIO) <= 256U))

IS_DFSDM_FILTER_OVS_RATIO

#define IS_DFSDM_FILTER_OVS_RATIO

(

RATIO

)

Value:

((1U <= (RATIO)) && ((RATIO) <= 1024U))

IS_DFSDM_FILTER_REG_TRIGGER

#define IS_DFSDM_FILTER_REG_TRIGGER

(

TRIG

)

Value:

(((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))

IS_DFSDM_FILTER_SINC_ORDER

#define IS_DFSDM_FILTER_SINC_ORDER

(

ORDER

)

Value:

(((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC5_ORDER))

IS_DFSDM_INJECTED_CHANNEL

#define IS_DFSDM_INJECTED_CHANNEL

(

CHANNEL

)

Value:

(((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))

IS_DFSDM_REGULAR_CHANNEL

#define IS_DFSDM_REGULAR_CHANNEL

(

CHANNEL

)

Value:

(((CHANNEL) == DFSDM_CHANNEL_0)  || \
((CHANNEL) == DFSDM_CHANNEL_1)  || \
((CHANNEL) == DFSDM_CHANNEL_2)  || \
((CHANNEL) == DFSDM_CHANNEL_3)  || \
((CHANNEL) == DFSDM_CHANNEL_4)  || \
((CHANNEL) == DFSDM_CHANNEL_5)  || \
((CHANNEL) == DFSDM_CHANNEL_6)  || \
((CHANNEL) == DFSDM_CHANNEL_7))