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RTEMS 6.3
|
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RTEMS 6.3
|
Macros | |
| #define | CSI_CR_COUNT (256U) |
| #define | CSI_CR_COUNT (256U) |
CR1 - CSI Control Register 1 | |
| #define | CSI_CR1_PIXEL_BIT_MASK (0x1U) |
| #define | CSI_CR1_PIXEL_BIT_SHIFT (0U) |
| #define | CSI_CR1_PIXEL_BIT(x) |
| #define | CSI_CR1_REDGE_MASK (0x2U) |
| #define | CSI_CR1_REDGE_SHIFT (1U) |
| #define | CSI_CR1_REDGE(x) |
| #define | CSI_CR1_INV_PCLK_MASK (0x4U) |
| #define | CSI_CR1_INV_PCLK_SHIFT (2U) |
| #define | CSI_CR1_INV_PCLK(x) |
| #define | CSI_CR1_INV_DATA_MASK (0x8U) |
| #define | CSI_CR1_INV_DATA_SHIFT (3U) |
| #define | CSI_CR1_INV_DATA(x) |
| #define | CSI_CR1_GCLK_MODE_MASK (0x10U) |
| #define | CSI_CR1_GCLK_MODE_SHIFT (4U) |
| #define | CSI_CR1_GCLK_MODE(x) |
| #define | CSI_CR1_CLR_RXFIFO_MASK (0x20U) |
| #define | CSI_CR1_CLR_RXFIFO_SHIFT (5U) |
| #define | CSI_CR1_CLR_RXFIFO(x) |
| #define | CSI_CR1_CLR_STATFIFO_MASK (0x40U) |
| #define | CSI_CR1_CLR_STATFIFO_SHIFT (6U) |
| #define | CSI_CR1_CLR_STATFIFO(x) |
| #define | CSI_CR1_PACK_DIR_MASK (0x80U) |
| #define | CSI_CR1_PACK_DIR_SHIFT (7U) |
| #define | CSI_CR1_PACK_DIR(x) |
| #define | CSI_CR1_FCC_MASK (0x100U) |
| #define | CSI_CR1_FCC_SHIFT (8U) |
| #define | CSI_CR1_FCC(x) |
| #define | CSI_CR1_CCIR_EN_MASK (0x400U) |
| #define | CSI_CR1_CCIR_EN_SHIFT (10U) |
| #define | CSI_CR1_CCIR_EN(x) |
| #define | CSI_CR1_HSYNC_POL_MASK (0x800U) |
| #define | CSI_CR1_HSYNC_POL_SHIFT (11U) |
| #define | CSI_CR1_HSYNC_POL(x) |
| #define | CSI_CR1_SOF_INTEN_MASK (0x10000U) |
| #define | CSI_CR1_SOF_INTEN_SHIFT (16U) |
| #define | CSI_CR1_SOF_INTEN(x) |
| #define | CSI_CR1_SOF_POL_MASK (0x20000U) |
| #define | CSI_CR1_SOF_POL_SHIFT (17U) |
| #define | CSI_CR1_SOF_POL(x) |
| #define | CSI_CR1_RXFF_INTEN_MASK (0x40000U) |
| #define | CSI_CR1_RXFF_INTEN_SHIFT (18U) |
| #define | CSI_CR1_RXFF_INTEN(x) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT (19U) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT (20U) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_STATFF_INTEN_MASK (0x200000U) |
| #define | CSI_CR1_STATFF_INTEN_SHIFT (21U) |
| #define | CSI_CR1_STATFF_INTEN(x) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT (22U) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_RF_OR_INTEN_MASK (0x1000000U) |
| #define | CSI_CR1_RF_OR_INTEN_SHIFT (24U) |
| #define | CSI_CR1_RF_OR_INTEN(x) |
| #define | CSI_CR1_SF_OR_INTEN_MASK (0x2000000U) |
| #define | CSI_CR1_SF_OR_INTEN_SHIFT (25U) |
| #define | CSI_CR1_SF_OR_INTEN(x) |
| #define | CSI_CR1_COF_INT_EN_MASK (0x4000000U) |
| #define | CSI_CR1_COF_INT_EN_SHIFT (26U) |
| #define | CSI_CR1_COF_INT_EN(x) |
| #define | CSI_CR1_EOF_INT_EN_MASK (0x20000000U) |
| #define | CSI_CR1_EOF_INT_EN_SHIFT (29U) |
| #define | CSI_CR1_EOF_INT_EN(x) |
| #define | CSI_CR1_EXT_VSYNC_MASK (0x40000000U) |
| #define | CSI_CR1_EXT_VSYNC_SHIFT (30U) |
| #define | CSI_CR1_EXT_VSYNC(x) |
| #define | CSI_CR1_SWAP16_EN_MASK (0x80000000U) |
| #define | CSI_CR1_SWAP16_EN_SHIFT (31U) |
| #define | CSI_CR1_SWAP16_EN(x) |
| #define | CSI_CR1_PIXEL_BIT_MASK (0x1U) |
| #define | CSI_CR1_PIXEL_BIT_SHIFT (0U) |
| #define | CSI_CR1_PIXEL_BIT(x) |
| #define | CSI_CR1_REDGE_MASK (0x2U) |
| #define | CSI_CR1_REDGE_SHIFT (1U) |
| #define | CSI_CR1_REDGE(x) |
| #define | CSI_CR1_INV_PCLK_MASK (0x4U) |
| #define | CSI_CR1_INV_PCLK_SHIFT (2U) |
| #define | CSI_CR1_INV_PCLK(x) |
| #define | CSI_CR1_INV_DATA_MASK (0x8U) |
| #define | CSI_CR1_INV_DATA_SHIFT (3U) |
| #define | CSI_CR1_INV_DATA(x) |
| #define | CSI_CR1_GCLK_MODE_MASK (0x10U) |
| #define | CSI_CR1_GCLK_MODE_SHIFT (4U) |
| #define | CSI_CR1_GCLK_MODE(x) |
| #define | CSI_CR1_CLR_RXFIFO_MASK (0x20U) |
| #define | CSI_CR1_CLR_RXFIFO_SHIFT (5U) |
| #define | CSI_CR1_CLR_RXFIFO(x) |
| #define | CSI_CR1_CLR_STATFIFO_MASK (0x40U) |
| #define | CSI_CR1_CLR_STATFIFO_SHIFT (6U) |
| #define | CSI_CR1_CLR_STATFIFO(x) |
| #define | CSI_CR1_PACK_DIR_MASK (0x80U) |
| #define | CSI_CR1_PACK_DIR_SHIFT (7U) |
| #define | CSI_CR1_PACK_DIR(x) |
| #define | CSI_CR1_FCC_MASK (0x100U) |
| #define | CSI_CR1_FCC_SHIFT (8U) |
| #define | CSI_CR1_FCC(x) |
| #define | CSI_CR1_CCIR_EN_MASK (0x400U) |
| #define | CSI_CR1_CCIR_EN_SHIFT (10U) |
| #define | CSI_CR1_CCIR_EN(x) |
| #define | CSI_CR1_HSYNC_POL_MASK (0x800U) |
| #define | CSI_CR1_HSYNC_POL_SHIFT (11U) |
| #define | CSI_CR1_HSYNC_POL(x) |
| #define | CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK (0x1000U) |
| #define | CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT (12U) |
| #define | CSI_CR1_HISTOGRAM_CALC_DONE_IE(x) |
| #define | CSI_CR1_SOF_INTEN_MASK (0x10000U) |
| #define | CSI_CR1_SOF_INTEN_SHIFT (16U) |
| #define | CSI_CR1_SOF_INTEN(x) |
| #define | CSI_CR1_SOF_POL_MASK (0x20000U) |
| #define | CSI_CR1_SOF_POL_SHIFT (17U) |
| #define | CSI_CR1_SOF_POL(x) |
| #define | CSI_CR1_RXFF_INTEN_MASK (0x40000U) |
| #define | CSI_CR1_RXFF_INTEN_SHIFT (18U) |
| #define | CSI_CR1_RXFF_INTEN(x) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT (19U) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT (20U) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_STATFF_INTEN_MASK (0x200000U) |
| #define | CSI_CR1_STATFF_INTEN_SHIFT (21U) |
| #define | CSI_CR1_STATFF_INTEN(x) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT (22U) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_RF_OR_INTEN_MASK (0x1000000U) |
| #define | CSI_CR1_RF_OR_INTEN_SHIFT (24U) |
| #define | CSI_CR1_RF_OR_INTEN(x) |
| #define | CSI_CR1_SF_OR_INTEN_MASK (0x2000000U) |
| #define | CSI_CR1_SF_OR_INTEN_SHIFT (25U) |
| #define | CSI_CR1_SF_OR_INTEN(x) |
| #define | CSI_CR1_COF_INT_EN_MASK (0x4000000U) |
| #define | CSI_CR1_COF_INT_EN_SHIFT (26U) |
| #define | CSI_CR1_COF_INT_EN(x) |
| #define | CSI_CR1_VIDEO_MODE_MASK (0x8000000U) |
| #define | CSI_CR1_VIDEO_MODE_SHIFT (27U) |
| #define | CSI_CR1_VIDEO_MODE(x) |
| #define | CSI_CR1_EOF_INT_EN_MASK (0x20000000U) |
| #define | CSI_CR1_EOF_INT_EN_SHIFT (29U) |
| #define | CSI_CR1_EOF_INT_EN(x) |
| #define | CSI_CR1_EXT_VSYNC_MASK (0x40000000U) |
| #define | CSI_CR1_EXT_VSYNC_SHIFT (30U) |
| #define | CSI_CR1_EXT_VSYNC(x) |
| #define | CSI_CR1_SWAP16_EN_MASK (0x80000000U) |
| #define | CSI_CR1_SWAP16_EN_SHIFT (31U) |
| #define | CSI_CR1_SWAP16_EN(x) |
| #define | CSI_CR1_PIXEL_BIT_MASK (0x1U) |
| #define | CSI_CR1_PIXEL_BIT_SHIFT (0U) |
| #define | CSI_CR1_PIXEL_BIT(x) |
| #define | CSI_CR1_REDGE_MASK (0x2U) |
| #define | CSI_CR1_REDGE_SHIFT (1U) |
| #define | CSI_CR1_REDGE(x) |
| #define | CSI_CR1_INV_PCLK_MASK (0x4U) |
| #define | CSI_CR1_INV_PCLK_SHIFT (2U) |
| #define | CSI_CR1_INV_PCLK(x) |
| #define | CSI_CR1_INV_DATA_MASK (0x8U) |
| #define | CSI_CR1_INV_DATA_SHIFT (3U) |
| #define | CSI_CR1_INV_DATA(x) |
| #define | CSI_CR1_GCLK_MODE_MASK (0x10U) |
| #define | CSI_CR1_GCLK_MODE_SHIFT (4U) |
| #define | CSI_CR1_GCLK_MODE(x) |
| #define | CSI_CR1_CLR_RXFIFO_MASK (0x20U) |
| #define | CSI_CR1_CLR_RXFIFO_SHIFT (5U) |
| #define | CSI_CR1_CLR_RXFIFO(x) |
| #define | CSI_CR1_CLR_STATFIFO_MASK (0x40U) |
| #define | CSI_CR1_CLR_STATFIFO_SHIFT (6U) |
| #define | CSI_CR1_CLR_STATFIFO(x) |
| #define | CSI_CR1_PACK_DIR_MASK (0x80U) |
| #define | CSI_CR1_PACK_DIR_SHIFT (7U) |
| #define | CSI_CR1_PACK_DIR(x) |
| #define | CSI_CR1_FCC_MASK (0x100U) |
| #define | CSI_CR1_FCC_SHIFT (8U) |
| #define | CSI_CR1_FCC(x) |
| #define | CSI_CR1_CCIR_EN_MASK (0x400U) |
| #define | CSI_CR1_CCIR_EN_SHIFT (10U) |
| #define | CSI_CR1_CCIR_EN(x) |
| #define | CSI_CR1_HSYNC_POL_MASK (0x800U) |
| #define | CSI_CR1_HSYNC_POL_SHIFT (11U) |
| #define | CSI_CR1_HSYNC_POL(x) |
| #define | CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK (0x1000U) |
| #define | CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT (12U) |
| #define | CSI_CR1_HISTOGRAM_CALC_DONE_IE(x) |
| #define | CSI_CR1_SOF_INTEN_MASK (0x10000U) |
| #define | CSI_CR1_SOF_INTEN_SHIFT (16U) |
| #define | CSI_CR1_SOF_INTEN(x) |
| #define | CSI_CR1_SOF_POL_MASK (0x20000U) |
| #define | CSI_CR1_SOF_POL_SHIFT (17U) |
| #define | CSI_CR1_SOF_POL(x) |
| #define | CSI_CR1_RXFF_INTEN_MASK (0x40000U) |
| #define | CSI_CR1_RXFF_INTEN_SHIFT (18U) |
| #define | CSI_CR1_RXFF_INTEN(x) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT (19U) |
| #define | CSI_CR1_FB1_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT (20U) |
| #define | CSI_CR1_FB2_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_STATFF_INTEN_MASK (0x200000U) |
| #define | CSI_CR1_STATFF_INTEN_SHIFT (21U) |
| #define | CSI_CR1_STATFF_INTEN(x) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT (22U) |
| #define | CSI_CR1_SFF_DMA_DONE_INTEN(x) |
| #define | CSI_CR1_RF_OR_INTEN_MASK (0x1000000U) |
| #define | CSI_CR1_RF_OR_INTEN_SHIFT (24U) |
| #define | CSI_CR1_RF_OR_INTEN(x) |
| #define | CSI_CR1_SF_OR_INTEN_MASK (0x2000000U) |
| #define | CSI_CR1_SF_OR_INTEN_SHIFT (25U) |
| #define | CSI_CR1_SF_OR_INTEN(x) |
| #define | CSI_CR1_COF_INT_EN_MASK (0x4000000U) |
| #define | CSI_CR1_COF_INT_EN_SHIFT (26U) |
| #define | CSI_CR1_COF_INT_EN(x) |
| #define | CSI_CR1_VIDEO_MODE_MASK (0x8000000U) |
| #define | CSI_CR1_VIDEO_MODE_SHIFT (27U) |
| #define | CSI_CR1_VIDEO_MODE(x) |
| #define | CSI_CR1_EOF_INT_EN_MASK (0x20000000U) |
| #define | CSI_CR1_EOF_INT_EN_SHIFT (29U) |
| #define | CSI_CR1_EOF_INT_EN(x) |
| #define | CSI_CR1_EXT_VSYNC_MASK (0x40000000U) |
| #define | CSI_CR1_EXT_VSYNC_SHIFT (30U) |
| #define | CSI_CR1_EXT_VSYNC(x) |
| #define | CSI_CR1_SWAP16_EN_MASK (0x80000000U) |
| #define | CSI_CR1_SWAP16_EN_SHIFT (31U) |
| #define | CSI_CR1_SWAP16_EN(x) |
CR1 - CSI Control Register 1 | |
| #define | CSI_CR1_CCIR_MODE_MASK (0x8000000U) |
| #define | CSI_CR1_CCIR_MODE_SHIFT (27U) |
| #define | CSI_CR1_CCIR_MODE(x) |
| #define | CSI_CR1_PrP_IF_EN_MASK (0x10000000U) |
| #define | CSI_CR1_PrP_IF_EN_SHIFT (28U) |
| #define | CSI_CR1_PrP_IF_EN(x) |
CR2 - CSI Control Register 2 | |
| #define | CSI_CR2_HSC_MASK (0xFFU) |
| #define | CSI_CR2_HSC_SHIFT (0U) |
| #define | CSI_CR2_HSC(x) |
| #define | CSI_CR2_VSC_MASK (0xFF00U) |
| #define | CSI_CR2_VSC_SHIFT (8U) |
| #define | CSI_CR2_VSC(x) |
| #define | CSI_CR2_LVRM_MASK (0x70000U) |
| #define | CSI_CR2_LVRM_SHIFT (16U) |
| #define | CSI_CR2_LVRM(x) |
| #define | CSI_CR2_BTS_MASK (0x180000U) |
| #define | CSI_CR2_BTS_SHIFT (19U) |
| #define | CSI_CR2_BTS(x) |
| #define | CSI_CR2_SCE_MASK (0x800000U) |
| #define | CSI_CR2_SCE_SHIFT (23U) |
| #define | CSI_CR2_SCE(x) |
| #define | CSI_CR2_AFS_MASK (0x3000000U) |
| #define | CSI_CR2_AFS_SHIFT (24U) |
| #define | CSI_CR2_AFS(x) |
| #define | CSI_CR2_DRM_MASK (0x4000000U) |
| #define | CSI_CR2_DRM_SHIFT (26U) |
| #define | CSI_CR2_DRM(x) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT (28U) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF(x) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT (30U) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF(x) |
| #define | CSI_CR2_HSC_MASK (0xFFU) |
| #define | CSI_CR2_HSC_SHIFT (0U) |
| #define | CSI_CR2_HSC(x) |
| #define | CSI_CR2_VSC_MASK (0xFF00U) |
| #define | CSI_CR2_VSC_SHIFT (8U) |
| #define | CSI_CR2_VSC(x) |
| #define | CSI_CR2_LVRM_MASK (0x70000U) |
| #define | CSI_CR2_LVRM_SHIFT (16U) |
| #define | CSI_CR2_LVRM(x) |
| #define | CSI_CR2_BTS_MASK (0x180000U) |
| #define | CSI_CR2_BTS_SHIFT (19U) |
| #define | CSI_CR2_BTS(x) |
| #define | CSI_CR2_SCE_MASK (0x800000U) |
| #define | CSI_CR2_SCE_SHIFT (23U) |
| #define | CSI_CR2_SCE(x) |
| #define | CSI_CR2_AFS_MASK (0x3000000U) |
| #define | CSI_CR2_AFS_SHIFT (24U) |
| #define | CSI_CR2_AFS(x) |
| #define | CSI_CR2_DRM_MASK (0x4000000U) |
| #define | CSI_CR2_DRM_SHIFT (26U) |
| #define | CSI_CR2_DRM(x) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT (28U) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF(x) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT (30U) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF(x) |
| #define | CSI_CR2_HSC_MASK (0xFFU) |
| #define | CSI_CR2_HSC_SHIFT (0U) |
| #define | CSI_CR2_HSC(x) |
| #define | CSI_CR2_VSC_MASK (0xFF00U) |
| #define | CSI_CR2_VSC_SHIFT (8U) |
| #define | CSI_CR2_VSC(x) |
| #define | CSI_CR2_LVRM_MASK (0x70000U) |
| #define | CSI_CR2_LVRM_SHIFT (16U) |
| #define | CSI_CR2_LVRM(x) |
| #define | CSI_CR2_BTS_MASK (0x180000U) |
| #define | CSI_CR2_BTS_SHIFT (19U) |
| #define | CSI_CR2_BTS(x) |
| #define | CSI_CR2_SCE_MASK (0x800000U) |
| #define | CSI_CR2_SCE_SHIFT (23U) |
| #define | CSI_CR2_SCE(x) |
| #define | CSI_CR2_AFS_MASK (0x3000000U) |
| #define | CSI_CR2_AFS_SHIFT (24U) |
| #define | CSI_CR2_AFS(x) |
| #define | CSI_CR2_DRM_MASK (0x4000000U) |
| #define | CSI_CR2_DRM_SHIFT (26U) |
| #define | CSI_CR2_DRM(x) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT (28U) |
| #define | CSI_CR2_DMA_BURST_TYPE_SFF(x) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT (30U) |
| #define | CSI_CR2_DMA_BURST_TYPE_RFF(x) |
CR3 - CSI Control Register 3 | |
| #define | CSI_CR3_ECC_AUTO_EN_MASK (0x1U) |
| #define | CSI_CR3_ECC_AUTO_EN_SHIFT (0U) |
| #define | CSI_CR3_ECC_AUTO_EN(x) |
| #define | CSI_CR3_ECC_INT_EN_MASK (0x2U) |
| #define | CSI_CR3_ECC_INT_EN_SHIFT (1U) |
| #define | CSI_CR3_ECC_INT_EN(x) |
| #define | CSI_CR3_ZERO_PACK_EN_MASK (0x4U) |
| #define | CSI_CR3_ZERO_PACK_EN_SHIFT (2U) |
| #define | CSI_CR3_ZERO_PACK_EN(x) |
| #define | CSI_CR3_SENSOR_16BITS_MASK (0x8U) |
| #define | CSI_CR3_SENSOR_16BITS_SHIFT (3U) |
| #define | CSI_CR3_SENSOR_16BITS(x) |
| #define | CSI_CR3_RxFF_LEVEL_MASK (0x70U) |
| #define | CSI_CR3_RxFF_LEVEL_SHIFT (4U) |
| #define | CSI_CR3_RxFF_LEVEL(x) |
| #define | CSI_CR3_HRESP_ERR_EN_MASK (0x80U) |
| #define | CSI_CR3_HRESP_ERR_EN_SHIFT (7U) |
| #define | CSI_CR3_HRESP_ERR_EN(x) |
| #define | CSI_CR3_STATFF_LEVEL_MASK (0x700U) |
| #define | CSI_CR3_STATFF_LEVEL_SHIFT (8U) |
| #define | CSI_CR3_STATFF_LEVEL(x) |
| #define | CSI_CR3_DMA_REQ_EN_SFF_MASK (0x800U) |
| #define | CSI_CR3_DMA_REQ_EN_SFF_SHIFT (11U) |
| #define | CSI_CR3_DMA_REQ_EN_SFF(x) |
| #define | CSI_CR3_DMA_REQ_EN_RFF_MASK (0x1000U) |
| #define | CSI_CR3_DMA_REQ_EN_RFF_SHIFT (12U) |
| #define | CSI_CR3_DMA_REQ_EN_RFF(x) |
| #define | CSI_CR3_DMA_REFLASH_SFF_MASK (0x2000U) |
| #define | CSI_CR3_DMA_REFLASH_SFF_SHIFT (13U) |
| #define | CSI_CR3_DMA_REFLASH_SFF(x) |
| #define | CSI_CR3_DMA_REFLASH_RFF_MASK (0x4000U) |
| #define | CSI_CR3_DMA_REFLASH_RFF_SHIFT (14U) |
| #define | CSI_CR3_DMA_REFLASH_RFF(x) |
| #define | CSI_CR3_FRMCNT_RST_MASK (0x8000U) |
| #define | CSI_CR3_FRMCNT_RST_SHIFT (15U) |
| #define | CSI_CR3_FRMCNT_RST(x) |
| #define | CSI_CR3_FRMCNT_MASK (0xFFFF0000U) |
| #define | CSI_CR3_FRMCNT_SHIFT (16U) |
| #define | CSI_CR3_FRMCNT(x) |
| #define | CSI_CR3_ECC_AUTO_EN_MASK (0x1U) |
| #define | CSI_CR3_ECC_AUTO_EN_SHIFT (0U) |
| #define | CSI_CR3_ECC_AUTO_EN(x) |
| #define | CSI_CR3_ECC_INT_EN_MASK (0x2U) |
| #define | CSI_CR3_ECC_INT_EN_SHIFT (1U) |
| #define | CSI_CR3_ECC_INT_EN(x) |
| #define | CSI_CR3_ZERO_PACK_EN_MASK (0x4U) |
| #define | CSI_CR3_ZERO_PACK_EN_SHIFT (2U) |
| #define | CSI_CR3_ZERO_PACK_EN(x) |
| #define | CSI_CR3_SENSOR_16BITS_MASK (0x8U) |
| #define | CSI_CR3_SENSOR_16BITS_SHIFT (3U) |
| #define | CSI_CR3_SENSOR_16BITS(x) |
| #define | CSI_CR3_RxFF_LEVEL_MASK (0x70U) |
| #define | CSI_CR3_RxFF_LEVEL_SHIFT (4U) |
| #define | CSI_CR3_RxFF_LEVEL(x) |
| #define | CSI_CR3_HRESP_ERR_EN_MASK (0x80U) |
| #define | CSI_CR3_HRESP_ERR_EN_SHIFT (7U) |
| #define | CSI_CR3_HRESP_ERR_EN(x) |
| #define | CSI_CR3_STATFF_LEVEL_MASK (0x700U) |
| #define | CSI_CR3_STATFF_LEVEL_SHIFT (8U) |
| #define | CSI_CR3_STATFF_LEVEL(x) |
| #define | CSI_CR3_DMA_REQ_EN_SFF_MASK (0x800U) |
| #define | CSI_CR3_DMA_REQ_EN_SFF_SHIFT (11U) |
| #define | CSI_CR3_DMA_REQ_EN_SFF(x) |
| #define | CSI_CR3_DMA_REQ_EN_RFF_MASK (0x1000U) |
| #define | CSI_CR3_DMA_REQ_EN_RFF_SHIFT (12U) |
| #define | CSI_CR3_DMA_REQ_EN_RFF(x) |
| #define | CSI_CR3_DMA_REFLASH_SFF_MASK (0x2000U) |
| #define | CSI_CR3_DMA_REFLASH_SFF_SHIFT (13U) |
| #define | CSI_CR3_DMA_REFLASH_SFF(x) |
| #define | CSI_CR3_DMA_REFLASH_RFF_MASK (0x4000U) |
| #define | CSI_CR3_DMA_REFLASH_RFF_SHIFT (14U) |
| #define | CSI_CR3_DMA_REFLASH_RFF(x) |
| #define | CSI_CR3_FRMCNT_RST_MASK (0x8000U) |
| #define | CSI_CR3_FRMCNT_RST_SHIFT (15U) |
| #define | CSI_CR3_FRMCNT_RST(x) |
| #define | CSI_CR3_FRMCNT_MASK (0xFFFF0000U) |
| #define | CSI_CR3_FRMCNT_SHIFT (16U) |
| #define | CSI_CR3_FRMCNT(x) |
| #define | CSI_CR3_ECC_AUTO_EN_MASK (0x1U) |
| #define | CSI_CR3_ECC_AUTO_EN_SHIFT (0U) |
| #define | CSI_CR3_ECC_AUTO_EN(x) |
| #define | CSI_CR3_ECC_INT_EN_MASK (0x2U) |
| #define | CSI_CR3_ECC_INT_EN_SHIFT (1U) |
| #define | CSI_CR3_ECC_INT_EN(x) |
| #define | CSI_CR3_ZERO_PACK_EN_MASK (0x4U) |
| #define | CSI_CR3_ZERO_PACK_EN_SHIFT (2U) |
| #define | CSI_CR3_ZERO_PACK_EN(x) |
| #define | CSI_CR3_SENSOR_16BITS_MASK (0x8U) |
| #define | CSI_CR3_SENSOR_16BITS_SHIFT (3U) |
| #define | CSI_CR3_SENSOR_16BITS(x) |
| #define | CSI_CR3_RxFF_LEVEL_MASK (0x70U) |
| #define | CSI_CR3_RxFF_LEVEL_SHIFT (4U) |
| #define | CSI_CR3_RxFF_LEVEL(x) |
| #define | CSI_CR3_HRESP_ERR_EN_MASK (0x80U) |
| #define | CSI_CR3_HRESP_ERR_EN_SHIFT (7U) |
| #define | CSI_CR3_HRESP_ERR_EN(x) |
| #define | CSI_CR3_STATFF_LEVEL_MASK (0x700U) |
| #define | CSI_CR3_STATFF_LEVEL_SHIFT (8U) |
| #define | CSI_CR3_STATFF_LEVEL(x) |
| #define | CSI_CR3_DMA_REQ_EN_SFF_MASK (0x800U) |
| #define | CSI_CR3_DMA_REQ_EN_SFF_SHIFT (11U) |
| #define | CSI_CR3_DMA_REQ_EN_SFF(x) |
| #define | CSI_CR3_DMA_REQ_EN_RFF_MASK (0x1000U) |
| #define | CSI_CR3_DMA_REQ_EN_RFF_SHIFT (12U) |
| #define | CSI_CR3_DMA_REQ_EN_RFF(x) |
| #define | CSI_CR3_DMA_REFLASH_SFF_MASK (0x2000U) |
| #define | CSI_CR3_DMA_REFLASH_SFF_SHIFT (13U) |
| #define | CSI_CR3_DMA_REFLASH_SFF(x) |
| #define | CSI_CR3_DMA_REFLASH_RFF_MASK (0x4000U) |
| #define | CSI_CR3_DMA_REFLASH_RFF_SHIFT (14U) |
| #define | CSI_CR3_DMA_REFLASH_RFF(x) |
| #define | CSI_CR3_FRMCNT_RST_MASK (0x8000U) |
| #define | CSI_CR3_FRMCNT_RST_SHIFT (15U) |
| #define | CSI_CR3_FRMCNT_RST(x) |
| #define | CSI_CR3_FRMCNT_MASK (0xFFFF0000U) |
| #define | CSI_CR3_FRMCNT_SHIFT (16U) |
| #define | CSI_CR3_FRMCNT(x) |
STATFIFO - CSI Statistic FIFO Register | |
| #define | CSI_STATFIFO_STAT_MASK (0xFFFFFFFFU) |
| #define | CSI_STATFIFO_STAT_SHIFT (0U) |
| #define | CSI_STATFIFO_STAT(x) |
| #define | CSI_STATFIFO_STAT_MASK (0xFFFFFFFFU) |
| #define | CSI_STATFIFO_STAT_SHIFT (0U) |
| #define | CSI_STATFIFO_STAT(x) |
| #define | CSI_STATFIFO_STAT_MASK (0xFFFFFFFFU) |
| #define | CSI_STATFIFO_STAT_SHIFT (0U) |
| #define | CSI_STATFIFO_STAT(x) |
RFIFO - CSI RX FIFO Register | |
| #define | CSI_RFIFO_IMAGE_MASK (0xFFFFFFFFU) |
| #define | CSI_RFIFO_IMAGE_SHIFT (0U) |
| #define | CSI_RFIFO_IMAGE(x) |
| #define | CSI_RFIFO_IMAGE_MASK (0xFFFFFFFFU) |
| #define | CSI_RFIFO_IMAGE_SHIFT (0U) |
| #define | CSI_RFIFO_IMAGE(x) |
| #define | CSI_RFIFO_IMAGE_MASK (0xFFFFFFFFU) |
| #define | CSI_RFIFO_IMAGE_SHIFT (0U) |
| #define | CSI_RFIFO_IMAGE(x) |
RXCNT - CSI RX Count Register | |
| #define | CSI_RXCNT_RXCNT_MASK (0x3FFFFFU) |
| #define | CSI_RXCNT_RXCNT_SHIFT (0U) |
| #define | CSI_RXCNT_RXCNT(x) |
| #define | CSI_RXCNT_RXCNT_MASK (0x3FFFFFU) |
| #define | CSI_RXCNT_RXCNT_SHIFT (0U) |
| #define | CSI_RXCNT_RXCNT(x) |
| #define | CSI_RXCNT_RXCNT_MASK (0x3FFFFFU) |
| #define | CSI_RXCNT_RXCNT_SHIFT (0U) |
| #define | CSI_RXCNT_RXCNT(x) |
SR - CSI Status Register | |
| #define | CSI_SR_DRDY_MASK (0x1U) |
| #define | CSI_SR_DRDY_SHIFT (0U) |
| #define | CSI_SR_DRDY(x) |
| #define | CSI_SR_ECC_INT_MASK (0x2U) |
| #define | CSI_SR_ECC_INT_SHIFT (1U) |
| #define | CSI_SR_ECC_INT(x) |
| #define | CSI_SR_HRESP_ERR_INT_MASK (0x80U) |
| #define | CSI_SR_HRESP_ERR_INT_SHIFT (7U) |
| #define | CSI_SR_HRESP_ERR_INT(x) |
| #define | CSI_SR_COF_INT_MASK (0x2000U) |
| #define | CSI_SR_COF_INT_SHIFT (13U) |
| #define | CSI_SR_COF_INT(x) |
| #define | CSI_SR_F1_INT_MASK (0x4000U) |
| #define | CSI_SR_F1_INT_SHIFT (14U) |
| #define | CSI_SR_F1_INT(x) |
| #define | CSI_SR_F2_INT_MASK (0x8000U) |
| #define | CSI_SR_F2_INT_SHIFT (15U) |
| #define | CSI_SR_F2_INT(x) |
| #define | CSI_SR_SOF_INT_MASK (0x10000U) |
| #define | CSI_SR_SOF_INT_SHIFT (16U) |
| #define | CSI_SR_SOF_INT(x) |
| #define | CSI_SR_EOF_INT_MASK (0x20000U) |
| #define | CSI_SR_EOF_INT_SHIFT (17U) |
| #define | CSI_SR_EOF_INT(x) |
| #define | CSI_SR_RxFF_INT_MASK (0x40000U) |
| #define | CSI_SR_RxFF_INT_SHIFT (18U) |
| #define | CSI_SR_RxFF_INT(x) |
| #define | CSI_SR_DMA_TSF_DONE_FB1_MASK (0x80000U) |
| #define | CSI_SR_DMA_TSF_DONE_FB1_SHIFT (19U) |
| #define | CSI_SR_DMA_TSF_DONE_FB1(x) |
| #define | CSI_SR_DMA_TSF_DONE_FB2_MASK (0x100000U) |
| #define | CSI_SR_DMA_TSF_DONE_FB2_SHIFT (20U) |
| #define | CSI_SR_DMA_TSF_DONE_FB2(x) |
| #define | CSI_SR_STATFF_INT_MASK (0x200000U) |
| #define | CSI_SR_STATFF_INT_SHIFT (21U) |
| #define | CSI_SR_STATFF_INT(x) |
| #define | CSI_SR_DMA_TSF_DONE_SFF_MASK (0x400000U) |
| #define | CSI_SR_DMA_TSF_DONE_SFF_SHIFT (22U) |
| #define | CSI_SR_DMA_TSF_DONE_SFF(x) |
| #define | CSI_SR_RF_OR_INT_MASK (0x1000000U) |
| #define | CSI_SR_RF_OR_INT_SHIFT (24U) |
| #define | CSI_SR_RF_OR_INT(x) |
| #define | CSI_SR_SF_OR_INT_MASK (0x2000000U) |
| #define | CSI_SR_SF_OR_INT_SHIFT (25U) |
| #define | CSI_SR_SF_OR_INT(x) |
| #define | CSI_SR_DMA_FIELD1_DONE_MASK (0x4000000U) |
| #define | CSI_SR_DMA_FIELD1_DONE_SHIFT (26U) |
| #define | CSI_SR_DMA_FIELD1_DONE(x) |
| #define | CSI_SR_DMA_FIELD0_DONE_MASK (0x8000000U) |
| #define | CSI_SR_DMA_FIELD0_DONE_SHIFT (27U) |
| #define | CSI_SR_DMA_FIELD0_DONE(x) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR(x) |
| #define | CSI_SR_DRDY_MASK (0x1U) |
| #define | CSI_SR_DRDY_SHIFT (0U) |
| #define | CSI_SR_DRDY(x) |
| #define | CSI_SR_ECC_INT_MASK (0x2U) |
| #define | CSI_SR_ECC_INT_SHIFT (1U) |
| #define | CSI_SR_ECC_INT(x) |
| #define | CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK (0x4U) |
| #define | CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT (2U) |
| #define | CSI_SR_HISTOGRAM_CALC_DONE_INT(x) |
| #define | CSI_SR_HRESP_ERR_INT_MASK (0x80U) |
| #define | CSI_SR_HRESP_ERR_INT_SHIFT (7U) |
| #define | CSI_SR_HRESP_ERR_INT(x) |
| #define | CSI_SR_COF_INT_MASK (0x2000U) |
| #define | CSI_SR_COF_INT_SHIFT (13U) |
| #define | CSI_SR_COF_INT(x) |
| #define | CSI_SR_F1_INT_MASK (0x4000U) |
| #define | CSI_SR_F1_INT_SHIFT (14U) |
| #define | CSI_SR_F1_INT(x) |
| #define | CSI_SR_F2_INT_MASK (0x8000U) |
| #define | CSI_SR_F2_INT_SHIFT (15U) |
| #define | CSI_SR_F2_INT(x) |
| #define | CSI_SR_SOF_INT_MASK (0x10000U) |
| #define | CSI_SR_SOF_INT_SHIFT (16U) |
| #define | CSI_SR_SOF_INT(x) |
| #define | CSI_SR_EOF_INT_MASK (0x20000U) |
| #define | CSI_SR_EOF_INT_SHIFT (17U) |
| #define | CSI_SR_EOF_INT(x) |
| #define | CSI_SR_RxFF_INT_MASK (0x40000U) |
| #define | CSI_SR_RxFF_INT_SHIFT (18U) |
| #define | CSI_SR_RxFF_INT(x) |
| #define | CSI_SR_DMA_TSF_DONE_FB1_MASK (0x80000U) |
| #define | CSI_SR_DMA_TSF_DONE_FB1_SHIFT (19U) |
| #define | CSI_SR_DMA_TSF_DONE_FB1(x) |
| #define | CSI_SR_DMA_TSF_DONE_FB2_MASK (0x100000U) |
| #define | CSI_SR_DMA_TSF_DONE_FB2_SHIFT (20U) |
| #define | CSI_SR_DMA_TSF_DONE_FB2(x) |
| #define | CSI_SR_STATFF_INT_MASK (0x200000U) |
| #define | CSI_SR_STATFF_INT_SHIFT (21U) |
| #define | CSI_SR_STATFF_INT(x) |
| #define | CSI_SR_DMA_TSF_DONE_SFF_MASK (0x400000U) |
| #define | CSI_SR_DMA_TSF_DONE_SFF_SHIFT (22U) |
| #define | CSI_SR_DMA_TSF_DONE_SFF(x) |
| #define | CSI_SR_RF_OR_INT_MASK (0x1000000U) |
| #define | CSI_SR_RF_OR_INT_SHIFT (24U) |
| #define | CSI_SR_RF_OR_INT(x) |
| #define | CSI_SR_SF_OR_INT_MASK (0x2000000U) |
| #define | CSI_SR_SF_OR_INT_SHIFT (25U) |
| #define | CSI_SR_SF_OR_INT(x) |
| #define | CSI_SR_DMA_FIELD1_DONE_MASK (0x4000000U) |
| #define | CSI_SR_DMA_FIELD1_DONE_SHIFT (26U) |
| #define | CSI_SR_DMA_FIELD1_DONE(x) |
| #define | CSI_SR_DMA_FIELD0_DONE_MASK (0x8000000U) |
| #define | CSI_SR_DMA_FIELD0_DONE_SHIFT (27U) |
| #define | CSI_SR_DMA_FIELD0_DONE(x) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR(x) |
| #define | CSI_SR_DRDY_MASK (0x1U) |
| #define | CSI_SR_DRDY_SHIFT (0U) |
| #define | CSI_SR_DRDY(x) |
| #define | CSI_SR_ECC_INT_MASK (0x2U) |
| #define | CSI_SR_ECC_INT_SHIFT (1U) |
| #define | CSI_SR_ECC_INT(x) |
| #define | CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK (0x4U) |
| #define | CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT (2U) |
| #define | CSI_SR_HISTOGRAM_CALC_DONE_INT(x) |
| #define | CSI_SR_HRESP_ERR_INT_MASK (0x80U) |
| #define | CSI_SR_HRESP_ERR_INT_SHIFT (7U) |
| #define | CSI_SR_HRESP_ERR_INT(x) |
| #define | CSI_SR_COF_INT_MASK (0x2000U) |
| #define | CSI_SR_COF_INT_SHIFT (13U) |
| #define | CSI_SR_COF_INT(x) |
| #define | CSI_SR_F1_INT_MASK (0x4000U) |
| #define | CSI_SR_F1_INT_SHIFT (14U) |
| #define | CSI_SR_F1_INT(x) |
| #define | CSI_SR_F2_INT_MASK (0x8000U) |
| #define | CSI_SR_F2_INT_SHIFT (15U) |
| #define | CSI_SR_F2_INT(x) |
| #define | CSI_SR_SOF_INT_MASK (0x10000U) |
| #define | CSI_SR_SOF_INT_SHIFT (16U) |
| #define | CSI_SR_SOF_INT(x) |
| #define | CSI_SR_EOF_INT_MASK (0x20000U) |
| #define | CSI_SR_EOF_INT_SHIFT (17U) |
| #define | CSI_SR_EOF_INT(x) |
| #define | CSI_SR_RxFF_INT_MASK (0x40000U) |
| #define | CSI_SR_RxFF_INT_SHIFT (18U) |
| #define | CSI_SR_RxFF_INT(x) |
| #define | CSI_SR_DMA_TSF_DONE_FB1_MASK (0x80000U) |
| #define | CSI_SR_DMA_TSF_DONE_FB1_SHIFT (19U) |
| #define | CSI_SR_DMA_TSF_DONE_FB1(x) |
| #define | CSI_SR_DMA_TSF_DONE_FB2_MASK (0x100000U) |
| #define | CSI_SR_DMA_TSF_DONE_FB2_SHIFT (20U) |
| #define | CSI_SR_DMA_TSF_DONE_FB2(x) |
| #define | CSI_SR_STATFF_INT_MASK (0x200000U) |
| #define | CSI_SR_STATFF_INT_SHIFT (21U) |
| #define | CSI_SR_STATFF_INT(x) |
| #define | CSI_SR_DMA_TSF_DONE_SFF_MASK (0x400000U) |
| #define | CSI_SR_DMA_TSF_DONE_SFF_SHIFT (22U) |
| #define | CSI_SR_DMA_TSF_DONE_SFF(x) |
| #define | CSI_SR_RF_OR_INT_MASK (0x1000000U) |
| #define | CSI_SR_RF_OR_INT_SHIFT (24U) |
| #define | CSI_SR_RF_OR_INT(x) |
| #define | CSI_SR_SF_OR_INT_MASK (0x2000000U) |
| #define | CSI_SR_SF_OR_INT_SHIFT (25U) |
| #define | CSI_SR_SF_OR_INT(x) |
| #define | CSI_SR_DMA_FIELD1_DONE_MASK (0x4000000U) |
| #define | CSI_SR_DMA_FIELD1_DONE_SHIFT (26U) |
| #define | CSI_SR_DMA_FIELD1_DONE(x) |
| #define | CSI_SR_DMA_FIELD0_DONE_MASK (0x8000000U) |
| #define | CSI_SR_DMA_FIELD0_DONE_SHIFT (27U) |
| #define | CSI_SR_DMA_FIELD0_DONE(x) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) |
| #define | CSI_SR_BASEADDR_CHHANGE_ERROR(x) |
DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO | |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) |
| #define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) |
DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO | |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) |
| #define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) |
DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 | |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) |
| #define | CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) |
DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 | |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) |
| #define | CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) |
FBUF_PARA - CSI Frame Buffer Parameter Register | |
| #define | CSI_FBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) |
| #define | CSI_FBUF_PARA_FBUF_STRIDE_SHIFT (0U) |
| #define | CSI_FBUF_PARA_FBUF_STRIDE(x) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) |
| #define | CSI_FBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) |
| #define | CSI_FBUF_PARA_FBUF_STRIDE_SHIFT (0U) |
| #define | CSI_FBUF_PARA_FBUF_STRIDE(x) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) |
| #define | CSI_FBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) |
| #define | CSI_FBUF_PARA_FBUF_STRIDE_SHIFT (0U) |
| #define | CSI_FBUF_PARA_FBUF_STRIDE(x) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) |
| #define | CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) |
IMAG_PARA - CSI Image Parameter Register | |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT(x) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT (16U) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH(x) |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT(x) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT (16U) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH(x) |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) |
| #define | CSI_IMAG_PARA_IMAGE_HEIGHT(x) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT (16U) |
| #define | CSI_IMAG_PARA_IMAGE_WIDTH(x) |
CR18 - CSI Control Register 18 | |
| #define | CSI_CR18_DEINTERLACE_EN_MASK (0x4U) |
| #define | CSI_CR18_DEINTERLACE_EN_SHIFT (2U) |
| #define | CSI_CR18_DEINTERLACE_EN(x) |
| #define | CSI_CR18_PARALLEL24_EN_MASK (0x8U) |
| #define | CSI_CR18_PARALLEL24_EN_SHIFT (3U) |
| #define | CSI_CR18_PARALLEL24_EN(x) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN_MASK (0x10U) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN_SHIFT (4U) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN(x) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL_MASK (0x20U) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT (5U) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL(x) |
| #define | CSI_CR18_FIELD0_DONE_IE_MASK (0x40U) |
| #define | CSI_CR18_FIELD0_DONE_IE_SHIFT (6U) |
| #define | CSI_CR18_FIELD0_DONE_IE(x) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE_MASK (0x80U) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT (7U) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE(x) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL_MASK (0x100U) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL_SHIFT (8U) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL(x) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL_MASK (0x400U) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL_SHIFT (10U) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL(x) |
| #define | CSI_CR18_AHB_HPROT_MASK (0xF000U) |
| #define | CSI_CR18_AHB_HPROT_SHIFT (12U) |
| #define | CSI_CR18_AHB_HPROT(x) |
| #define | CSI_CR18_MASK_OPTION_MASK (0xC0000U) |
| #define | CSI_CR18_MASK_OPTION_SHIFT (18U) |
| #define | CSI_CR18_MASK_OPTION(x) |
| #define | CSI_CR18_CSI_ENABLE_MASK (0x80000000U) |
| #define | CSI_CR18_CSI_ENABLE_SHIFT (31U) |
| #define | CSI_CR18_CSI_ENABLE(x) |
| #define | CSI_CR18_NTSC_EN_MASK (0x1U) |
| #define | CSI_CR18_NTSC_EN_SHIFT (0U) |
| #define | CSI_CR18_NTSC_EN(x) |
| #define | CSI_CR18_TVDECODER_IN_EN_MASK (0x2U) |
| #define | CSI_CR18_TVDECODER_IN_EN_SHIFT (1U) |
| #define | CSI_CR18_TVDECODER_IN_EN(x) |
| #define | CSI_CR18_DEINTERLACE_EN_MASK (0x4U) |
| #define | CSI_CR18_DEINTERLACE_EN_SHIFT (2U) |
| #define | CSI_CR18_DEINTERLACE_EN(x) |
| #define | CSI_CR18_PARALLEL24_EN_MASK (0x8U) |
| #define | CSI_CR18_PARALLEL24_EN_SHIFT (3U) |
| #define | CSI_CR18_PARALLEL24_EN(x) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN_MASK (0x10U) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN_SHIFT (4U) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN(x) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL_MASK (0x20U) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT (5U) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL(x) |
| #define | CSI_CR18_FIELD0_DONE_IE_MASK (0x40U) |
| #define | CSI_CR18_FIELD0_DONE_IE_SHIFT (6U) |
| #define | CSI_CR18_FIELD0_DONE_IE(x) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE_MASK (0x80U) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT (7U) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE(x) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL_MASK (0x100U) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL_SHIFT (8U) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL(x) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL_MASK (0x400U) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL_SHIFT (10U) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL(x) |
| #define | CSI_CR18_AHB_HPROT_MASK (0xF000U) |
| #define | CSI_CR18_AHB_HPROT_SHIFT (12U) |
| #define | CSI_CR18_AHB_HPROT(x) |
| #define | CSI_CR18_MASK_OPTION_MASK (0xC0000U) |
| #define | CSI_CR18_MASK_OPTION_SHIFT (18U) |
| #define | CSI_CR18_MASK_OPTION(x) |
| #define | CSI_CR18_MIPI_DOUBLE_CMPNT_MASK (0x100000U) |
| #define | CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT (20U) |
| #define | CSI_CR18_MIPI_DOUBLE_CMPNT(x) |
| #define | CSI_CR18_MIPI_YU_SWAP_MASK (0x200000U) |
| #define | CSI_CR18_MIPI_YU_SWAP_SHIFT (21U) |
| #define | CSI_CR18_MIPI_YU_SWAP(x) |
| #define | CSI_CR18_DATA_FROM_MIPI_MASK (0x400000U) |
| #define | CSI_CR18_DATA_FROM_MIPI_SHIFT (22U) |
| #define | CSI_CR18_DATA_FROM_MIPI(x) |
| #define | CSI_CR18_LINE_STRIDE_EN_MASK (0x1000000U) |
| #define | CSI_CR18_LINE_STRIDE_EN_SHIFT (24U) |
| #define | CSI_CR18_LINE_STRIDE_EN(x) |
| #define | CSI_CR18_MIPI_DATA_FORMAT_MASK (0x7E000000U) |
| #define | CSI_CR18_MIPI_DATA_FORMAT_SHIFT (25U) |
| #define | CSI_CR18_MIPI_DATA_FORMAT(x) |
| #define | CSI_CR18_CSI_ENABLE_MASK (0x80000000U) |
| #define | CSI_CR18_CSI_ENABLE_SHIFT (31U) |
| #define | CSI_CR18_CSI_ENABLE(x) |
| #define | CSI_CR18_NTSC_EN_MASK (0x1U) |
| #define | CSI_CR18_NTSC_EN_SHIFT (0U) |
| #define | CSI_CR18_NTSC_EN(x) |
| #define | CSI_CR18_TVDECODER_IN_EN_MASK (0x2U) |
| #define | CSI_CR18_TVDECODER_IN_EN_SHIFT (1U) |
| #define | CSI_CR18_TVDECODER_IN_EN(x) |
| #define | CSI_CR18_DEINTERLACE_EN_MASK (0x4U) |
| #define | CSI_CR18_DEINTERLACE_EN_SHIFT (2U) |
| #define | CSI_CR18_DEINTERLACE_EN(x) |
| #define | CSI_CR18_PARALLEL24_EN_MASK (0x8U) |
| #define | CSI_CR18_PARALLEL24_EN_SHIFT (3U) |
| #define | CSI_CR18_PARALLEL24_EN(x) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN_MASK (0x10U) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN_SHIFT (4U) |
| #define | CSI_CR18_BASEADDR_SWITCH_EN(x) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL_MASK (0x20U) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT (5U) |
| #define | CSI_CR18_BASEADDR_SWITCH_SEL(x) |
| #define | CSI_CR18_FIELD0_DONE_IE_MASK (0x40U) |
| #define | CSI_CR18_FIELD0_DONE_IE_SHIFT (6U) |
| #define | CSI_CR18_FIELD0_DONE_IE(x) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE_MASK (0x80U) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT (7U) |
| #define | CSI_CR18_DMA_FIELD1_DONE_IE(x) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL_MASK (0x100U) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL_SHIFT (8U) |
| #define | CSI_CR18_LAST_DMA_REQ_SEL(x) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) |
| #define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL_MASK (0x400U) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL_SHIFT (10U) |
| #define | CSI_CR18_RGB888A_FORMAT_SEL(x) |
| #define | CSI_CR18_AHB_HPROT_MASK (0xF000U) |
| #define | CSI_CR18_AHB_HPROT_SHIFT (12U) |
| #define | CSI_CR18_AHB_HPROT(x) |
| #define | CSI_CR18_MASK_OPTION_MASK (0xC0000U) |
| #define | CSI_CR18_MASK_OPTION_SHIFT (18U) |
| #define | CSI_CR18_MASK_OPTION(x) |
| #define | CSI_CR18_MIPI_DOUBLE_CMPNT_MASK (0x100000U) |
| #define | CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT (20U) |
| #define | CSI_CR18_MIPI_DOUBLE_CMPNT(x) |
| #define | CSI_CR18_MIPI_YU_SWAP_MASK (0x200000U) |
| #define | CSI_CR18_MIPI_YU_SWAP_SHIFT (21U) |
| #define | CSI_CR18_MIPI_YU_SWAP(x) |
| #define | CSI_CR18_DATA_FROM_MIPI_MASK (0x400000U) |
| #define | CSI_CR18_DATA_FROM_MIPI_SHIFT (22U) |
| #define | CSI_CR18_DATA_FROM_MIPI(x) |
| #define | CSI_CR18_LINE_STRIDE_EN_MASK (0x1000000U) |
| #define | CSI_CR18_LINE_STRIDE_EN_SHIFT (24U) |
| #define | CSI_CR18_LINE_STRIDE_EN(x) |
| #define | CSI_CR18_MIPI_DATA_FORMAT_MASK (0x7E000000U) |
| #define | CSI_CR18_MIPI_DATA_FORMAT_SHIFT (25U) |
| #define | CSI_CR18_MIPI_DATA_FORMAT(x) |
| #define | CSI_CR18_CSI_ENABLE_MASK (0x80000000U) |
| #define | CSI_CR18_CSI_ENABLE_SHIFT (31U) |
| #define | CSI_CR18_CSI_ENABLE(x) |
CR19 - CSI Control Register 19 | |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) |
| #define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) |
CR20 - CSI Control Register 20 | |
| #define | CSI_CR20_THRESHOLD_MASK (0xFFU) |
| #define | CSI_CR20_THRESHOLD_SHIFT (0U) |
| #define | CSI_CR20_THRESHOLD(x) |
| #define | CSI_CR20_BINARY_EN_MASK (0x100U) |
| #define | CSI_CR20_BINARY_EN_SHIFT (8U) |
| #define | CSI_CR20_BINARY_EN(x) |
| #define | CSI_CR20_QR_DATA_FORMAT_MASK (0xE00U) |
| #define | CSI_CR20_QR_DATA_FORMAT_SHIFT (9U) |
| #define | CSI_CR20_QR_DATA_FORMAT(x) |
| #define | CSI_CR20_BIG_END_MASK (0x1000U) |
| #define | CSI_CR20_BIG_END_SHIFT (12U) |
| #define | CSI_CR20_BIG_END(x) |
| #define | CSI_CR20_10BIT_NEW_EN_MASK (0x20000000U) |
| #define | CSI_CR20_10BIT_NEW_EN_SHIFT (29U) |
| #define | CSI_CR20_10BIT_NEW_EN(x) |
| #define | CSI_CR20_HISTOGRAM_EN_MASK (0x40000000U) |
| #define | CSI_CR20_HISTOGRAM_EN_SHIFT (30U) |
| #define | CSI_CR20_HISTOGRAM_EN(x) |
| #define | CSI_CR20_QRCODE_EN_MASK (0x80000000U) |
| #define | CSI_CR20_QRCODE_EN_SHIFT (31U) |
| #define | CSI_CR20_QRCODE_EN(x) |
| #define | CSI_CR20_THRESHOLD_MASK (0xFFU) |
| #define | CSI_CR20_THRESHOLD_SHIFT (0U) |
| #define | CSI_CR20_THRESHOLD(x) |
| #define | CSI_CR20_BINARY_EN_MASK (0x100U) |
| #define | CSI_CR20_BINARY_EN_SHIFT (8U) |
| #define | CSI_CR20_BINARY_EN(x) |
| #define | CSI_CR20_QR_DATA_FORMAT_MASK (0xE00U) |
| #define | CSI_CR20_QR_DATA_FORMAT_SHIFT (9U) |
| #define | CSI_CR20_QR_DATA_FORMAT(x) |
| #define | CSI_CR20_BIG_END_MASK (0x1000U) |
| #define | CSI_CR20_BIG_END_SHIFT (12U) |
| #define | CSI_CR20_BIG_END(x) |
| #define | CSI_CR20_10BIT_NEW_EN_MASK (0x20000000U) |
| #define | CSI_CR20_10BIT_NEW_EN_SHIFT (29U) |
| #define | CSI_CR20_10BIT_NEW_EN(x) |
| #define | CSI_CR20_HISTOGRAM_EN_MASK (0x40000000U) |
| #define | CSI_CR20_HISTOGRAM_EN_SHIFT (30U) |
| #define | CSI_CR20_HISTOGRAM_EN(x) |
| #define | CSI_CR20_QRCODE_EN_MASK (0x80000000U) |
| #define | CSI_CR20_QRCODE_EN_SHIFT (31U) |
| #define | CSI_CR20_QRCODE_EN(x) |
CR - CSI Control Register | |
| #define | CSI_CR_PIXEL_COUNTERS_MASK (0xFFFFFFU) |
| #define | CSI_CR_PIXEL_COUNTERS_SHIFT (0U) |
| #define | CSI_CR_PIXEL_COUNTERS(x) |
| #define | CSI_CR_PIXEL_COUNTERS_MASK (0xFFFFFFU) |
| #define | CSI_CR_PIXEL_COUNTERS_SHIFT (0U) |
| #define | CSI_CR_PIXEL_COUNTERS(x) |
| #define CSI_CR18_AHB_HPROT | ( | x | ) |
| #define CSI_CR18_AHB_HPROT | ( | x | ) |
| #define CSI_CR18_AHB_HPROT | ( | x | ) |
| #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE | ( | x | ) |
BASEADDR_CHANGE_ERROR_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE | ( | x | ) |
BASEADDR_CHANGE_ERROR_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE | ( | x | ) |
BASEADDR_CHANGE_ERROR_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_BASEADDR_SWITCH_EN | ( | x | ) |
| #define CSI_CR18_BASEADDR_SWITCH_EN | ( | x | ) |
| #define CSI_CR18_BASEADDR_SWITCH_EN | ( | x | ) |
| #define CSI_CR18_BASEADDR_SWITCH_SEL | ( | x | ) |
BASEADDR_SWITCH_SEL 0b0..Switching base address at the edge of the vsync 0b1..Switching base address at the edge of the first data of each frame
| #define CSI_CR18_BASEADDR_SWITCH_SEL | ( | x | ) |
BASEADDR_SWITCH_SEL 0b0..Switching base address at the edge of the vsync 0b1..Switching base address at the edge of the first data of each frame
| #define CSI_CR18_BASEADDR_SWITCH_SEL | ( | x | ) |
BASEADDR_SWITCH_SEL 0b0..Switching base address at the edge of the vsync 0b1..Switching base address at the edge of the first data of each frame
| #define CSI_CR18_CSI_ENABLE | ( | x | ) |
| #define CSI_CR18_CSI_ENABLE | ( | x | ) |
| #define CSI_CR18_CSI_ENABLE | ( | x | ) |
| #define CSI_CR18_DATA_FROM_MIPI | ( | x | ) |
DATA_FROM_MIPI 0b0..Data from parallel sensor 0b1..Data from MIPI
| #define CSI_CR18_DATA_FROM_MIPI | ( | x | ) |
DATA_FROM_MIPI 0b0..Data from parallel sensor 0b1..Data from MIPI
| #define CSI_CR18_DEINTERLACE_EN | ( | x | ) |
DEINTERLACE_EN 0b0..Deinterlace disabled 0b1..Deinterlace enabled
| #define CSI_CR18_DEINTERLACE_EN | ( | x | ) |
DEINTERLACE_EN 0b0..Deinterlace disabled 0b1..Deinterlace enabled
| #define CSI_CR18_DEINTERLACE_EN | ( | x | ) |
DEINTERLACE_EN 0b0..Deinterlace disabled 0b1..Deinterlace enabled
| #define CSI_CR18_DMA_FIELD1_DONE_IE | ( | x | ) |
DMA_FIELD1_DONE_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_DMA_FIELD1_DONE_IE | ( | x | ) |
DMA_FIELD1_DONE_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_DMA_FIELD1_DONE_IE | ( | x | ) |
DMA_FIELD1_DONE_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_FIELD0_DONE_IE | ( | x | ) |
FIELD0_DONE_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_FIELD0_DONE_IE | ( | x | ) |
FIELD0_DONE_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_FIELD0_DONE_IE | ( | x | ) |
FIELD0_DONE_IE 0b0..Interrupt disabled 0b1..Interrupt enabled
| #define CSI_CR18_LAST_DMA_REQ_SEL | ( | x | ) |
LAST_DMA_REQ_SEL 0b0..fifo_full_level 0b1..hburst_length
| #define CSI_CR18_LAST_DMA_REQ_SEL | ( | x | ) |
LAST_DMA_REQ_SEL 0b0..fifo_full_level 0b1..hburst_length
| #define CSI_CR18_LAST_DMA_REQ_SEL | ( | x | ) |
LAST_DMA_REQ_SEL 0b0..fifo_full_level 0b1..hburst_length
| #define CSI_CR18_LINE_STRIDE_EN | ( | x | ) |
| #define CSI_CR18_LINE_STRIDE_EN | ( | x | ) |
| #define CSI_CR18_MASK_OPTION | ( | x | ) |
MASK_OPTION 0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1. 0b01..Writing to memory when CSI_ENABLE is 1. 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
| #define CSI_CR18_MASK_OPTION | ( | x | ) |
MASK_OPTION 0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1. 0b01..Writing to memory when CSI_ENABLE is 1. 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
| #define CSI_CR18_MASK_OPTION | ( | x | ) |
MASK_OPTION 0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1. 0b01..Writing to memory when CSI_ENABLE is 1. 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
| #define CSI_CR18_MIPI_DATA_FORMAT | ( | x | ) |
MIPI_DATA_FORMAT - Image Data Format
| #define CSI_CR18_MIPI_DATA_FORMAT | ( | x | ) |
MIPI_DATA_FORMAT - Image Data Format
| #define CSI_CR18_MIPI_DOUBLE_CMPNT | ( | x | ) |
MIPI_DOUBLE_CMPNT 0b0..Single component per clock cycle (half pixel per clock cycle) 0b1..Double component per clock cycle (a pixel per clock cycle)
| #define CSI_CR18_MIPI_DOUBLE_CMPNT | ( | x | ) |
MIPI_DOUBLE_CMPNT 0b0..Single component per clock cycle (half pixel per clock cycle) 0b1..Double component per clock cycle (a pixel per clock cycle)
| #define CSI_CR18_MIPI_YU_SWAP | ( | x | ) |
MIPI_YU_SWAP - It only works in MIPI CSI YUV422 double component mode.
| #define CSI_CR18_MIPI_YU_SWAP | ( | x | ) |
MIPI_YU_SWAP - It only works in MIPI CSI YUV422 double component mode.
| #define CSI_CR18_NTSC_EN | ( | x | ) |
NTSC_EN 0b0..PAL 0b1..NTSC
| #define CSI_CR18_NTSC_EN | ( | x | ) |
NTSC_EN 0b0..PAL 0b1..NTSC
| #define CSI_CR18_PARALLEL24_EN | ( | x | ) |
PARALLEL24_EN 0b0..Input is disabled 0b1..Input is enabled
| #define CSI_CR18_PARALLEL24_EN | ( | x | ) |
PARALLEL24_EN 0b0..Input is disabled 0b1..Input is enabled
| #define CSI_CR18_PARALLEL24_EN | ( | x | ) |
PARALLEL24_EN 0b0..Input is disabled 0b1..Input is enabled
| #define CSI_CR18_RGB888A_FORMAT_SEL | ( | x | ) |
RGB888A_FORMAT_SEL 0b0..{8'h0, data[23:0]} 0b1..{data[23:0], 8'h0}
| #define CSI_CR18_RGB888A_FORMAT_SEL | ( | x | ) |
RGB888A_FORMAT_SEL 0b0..{8'h0, data[23:0]} 0b1..{data[23:0], 8'h0}
| #define CSI_CR18_RGB888A_FORMAT_SEL | ( | x | ) |
RGB888A_FORMAT_SEL 0b0..{8'h0, data[23:0]} 0b1..{data[23:0], 8'h0}
| #define CSI_CR18_TVDECODER_IN_EN | ( | x | ) |
| #define CSI_CR18_TVDECODER_IN_EN | ( | x | ) |
| #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL | ( | x | ) |
| #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL | ( | x | ) |
| #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL | ( | x | ) |
| #define CSI_CR1_CCIR_EN | ( | x | ) |
CCIR_EN 0b0..Traditional interface is selected. 0b1..BT.656 interface is selected.
| #define CSI_CR1_CCIR_EN | ( | x | ) |
CCIR_EN 0b0..Traditional interface is selected. 0b1..BT.656 interface is selected.
| #define CSI_CR1_CCIR_EN | ( | x | ) |
CCIR_EN 0b0..Traditional interface is selected. 0b1..BT.656 interface is selected.
| #define CSI_CR1_CCIR_MODE | ( | x | ) |
CCIR_MODE 0b0..Progressive mode is selected 0b1..Interlace mode is selected
| #define CSI_CR1_CLR_RXFIFO | ( | x | ) |
| #define CSI_CR1_CLR_RXFIFO | ( | x | ) |
| #define CSI_CR1_CLR_RXFIFO | ( | x | ) |
| #define CSI_CR1_CLR_STATFIFO | ( | x | ) |
| #define CSI_CR1_CLR_STATFIFO | ( | x | ) |
| #define CSI_CR1_CLR_STATFIFO | ( | x | ) |
| #define CSI_CR1_COF_INT_EN | ( | x | ) |
COF_INT_EN 0b0..COF interrupt is disabled 0b1..COF interrupt is enabled
| #define CSI_CR1_COF_INT_EN | ( | x | ) |
COF_INT_EN 0b0..COF interrupt is disabled 0b1..COF interrupt is enabled
| #define CSI_CR1_COF_INT_EN | ( | x | ) |
COF_INT_EN 0b0..COF interrupt is disabled 0b1..COF interrupt is enabled
| #define CSI_CR1_EOF_INT_EN | ( | x | ) |
EOF_INT_EN 0b0..EOF interrupt is disabled. 0b1..EOF interrupt is generated when RX count value is reached.
| #define CSI_CR1_EOF_INT_EN | ( | x | ) |
EOF_INT_EN 0b0..EOF interrupt is disabled. 0b1..EOF interrupt is generated when RX count value is reached.
| #define CSI_CR1_EOF_INT_EN | ( | x | ) |
EOF_INT_EN 0b0..EOF interrupt is disabled. 0b1..EOF interrupt is generated when RX count value is reached.
| #define CSI_CR1_EXT_VSYNC | ( | x | ) |
EXT_VSYNC 0b0..Internal VSYNC mode 0b1..External VSYNC mode
| #define CSI_CR1_EXT_VSYNC | ( | x | ) |
EXT_VSYNC 0b0..Internal VSYNC mode 0b1..External VSYNC mode
| #define CSI_CR1_EXT_VSYNC | ( | x | ) |
EXT_VSYNC 0b0..Internal VSYNC mode 0b1..External VSYNC mode
| #define CSI_CR1_FB1_DMA_DONE_INTEN | ( | x | ) |
FB1_DMA_DONE_INTEN 0b0..Frame Buffer1 DMA Transfer Done interrupt disable 0b1..Frame Buffer1 DMA Transfer Done interrupt enable
| #define CSI_CR1_FB1_DMA_DONE_INTEN | ( | x | ) |
FB1_DMA_DONE_INTEN 0b0..Frame Buffer1 DMA Transfer Done interrupt disable 0b1..Frame Buffer1 DMA Transfer Done interrupt enable
| #define CSI_CR1_FB1_DMA_DONE_INTEN | ( | x | ) |
FB1_DMA_DONE_INTEN 0b0..Frame Buffer1 DMA Transfer Done interrupt disable 0b1..Frame Buffer1 DMA Transfer Done interrupt enable
| #define CSI_CR1_FB2_DMA_DONE_INTEN | ( | x | ) |
FB2_DMA_DONE_INTEN 0b0..Frame Buffer2 DMA Transfer Done interrupt disable 0b1..Frame Buffer2 DMA Transfer Done interrupt enable
| #define CSI_CR1_FB2_DMA_DONE_INTEN | ( | x | ) |
FB2_DMA_DONE_INTEN 0b0..Frame Buffer2 DMA Transfer Done interrupt disable 0b1..Frame Buffer2 DMA Transfer Done interrupt enable
| #define CSI_CR1_FB2_DMA_DONE_INTEN | ( | x | ) |
FB2_DMA_DONE_INTEN 0b0..Frame Buffer2 DMA Transfer Done interrupt disable 0b1..Frame Buffer2 DMA Transfer Done interrupt enable
| #define CSI_CR1_FCC | ( | x | ) |
FCC 0b0..Asynchronous FIFO clear is selected. 0b1..Synchronous FIFO clear is selected.
| #define CSI_CR1_FCC | ( | x | ) |
FCC 0b0..Asynchronous FIFO clear is selected. 0b1..Synchronous FIFO clear is selected.
| #define CSI_CR1_FCC | ( | x | ) |
FCC 0b0..Asynchronous FIFO clear is selected. 0b1..Synchronous FIFO clear is selected.
| #define CSI_CR1_GCLK_MODE | ( | x | ) |
GCLK_MODE 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
| #define CSI_CR1_GCLK_MODE | ( | x | ) |
GCLK_MODE 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
| #define CSI_CR1_GCLK_MODE | ( | x | ) |
GCLK_MODE 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
| #define CSI_CR1_HISTOGRAM_CALC_DONE_IE | ( | x | ) |
HISTOGRAM_CALC_DONE_IE 0b0..Histogram done interrupt disable 0b1..Histogram done interrupt enable
| #define CSI_CR1_HISTOGRAM_CALC_DONE_IE | ( | x | ) |
HISTOGRAM_CALC_DONE_IE 0b0..Histogram done interrupt disable 0b1..Histogram done interrupt enable
| #define CSI_CR1_HSYNC_POL | ( | x | ) |
HSYNC_POL 0b0..HSYNC is active low 0b1..HSYNC is active high
| #define CSI_CR1_HSYNC_POL | ( | x | ) |
HSYNC_POL 0b0..HSYNC is active low 0b1..HSYNC is active high
| #define CSI_CR1_HSYNC_POL | ( | x | ) |
HSYNC_POL 0b0..HSYNC is active low 0b1..HSYNC is active high
| #define CSI_CR1_INV_DATA | ( | x | ) |
INV_DATA 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
| #define CSI_CR1_INV_DATA | ( | x | ) |
INV_DATA 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
| #define CSI_CR1_INV_DATA | ( | x | ) |
INV_DATA 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
| #define CSI_CR1_INV_PCLK | ( | x | ) |
INV_PCLK 0b0..CSI_PIXCLK is directly applied to internal circuitry 0b1..CSI_PIXCLK is inverted before applied to internal circuitry
| #define CSI_CR1_INV_PCLK | ( | x | ) |
INV_PCLK 0b0..CSI_PIXCLK is directly applied to internal circuitry 0b1..CSI_PIXCLK is inverted before applied to internal circuitry
| #define CSI_CR1_INV_PCLK | ( | x | ) |
INV_PCLK 0b0..CSI_PIXCLK is directly applied to internal circuitry 0b1..CSI_PIXCLK is inverted before applied to internal circuitry
| #define CSI_CR1_PACK_DIR | ( | x | ) |
PACK_DIR 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
| #define CSI_CR1_PACK_DIR | ( | x | ) |
PACK_DIR 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
| #define CSI_CR1_PACK_DIR | ( | x | ) |
PACK_DIR 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
| #define CSI_CR1_PIXEL_BIT | ( | x | ) |
PIXEL_BIT 0b0..8-bit data for each pixel 0b1..10-bit data for each pixel
| #define CSI_CR1_PIXEL_BIT | ( | x | ) |
PIXEL_BIT 0b0..8-bit data for each pixel 0b1..10-bit data for each pixel
| #define CSI_CR1_PIXEL_BIT | ( | x | ) |
PIXEL_BIT 0b0..8-bit data for each pixel 0b1..10-bit data for each pixel
| #define CSI_CR1_PrP_IF_EN | ( | x | ) |
PrP_IF_EN 0b0..CSI to PrP bus is disabled 0b1..CSI to PrP bus is enabled
| #define CSI_CR1_REDGE | ( | x | ) |
REDGE 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
| #define CSI_CR1_REDGE | ( | x | ) |
REDGE 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
| #define CSI_CR1_REDGE | ( | x | ) |
REDGE 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
| #define CSI_CR1_RF_OR_INTEN | ( | x | ) |
RF_OR_INTEN 0b0..RxFIFO overrun interrupt is disabled 0b1..RxFIFO overrun interrupt is enabled
| #define CSI_CR1_RF_OR_INTEN | ( | x | ) |
RF_OR_INTEN 0b0..RxFIFO overrun interrupt is disabled 0b1..RxFIFO overrun interrupt is enabled
| #define CSI_CR1_RF_OR_INTEN | ( | x | ) |
RF_OR_INTEN 0b0..RxFIFO overrun interrupt is disabled 0b1..RxFIFO overrun interrupt is enabled
| #define CSI_CR1_RXFF_INTEN | ( | x | ) |
RXFF_INTEN 0b0..RxFIFO full interrupt disable 0b1..RxFIFO full interrupt enable
| #define CSI_CR1_RXFF_INTEN | ( | x | ) |
RXFF_INTEN 0b0..RxFIFO full interrupt disable 0b1..RxFIFO full interrupt enable
| #define CSI_CR1_RXFF_INTEN | ( | x | ) |
RXFF_INTEN 0b0..RxFIFO full interrupt disable 0b1..RxFIFO full interrupt enable
| #define CSI_CR1_SF_OR_INTEN | ( | x | ) |
SF_OR_INTEN 0b0..STATFIFO overrun interrupt is disabled 0b1..STATFIFO overrun interrupt is enabled
| #define CSI_CR1_SF_OR_INTEN | ( | x | ) |
SF_OR_INTEN 0b0..STATFIFO overrun interrupt is disabled 0b1..STATFIFO overrun interrupt is enabled
| #define CSI_CR1_SF_OR_INTEN | ( | x | ) |
SF_OR_INTEN 0b0..STATFIFO overrun interrupt is disabled 0b1..STATFIFO overrun interrupt is enabled
| #define CSI_CR1_SFF_DMA_DONE_INTEN | ( | x | ) |
SFF_DMA_DONE_INTEN 0b0..STATFIFO DMA Transfer Done interrupt disable 0b1..STATFIFO DMA Transfer Done interrupt enable
| #define CSI_CR1_SFF_DMA_DONE_INTEN | ( | x | ) |
SFF_DMA_DONE_INTEN 0b0..STATFIFO DMA Transfer Done interrupt disable 0b1..STATFIFO DMA Transfer Done interrupt enable
| #define CSI_CR1_SFF_DMA_DONE_INTEN | ( | x | ) |
SFF_DMA_DONE_INTEN 0b0..STATFIFO DMA Transfer Done interrupt disable 0b1..STATFIFO DMA Transfer Done interrupt enable
| #define CSI_CR1_SOF_INTEN | ( | x | ) |
SOF_INTEN 0b0..SOF interrupt disable 0b1..SOF interrupt enable
| #define CSI_CR1_SOF_INTEN | ( | x | ) |
SOF_INTEN 0b0..SOF interrupt disable 0b1..SOF interrupt enable
| #define CSI_CR1_SOF_INTEN | ( | x | ) |
SOF_INTEN 0b0..SOF interrupt disable 0b1..SOF interrupt enable
| #define CSI_CR1_SOF_POL | ( | x | ) |
SOF_POL 0b0..SOF interrupt is generated on SOF falling edge 0b1..SOF interrupt is generated on SOF rising edge
| #define CSI_CR1_SOF_POL | ( | x | ) |
SOF_POL 0b0..SOF interrupt is generated on SOF falling edge 0b1..SOF interrupt is generated on SOF rising edge
| #define CSI_CR1_SOF_POL | ( | x | ) |
SOF_POL 0b0..SOF interrupt is generated on SOF falling edge 0b1..SOF interrupt is generated on SOF rising edge
| #define CSI_CR1_STATFF_INTEN | ( | x | ) |
STATFF_INTEN 0b0..STATFIFO full interrupt disable 0b1..STATFIFO full interrupt enable
| #define CSI_CR1_STATFF_INTEN | ( | x | ) |
STATFF_INTEN 0b0..STATFIFO full interrupt disable 0b1..STATFIFO full interrupt enable
| #define CSI_CR1_STATFF_INTEN | ( | x | ) |
STATFF_INTEN 0b0..STATFIFO full interrupt disable 0b1..STATFIFO full interrupt enable
| #define CSI_CR1_SWAP16_EN | ( | x | ) |
SWAP16_EN 0b0..Disable swapping 0b1..Enable swapping
| #define CSI_CR1_SWAP16_EN | ( | x | ) |
SWAP16_EN 0b0..Disable swapping 0b1..Enable swapping
| #define CSI_CR1_SWAP16_EN | ( | x | ) |
SWAP16_EN 0b0..Disable swapping 0b1..Enable swapping
| #define CSI_CR1_VIDEO_MODE | ( | x | ) |
VIDEO_MODE 0b0..Progressive mode is selected 0b1..Interlace mode is selected
| #define CSI_CR1_VIDEO_MODE | ( | x | ) |
VIDEO_MODE 0b0..Progressive mode is selected 0b1..Interlace mode is selected
| #define CSI_CR20_10BIT_NEW_EN | ( | x | ) |
10BIT_NEW_EN 0b0..When input 8bits data, it will use the data[9:2] 0b1..If input is 10bits data, it will use the data[7:0] (optional)
| #define CSI_CR20_10BIT_NEW_EN | ( | x | ) |
10BIT_NEW_EN 0b0..When input 8bits data, it will use the data[9:2] 0b1..If input is 10bits data, it will use the data[7:0] (optional)
| #define CSI_CR20_BIG_END | ( | x | ) |
BIG_END 0b0..The newest (most recent) data will be assigned the lowest position when store to memory. 0b1..The newest (most recent) data will be assigned the highest position when store to memory.
| #define CSI_CR20_BIG_END | ( | x | ) |
BIG_END 0b0..The newest (most recent) data will be assigned the lowest position when store to memory. 0b1..The newest (most recent) data will be assigned the highest position when store to memory.
| #define CSI_CR20_BINARY_EN | ( | x | ) |
BINARY_EN 0b0..Output is Y8 format(8 bits each pixel) 0b1..Output is Y1 format(1 bit each pixel)
| #define CSI_CR20_BINARY_EN | ( | x | ) |
BINARY_EN 0b0..Output is Y8 format(8 bits each pixel) 0b1..Output is Y1 format(1 bit each pixel)
| #define CSI_CR20_HISTOGRAM_EN | ( | x | ) |
HISTOGRAM_EN 0b0..Histogram disable 0b1..Histogram enable
| #define CSI_CR20_HISTOGRAM_EN | ( | x | ) |
HISTOGRAM_EN 0b0..Histogram disable 0b1..Histogram enable
| #define CSI_CR20_QR_DATA_FORMAT | ( | x | ) |
QR_DATA_FORMAT 0b000..YU YV one cycle per 1 pixel input 0b001..UY VY one cycle per1 pixel input 0b010..Y U Y V two cycles per 1 pixel input 0b011..U Y V Y two cycles per 1 pixel input 0b100..YUV one cycle per 1 pixel input 0b101..Y U V three cycles per 1 pixel input
| #define CSI_CR20_QR_DATA_FORMAT | ( | x | ) |
QR_DATA_FORMAT 0b000..YU YV one cycle per 1 pixel input 0b001..UY VY one cycle per1 pixel input 0b010..Y U Y V two cycles per 1 pixel input 0b011..U Y V Y two cycles per 1 pixel input 0b100..YUV one cycle per 1 pixel input 0b101..Y U V three cycles per 1 pixel input
| #define CSI_CR20_QRCODE_EN | ( | x | ) |
QRCODE_EN 0b0..Normal mode 0b1..Gray scale mode
| #define CSI_CR20_QRCODE_EN | ( | x | ) |
QRCODE_EN 0b0..Normal mode 0b1..Gray scale mode
| #define CSI_CR20_THRESHOLD | ( | x | ) |
| #define CSI_CR20_THRESHOLD | ( | x | ) |
| #define CSI_CR2_AFS | ( | x | ) |
AFS 0b00..Abs Diff on consecutive green pixels 0b01..Abs Diff on every third green pixels 0b1x..Abs Diff on every four green pixels
| #define CSI_CR2_AFS | ( | x | ) |
AFS 0b00..Abs Diff on consecutive green pixels 0b01..Abs Diff on every third green pixels 0b1x..Abs Diff on every four green pixels
| #define CSI_CR2_AFS | ( | x | ) |
AFS 0b00..Abs Diff on consecutive green pixels 0b01..Abs Diff on every third green pixels 0b1x..Abs Diff on every four green pixels
| #define CSI_CR2_BTS | ( | x | ) |
BTS 0b00..GR 0b01..RG 0b10..BG 0b11..GB
| #define CSI_CR2_BTS | ( | x | ) |
BTS 0b00..GR 0b01..RG 0b10..BG 0b11..GB
| #define CSI_CR2_BTS | ( | x | ) |
BTS 0b00..GR 0b01..RG 0b10..BG 0b11..GB
| #define CSI_CR2_DMA_BURST_TYPE_RFF | ( | x | ) |
DMA_BURST_TYPE_RFF 0bx0..INCR8 0b01..INCR4 0b11..INCR16
| #define CSI_CR2_DMA_BURST_TYPE_RFF | ( | x | ) |
DMA_BURST_TYPE_RFF 0bx0..INCR8 0b01..INCR4 0b11..INCR16
| #define CSI_CR2_DMA_BURST_TYPE_RFF | ( | x | ) |
DMA_BURST_TYPE_RFF 0bx0..INCR8 0b01..INCR4 0b11..INCR16
| #define CSI_CR2_DMA_BURST_TYPE_SFF | ( | x | ) |
DMA_BURST_TYPE_SFF 0bx0..INCR8 0b01..INCR4 0b11..INCR16
| #define CSI_CR2_DMA_BURST_TYPE_SFF | ( | x | ) |
DMA_BURST_TYPE_SFF 0bx0..INCR8 0b01..INCR4 0b11..INCR16
| #define CSI_CR2_DMA_BURST_TYPE_SFF | ( | x | ) |
DMA_BURST_TYPE_SFF 0bx0..INCR8 0b01..INCR4 0b11..INCR16
| #define CSI_CR2_DRM | ( | x | ) |
DRM 0b0..Stats grid of 8 x 6 0b1..Stats grid of 8 x 12
| #define CSI_CR2_DRM | ( | x | ) |
DRM 0b0..Stats grid of 8 x 6 0b1..Stats grid of 8 x 12
| #define CSI_CR2_DRM | ( | x | ) |
DRM 0b0..Stats grid of 8 x 6 0b1..Stats grid of 8 x 12
| #define CSI_CR2_HSC | ( | x | ) |
HSC 0b00000000-0b11111111..Number of pixels to skip minus 1
| #define CSI_CR2_HSC | ( | x | ) |
HSC 0b00000000-0b11111111..Number of pixels to skip minus 1
| #define CSI_CR2_HSC | ( | x | ) |
HSC 0b00000000-0b11111111..Number of pixels to skip minus 1
| #define CSI_CR2_LVRM | ( | x | ) |
LVRM 0b000..512 x 384 0b001..448 x 336 0b010..384 x 288 0b011..384 x 256 0b100..320 x 240 0b101..288 x 216 0b110..400 x 300
| #define CSI_CR2_LVRM | ( | x | ) |
LVRM 0b000..512 x 384 0b001..448 x 336 0b010..384 x 288 0b011..384 x 256 0b100..320 x 240 0b101..288 x 216 0b110..400 x 300
| #define CSI_CR2_LVRM | ( | x | ) |
LVRM 0b000..512 x 384 0b001..448 x 336 0b010..384 x 288 0b011..384 x 256 0b100..320 x 240 0b101..288 x 216 0b110..400 x 300
| #define CSI_CR2_SCE | ( | x | ) |
SCE 0b0..Skip count disable 0b1..Skip count enable
| #define CSI_CR2_SCE | ( | x | ) |
SCE 0b0..Skip count disable 0b1..Skip count enable
| #define CSI_CR2_SCE | ( | x | ) |
SCE 0b0..Skip count disable 0b1..Skip count enable
| #define CSI_CR2_VSC | ( | x | ) |
VSC 0b00000000-0b11111111..Number of rows to skip minus 1
| #define CSI_CR2_VSC | ( | x | ) |
VSC 0b00000000-0b11111111..Number of rows to skip minus 1
| #define CSI_CR2_VSC | ( | x | ) |
VSC 0b00000000-0b11111111..Number of rows to skip minus 1
| #define CSI_CR3_DMA_REFLASH_RFF | ( | x | ) |
DMA_REFLASH_RFF 0b0..No reflashing 0b1..Reflash the embedded DMA controller
| #define CSI_CR3_DMA_REFLASH_RFF | ( | x | ) |
DMA_REFLASH_RFF 0b0..No reflashing 0b1..Reflash the embedded DMA controller
| #define CSI_CR3_DMA_REFLASH_RFF | ( | x | ) |
DMA_REFLASH_RFF 0b0..No reflashing 0b1..Reflash the embedded DMA controller
| #define CSI_CR3_DMA_REFLASH_SFF | ( | x | ) |
DMA_REFLASH_SFF 0b0..No reflashing 0b1..Reflash the embedded DMA controller
| #define CSI_CR3_DMA_REFLASH_SFF | ( | x | ) |
DMA_REFLASH_SFF 0b0..No reflashing 0b1..Reflash the embedded DMA controller
| #define CSI_CR3_DMA_REFLASH_SFF | ( | x | ) |
DMA_REFLASH_SFF 0b0..No reflashing 0b1..Reflash the embedded DMA controller
| #define CSI_CR3_DMA_REQ_EN_RFF | ( | x | ) |
DMA_REQ_EN_RFF 0b0..Disable the dma request 0b1..Enable the dma request
| #define CSI_CR3_DMA_REQ_EN_RFF | ( | x | ) |
DMA_REQ_EN_RFF 0b0..Disable the dma request 0b1..Enable the dma request
| #define CSI_CR3_DMA_REQ_EN_RFF | ( | x | ) |
DMA_REQ_EN_RFF 0b0..Disable the dma request 0b1..Enable the dma request
| #define CSI_CR3_DMA_REQ_EN_SFF | ( | x | ) |
DMA_REQ_EN_SFF 0b0..Disable the dma request 0b1..Enable the dma request
| #define CSI_CR3_DMA_REQ_EN_SFF | ( | x | ) |
DMA_REQ_EN_SFF 0b0..Disable the dma request 0b1..Enable the dma request
| #define CSI_CR3_DMA_REQ_EN_SFF | ( | x | ) |
DMA_REQ_EN_SFF 0b0..Disable the dma request 0b1..Enable the dma request
| #define CSI_CR3_ECC_AUTO_EN | ( | x | ) |
ECC_AUTO_EN 0b0..Auto Error correction is disabled. 0b1..Auto Error correction is enabled.
| #define CSI_CR3_ECC_AUTO_EN | ( | x | ) |
ECC_AUTO_EN 0b0..Auto Error correction is disabled. 0b1..Auto Error correction is enabled.
| #define CSI_CR3_ECC_AUTO_EN | ( | x | ) |
ECC_AUTO_EN 0b0..Auto Error correction is disabled. 0b1..Auto Error correction is enabled.
| #define CSI_CR3_ECC_INT_EN | ( | x | ) |
ECC_INT_EN 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. 0b1..Interrupt is generated when error is detected.
| #define CSI_CR3_ECC_INT_EN | ( | x | ) |
ECC_INT_EN 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. 0b1..Interrupt is generated when error is detected.
| #define CSI_CR3_ECC_INT_EN | ( | x | ) |
ECC_INT_EN 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. 0b1..Interrupt is generated when error is detected.
| #define CSI_CR3_FRMCNT | ( | x | ) |
| #define CSI_CR3_FRMCNT | ( | x | ) |
| #define CSI_CR3_FRMCNT | ( | x | ) |
| #define CSI_CR3_FRMCNT_RST | ( | x | ) |
FRMCNT_RST 0b0..Do not reset 0b1..Reset frame counter immediately
| #define CSI_CR3_FRMCNT_RST | ( | x | ) |
FRMCNT_RST 0b0..Do not reset 0b1..Reset frame counter immediately
| #define CSI_CR3_FRMCNT_RST | ( | x | ) |
FRMCNT_RST 0b0..Do not reset 0b1..Reset frame counter immediately
| #define CSI_CR3_HRESP_ERR_EN | ( | x | ) |
HRESP_ERR_EN 0b0..Disable hresponse error interrupt 0b1..Enable hresponse error interrupt
| #define CSI_CR3_HRESP_ERR_EN | ( | x | ) |
HRESP_ERR_EN 0b0..Disable hresponse error interrupt 0b1..Enable hresponse error interrupt
| #define CSI_CR3_HRESP_ERR_EN | ( | x | ) |
HRESP_ERR_EN 0b0..Disable hresponse error interrupt 0b1..Enable hresponse error interrupt
| #define CSI_CR3_RxFF_LEVEL | ( | x | ) |
RxFF_LEVEL 0b000..4 Double words 0b001..8 Double words 0b010..16 Double words 0b011..24 Double words 0b100..32 Double words 0b101..48 Double words 0b110..64 Double words 0b111..96 Double words
| #define CSI_CR3_RxFF_LEVEL | ( | x | ) |
RxFF_LEVEL 0b000..4 Double words 0b001..8 Double words 0b010..16 Double words 0b011..24 Double words 0b100..32 Double words 0b101..48 Double words 0b110..64 Double words 0b111..96 Double words
| #define CSI_CR3_RxFF_LEVEL | ( | x | ) |
RxFF_LEVEL 0b000..4 Double words 0b001..8 Double words 0b010..16 Double words 0b011..24 Double words 0b100..32 Double words 0b101..48 Double words 0b110..64 Double words 0b111..96 Double words
| #define CSI_CR3_SENSOR_16BITS | ( | x | ) |
SENSOR_16BITS 0b0..Only one 8-bit sensor is connected. 0b1..One 16-bit sensor is connected.
| #define CSI_CR3_SENSOR_16BITS | ( | x | ) |
SENSOR_16BITS 0b0..Only one 8-bit sensor is connected. 0b1..One 16-bit sensor is connected.
| #define CSI_CR3_SENSOR_16BITS | ( | x | ) |
SENSOR_16BITS 0b0..Only one 8-bit sensor is connected. 0b1..One 16-bit sensor is connected.
| #define CSI_CR3_STATFF_LEVEL | ( | x | ) |
STATFF_LEVEL 0b000..4 Double words 0b001..8 Double words 0b010..12 Double words 0b011..16 Double words 0b100..24 Double words 0b101..32 Double words 0b110..48 Double words 0b111..64 Double words
| #define CSI_CR3_STATFF_LEVEL | ( | x | ) |
STATFF_LEVEL 0b000..4 Double words 0b001..8 Double words 0b010..12 Double words 0b011..16 Double words 0b100..24 Double words 0b101..32 Double words 0b110..48 Double words 0b111..64 Double words
| #define CSI_CR3_STATFF_LEVEL | ( | x | ) |
STATFF_LEVEL 0b000..4 Double words 0b001..8 Double words 0b010..12 Double words 0b011..16 Double words 0b100..24 Double words 0b101..32 Double words 0b110..48 Double words 0b111..64 Double words
| #define CSI_CR3_ZERO_PACK_EN | ( | x | ) |
ZERO_PACK_EN 0b0..Zero packing disabled 0b1..Zero packing enabled
| #define CSI_CR3_ZERO_PACK_EN | ( | x | ) |
ZERO_PACK_EN 0b0..Zero packing disabled 0b1..Zero packing enabled
| #define CSI_CR3_ZERO_PACK_EN | ( | x | ) |
ZERO_PACK_EN 0b0..Zero packing disabled 0b1..Zero packing enabled
| #define CSI_CR_PIXEL_COUNTERS | ( | x | ) |
| #define CSI_CR_PIXEL_COUNTERS | ( | x | ) |
| #define CSI_DMASA_FB1_DMA_START_ADDR_FB1 | ( | x | ) |
| #define CSI_DMASA_FB1_DMA_START_ADDR_FB1 | ( | x | ) |
| #define CSI_DMASA_FB1_DMA_START_ADDR_FB1 | ( | x | ) |
| #define CSI_DMASA_FB2_DMA_START_ADDR_FB2 | ( | x | ) |
| #define CSI_DMASA_FB2_DMA_START_ADDR_FB2 | ( | x | ) |
| #define CSI_DMASA_FB2_DMA_START_ADDR_FB2 | ( | x | ) |
| #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF | ( | x | ) |
| #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF | ( | x | ) |
| #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF | ( | x | ) |
| #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF | ( | x | ) |
| #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF | ( | x | ) |
| #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF | ( | x | ) |
| #define CSI_FBUF_PARA_DEINTERLACE_STRIDE | ( | x | ) |
| #define CSI_FBUF_PARA_DEINTERLACE_STRIDE | ( | x | ) |
| #define CSI_FBUF_PARA_DEINTERLACE_STRIDE | ( | x | ) |
| #define CSI_FBUF_PARA_FBUF_STRIDE | ( | x | ) |
| #define CSI_FBUF_PARA_FBUF_STRIDE | ( | x | ) |
| #define CSI_FBUF_PARA_FBUF_STRIDE | ( | x | ) |
| #define CSI_IMAG_PARA_IMAGE_HEIGHT | ( | x | ) |
| #define CSI_IMAG_PARA_IMAGE_HEIGHT | ( | x | ) |
| #define CSI_IMAG_PARA_IMAGE_HEIGHT | ( | x | ) |
| #define CSI_IMAG_PARA_IMAGE_WIDTH | ( | x | ) |
| #define CSI_IMAG_PARA_IMAGE_WIDTH | ( | x | ) |
| #define CSI_IMAG_PARA_IMAGE_WIDTH | ( | x | ) |
| #define CSI_RFIFO_IMAGE | ( | x | ) |
| #define CSI_RFIFO_IMAGE | ( | x | ) |
| #define CSI_RFIFO_IMAGE | ( | x | ) |
| #define CSI_RXCNT_RXCNT | ( | x | ) |
| #define CSI_RXCNT_RXCNT | ( | x | ) |
| #define CSI_RXCNT_RXCNT | ( | x | ) |
| #define CSI_SR_BASEADDR_CHHANGE_ERROR | ( | x | ) |
| #define CSI_SR_BASEADDR_CHHANGE_ERROR | ( | x | ) |
| #define CSI_SR_BASEADDR_CHHANGE_ERROR | ( | x | ) |
| #define CSI_SR_COF_INT | ( | x | ) |
COF_INT 0b0..Video field has no change. 0b1..Change of video field is detected.
| #define CSI_SR_COF_INT | ( | x | ) |
COF_INT 0b0..Video field has no change. 0b1..Change of video field is detected.
| #define CSI_SR_COF_INT | ( | x | ) |
COF_INT 0b0..Video field has no change. 0b1..Change of video field is detected.
| #define CSI_SR_DMA_FIELD0_DONE | ( | x | ) |
| #define CSI_SR_DMA_FIELD0_DONE | ( | x | ) |
| #define CSI_SR_DMA_FIELD0_DONE | ( | x | ) |
| #define CSI_SR_DMA_FIELD1_DONE | ( | x | ) |
| #define CSI_SR_DMA_FIELD1_DONE | ( | x | ) |
| #define CSI_SR_DMA_FIELD1_DONE | ( | x | ) |
| #define CSI_SR_DMA_TSF_DONE_FB1 | ( | x | ) |
DMA_TSF_DONE_FB1 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DMA_TSF_DONE_FB1 | ( | x | ) |
DMA_TSF_DONE_FB1 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DMA_TSF_DONE_FB1 | ( | x | ) |
DMA_TSF_DONE_FB1 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DMA_TSF_DONE_FB2 | ( | x | ) |
DMA_TSF_DONE_FB2 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DMA_TSF_DONE_FB2 | ( | x | ) |
DMA_TSF_DONE_FB2 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DMA_TSF_DONE_FB2 | ( | x | ) |
DMA_TSF_DONE_FB2 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DMA_TSF_DONE_SFF | ( | x | ) |
DMA_TSF_DONE_SFF 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DMA_TSF_DONE_SFF | ( | x | ) |
DMA_TSF_DONE_SFF 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DMA_TSF_DONE_SFF | ( | x | ) |
DMA_TSF_DONE_SFF 0b0..DMA transfer is not completed. 0b1..DMA transfer is completed.
| #define CSI_SR_DRDY | ( | x | ) |
DRDY 0b0..No data (word) is ready 0b1..At least 1 datum (word) is ready in RXFIFO.
| #define CSI_SR_DRDY | ( | x | ) |
DRDY 0b0..No data (word) is ready 0b1..At least 1 datum (word) is ready in RXFIFO.
| #define CSI_SR_DRDY | ( | x | ) |
DRDY 0b0..No data (word) is ready 0b1..At least 1 datum (word) is ready in RXFIFO.
| #define CSI_SR_ECC_INT | ( | x | ) |
ECC_INT 0b0..No error detected 0b1..Error is detected in BT.656 coding
| #define CSI_SR_ECC_INT | ( | x | ) |
ECC_INT 0b0..No error detected 0b1..Error is detected in BT.656 coding
| #define CSI_SR_ECC_INT | ( | x | ) |
ECC_INT 0b0..No error detected 0b1..Error is detected in BT.656 coding
| #define CSI_SR_EOF_INT | ( | x | ) |
EOF_INT 0b0..EOF is not detected. 0b1..EOF is detected.
| #define CSI_SR_EOF_INT | ( | x | ) |
EOF_INT 0b0..EOF is not detected. 0b1..EOF is detected.
| #define CSI_SR_EOF_INT | ( | x | ) |
EOF_INT 0b0..EOF is not detected. 0b1..EOF is detected.
| #define CSI_SR_F1_INT | ( | x | ) |
F1_INT 0b0..Field 1 of video is not detected. 0b1..Field 1 of video is about to start.
| #define CSI_SR_F1_INT | ( | x | ) |
F1_INT 0b0..Field 1 of video is not detected. 0b1..Field 1 of video is about to start.
| #define CSI_SR_F1_INT | ( | x | ) |
F1_INT 0b0..Field 1 of video is not detected. 0b1..Field 1 of video is about to start.
| #define CSI_SR_F2_INT | ( | x | ) |
F2_INT 0b0..Field 2 of video is not detected 0b1..Field 2 of video is about to start
| #define CSI_SR_F2_INT | ( | x | ) |
F2_INT 0b0..Field 2 of video is not detected 0b1..Field 2 of video is about to start
| #define CSI_SR_F2_INT | ( | x | ) |
F2_INT 0b0..Field 2 of video is not detected 0b1..Field 2 of video is about to start
| #define CSI_SR_HISTOGRAM_CALC_DONE_INT | ( | x | ) |
HISTOGRAM_CALC_DONE_INT 0b0..Histogram calculation is not finished 0b1..Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level
| #define CSI_SR_HISTOGRAM_CALC_DONE_INT | ( | x | ) |
HISTOGRAM_CALC_DONE_INT 0b0..Histogram calculation is not finished 0b1..Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level
| #define CSI_SR_HRESP_ERR_INT | ( | x | ) |
HRESP_ERR_INT 0b0..No hresponse error. 0b1..Hresponse error is detected.
| #define CSI_SR_HRESP_ERR_INT | ( | x | ) |
HRESP_ERR_INT 0b0..No hresponse error. 0b1..Hresponse error is detected.
| #define CSI_SR_HRESP_ERR_INT | ( | x | ) |
HRESP_ERR_INT 0b0..No hresponse error. 0b1..Hresponse error is detected.
| #define CSI_SR_RF_OR_INT | ( | x | ) |
RF_OR_INT 0b0..RXFIFO has not overflowed. 0b1..RXFIFO has overflowed.
| #define CSI_SR_RF_OR_INT | ( | x | ) |
RF_OR_INT 0b0..RXFIFO has not overflowed. 0b1..RXFIFO has overflowed.
| #define CSI_SR_RF_OR_INT | ( | x | ) |
RF_OR_INT 0b0..RXFIFO has not overflowed. 0b1..RXFIFO has overflowed.
| #define CSI_SR_RxFF_INT | ( | x | ) |
RxFF_INT 0b0..RxFIFO is not full. 0b1..RxFIFO is full.
| #define CSI_SR_RxFF_INT | ( | x | ) |
RxFF_INT 0b0..RxFIFO is not full. 0b1..RxFIFO is full.
| #define CSI_SR_RxFF_INT | ( | x | ) |
RxFF_INT 0b0..RxFIFO is not full. 0b1..RxFIFO is full.
| #define CSI_SR_SF_OR_INT | ( | x | ) |
SF_OR_INT 0b0..STATFIFO has not overflowed. 0b1..STATFIFO has overflowed.
| #define CSI_SR_SF_OR_INT | ( | x | ) |
SF_OR_INT 0b0..STATFIFO has not overflowed. 0b1..STATFIFO has overflowed.
| #define CSI_SR_SF_OR_INT | ( | x | ) |
SF_OR_INT 0b0..STATFIFO has not overflowed. 0b1..STATFIFO has overflowed.
| #define CSI_SR_SOF_INT | ( | x | ) |
SOF_INT 0b0..SOF is not detected. 0b1..SOF is detected.
| #define CSI_SR_SOF_INT | ( | x | ) |
SOF_INT 0b0..SOF is not detected. 0b1..SOF is detected.
| #define CSI_SR_SOF_INT | ( | x | ) |
SOF_INT 0b0..SOF is not detected. 0b1..SOF is detected.
| #define CSI_SR_STATFF_INT | ( | x | ) |
STATFF_INT 0b0..STATFIFO is not full. 0b1..STATFIFO is full.
| #define CSI_SR_STATFF_INT | ( | x | ) |
STATFF_INT 0b0..STATFIFO is not full. 0b1..STATFIFO is full.
| #define CSI_SR_STATFF_INT | ( | x | ) |
STATFF_INT 0b0..STATFIFO is not full. 0b1..STATFIFO is full.
| #define CSI_STATFIFO_STAT | ( | x | ) |
| #define CSI_STATFIFO_STAT | ( | x | ) |
| #define CSI_STATFIFO_STAT | ( | x | ) |
1.18.0