Memory Protection Unit (MPU)

Type definitions for the Memory Protection Unit (MPU). More...

Topics
	Floating Point Unit (FPU)
	Type definitions for the Floating Point Unit (FPU).

Data Structures
struct	MPU_Type
	Structure type to access the Memory Protection Unit (MPU). More...
#define	MPU_TYPE_RALIASES   4U
#define	MPU_TYPE_IREGION_Pos   16U
#define	MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
#define	MPU_TYPE_DREGION_Pos   8U
#define	MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
#define	MPU_TYPE_SEPARATE_Pos   0U
#define	MPU_TYPE_SEPARATE_Msk   (1UL )
#define	MPU_CTRL_PRIVDEFENA_Pos   2U
#define	MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
#define	MPU_CTRL_HFNMIENA_Pos   1U
#define	MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
#define	MPU_CTRL_ENABLE_Pos   0U
#define	MPU_CTRL_ENABLE_Msk   (1UL )
#define	MPU_RNR_REGION_Pos   0U
#define	MPU_RNR_REGION_Msk   (0xFFUL )
#define	MPU_RBAR_ADDR_Pos   5U
#define	MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
#define	MPU_RBAR_VALID_Pos   4U
#define	MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
#define	MPU_RBAR_REGION_Pos   0U
#define	MPU_RBAR_REGION_Msk   (0xFUL )
#define	MPU_RASR_ATTRS_Pos   16U
#define	MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
#define	MPU_RASR_XN_Pos   28U
#define	MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
#define	MPU_RASR_AP_Pos   24U
#define	MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
#define	MPU_RASR_TEX_Pos   19U
#define	MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
#define	MPU_RASR_S_Pos   18U
#define	MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
#define	MPU_RASR_C_Pos   17U
#define	MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
#define	MPU_RASR_B_Pos   16U
#define	MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
#define	MPU_RASR_SRD_Pos   8U
#define	MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
#define	MPU_RASR_SIZE_Pos   1U
#define	MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
#define	MPU_RASR_ENABLE_Pos   0U
#define	MPU_RASR_ENABLE_Msk   (1UL )
#define	MPU_TYPE_RALIASES   4U
#define	MPU_TYPE_IREGION_Pos   16U
#define	MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
#define	MPU_TYPE_DREGION_Pos   8U
#define	MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
#define	MPU_TYPE_SEPARATE_Pos   0U
#define	MPU_TYPE_SEPARATE_Msk   (1UL )
#define	MPU_CTRL_PRIVDEFENA_Pos   2U
#define	MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
#define	MPU_CTRL_HFNMIENA_Pos   1U
#define	MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
#define	MPU_CTRL_ENABLE_Pos   0U
#define	MPU_CTRL_ENABLE_Msk   (1UL )
#define	MPU_RNR_REGION_Pos   0U
#define	MPU_RNR_REGION_Msk   (0xFFUL )
#define	MPU_RBAR_ADDR_Pos   5U
#define	MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
#define	MPU_RBAR_VALID_Pos   4U
#define	MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
#define	MPU_RBAR_REGION_Pos   0U
#define	MPU_RBAR_REGION_Msk   (0xFUL )
#define	MPU_RASR_ATTRS_Pos   16U
#define	MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
#define	MPU_RASR_XN_Pos   28U
#define	MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
#define	MPU_RASR_AP_Pos   24U
#define	MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
#define	MPU_RASR_TEX_Pos   19U
#define	MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
#define	MPU_RASR_S_Pos   18U
#define	MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
#define	MPU_RASR_C_Pos   17U
#define	MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
#define	MPU_RASR_B_Pos   16U
#define	MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
#define	MPU_RASR_SRD_Pos   8U
#define	MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
#define	MPU_RASR_SIZE_Pos   1U
#define	MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
#define	MPU_RASR_ENABLE_Pos   0U
#define	MPU_RASR_ENABLE_Msk   (1UL )

Detailed Description

Type definitions for the Memory Protection Unit (MPU).

Macro Definition Documentation

MPU_CTRL_ENABLE_Msk [1/2]

#define MPU_CTRL_ENABLE_Msk   (1UL )

MPU CTRL: ENABLE Mask

MPU_CTRL_ENABLE_Msk [2/2]

#define MPU_CTRL_ENABLE_Msk   (1UL )

MPU CTRL: ENABLE Mask

MPU_CTRL_ENABLE_Pos [1/2]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

MPU_CTRL_ENABLE_Pos [2/2]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

MPU_CTRL_HFNMIENA_Msk [1/2]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

MPU_CTRL_HFNMIENA_Msk [2/2]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

MPU_CTRL_HFNMIENA_Pos [1/2]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

MPU_CTRL_HFNMIENA_Pos [2/2]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

MPU_CTRL_PRIVDEFENA_Msk [1/2]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

MPU_CTRL_PRIVDEFENA_Msk [2/2]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

MPU_CTRL_PRIVDEFENA_Pos [1/2]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

MPU_CTRL_PRIVDEFENA_Pos [2/2]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

MPU_RASR_AP_Msk [1/2]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

MPU_RASR_AP_Msk [2/2]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

MPU_RASR_AP_Pos [1/2]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

MPU_RASR_AP_Pos [2/2]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

MPU_RASR_ATTRS_Msk [1/2]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

MPU_RASR_ATTRS_Msk [2/2]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

MPU_RASR_ATTRS_Pos [1/2]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

MPU_RASR_ATTRS_Pos [2/2]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

MPU_RASR_B_Msk [1/2]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

MPU_RASR_B_Msk [2/2]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

MPU_RASR_B_Pos [1/2]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

MPU_RASR_B_Pos [2/2]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

MPU_RASR_C_Msk [1/2]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

MPU_RASR_C_Msk [2/2]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

MPU_RASR_C_Pos [1/2]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

MPU_RASR_C_Pos [2/2]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

MPU_RASR_ENABLE_Msk [1/2]

#define MPU_RASR_ENABLE_Msk   (1UL )

MPU RASR: Region enable bit Disable Mask

MPU_RASR_ENABLE_Msk [2/2]

#define MPU_RASR_ENABLE_Msk   (1UL )

MPU RASR: Region enable bit Disable Mask

MPU_RASR_ENABLE_Pos [1/2]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

MPU_RASR_ENABLE_Pos [2/2]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

MPU_RASR_S_Msk [1/2]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

MPU_RASR_S_Msk [2/2]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

MPU_RASR_S_Pos [1/2]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

MPU_RASR_S_Pos [2/2]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

MPU_RASR_SIZE_Msk [1/2]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

MPU_RASR_SIZE_Msk [2/2]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

MPU_RASR_SIZE_Pos [1/2]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

MPU_RASR_SIZE_Pos [2/2]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

MPU_RASR_SRD_Msk [1/2]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

MPU_RASR_SRD_Msk [2/2]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

MPU_RASR_SRD_Pos [1/2]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

MPU_RASR_SRD_Pos [2/2]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

MPU_RASR_TEX_Msk [1/2]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

MPU_RASR_TEX_Msk [2/2]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

MPU_RASR_TEX_Pos [1/2]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

MPU_RASR_TEX_Pos [2/2]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

MPU_RASR_XN_Msk [1/2]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

MPU_RASR_XN_Msk [2/2]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

MPU_RASR_XN_Pos [1/2]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

MPU_RASR_XN_Pos [2/2]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

MPU_RBAR_ADDR_Msk [1/2]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

MPU_RBAR_ADDR_Msk [2/2]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

MPU_RBAR_ADDR_Pos [1/2]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

MPU_RBAR_ADDR_Pos [2/2]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

MPU_RBAR_REGION_Msk [1/2]

#define MPU_RBAR_REGION_Msk   (0xFUL )

MPU RBAR: REGION Mask

MPU_RBAR_REGION_Msk [2/2]

#define MPU_RBAR_REGION_Msk   (0xFUL )

MPU RBAR: REGION Mask

MPU_RBAR_REGION_Pos [1/2]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

MPU_RBAR_REGION_Pos [2/2]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

MPU_RBAR_VALID_Msk [1/2]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

MPU_RBAR_VALID_Msk [2/2]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

MPU_RBAR_VALID_Pos [1/2]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

MPU_RBAR_VALID_Pos [2/2]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

MPU_RNR_REGION_Msk [1/2]

#define MPU_RNR_REGION_Msk   (0xFFUL )

MPU RNR: REGION Mask

MPU_RNR_REGION_Msk [2/2]

#define MPU_RNR_REGION_Msk   (0xFFUL )

MPU RNR: REGION Mask

MPU_RNR_REGION_Pos [1/2]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

MPU_RNR_REGION_Pos [2/2]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

MPU_TYPE_DREGION_Msk [1/2]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

MPU_TYPE_DREGION_Msk [2/2]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

MPU_TYPE_DREGION_Pos [1/2]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

MPU_TYPE_DREGION_Pos [2/2]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

MPU_TYPE_IREGION_Msk [1/2]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

MPU_TYPE_IREGION_Msk [2/2]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

MPU_TYPE_IREGION_Pos [1/2]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

MPU_TYPE_IREGION_Pos [2/2]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

MPU_TYPE_SEPARATE_Msk [1/2]

#define MPU_TYPE_SEPARATE_Msk   (1UL )

MPU TYPE: SEPARATE Mask

MPU_TYPE_SEPARATE_Msk [2/2]

#define MPU_TYPE_SEPARATE_Msk   (1UL )

MPU TYPE: SEPARATE Mask

MPU_TYPE_SEPARATE_Pos [1/2]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

MPU_TYPE_SEPARATE_Pos [2/2]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position