RTEMS
6.3
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bsps
powerpc
mpc55xxevb
include
bsp
irq.h
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_POWERPC_IRQ_H
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#define LIBBSP_POWERPC_IRQ_H
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#include <
rtems/irq-extension.h
>
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#include <
rtems/irq.h
>
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#include <bspopts.h>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
/* __cplusplus */
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/*
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* Interrupt numbers
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*/
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#define MPC55XX_IRQ_INVALID 0x10000U
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#define MPC55XX_IRQ_MIN 0U
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/* Software interrupts */
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#define MPC55XX_IRQ_SOFTWARE_MIN 0U
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#define MPC55XX_IRQ_SOFTWARE_MAX 7U
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#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v)
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#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
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#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
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#if MPC55XX_CHIP_FAMILY == 551
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#define MPC55XX_IRQ_MAX 293U
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/* eDMA */
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#define MPC55XX_IRQ_EDMA_ERROR(group) \
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((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
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#define MPC55XX_IRQ_EDMA(ch) \
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((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
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/* I2C */
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#define MPC55XX_IRQ_I2C(mod) \
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((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID)
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/* SIU external interrupts */
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#define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
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#define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
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#define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
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#define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
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#define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
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/* PIT */
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#define MPC55XX_IRQ_RTI 148U
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#define MPC55XX_IRQ_PIT(timer) (148U + (timer))
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/* eTPU */
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#define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID
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/* DSPI */
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#define MPC55XX_IRQ_DSPI_BASE(mod) \
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((mod) == 0 ? 117U : \
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((mod) == 1 ? 122U : \
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((mod) == 2 ? 274U : \
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((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID))))
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/* eMIOS */
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#define MPC55XX_IRQ_EMIOS(ch) \
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((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID)
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/* eQADC */
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#define MPC55XX_IRQ_EQADC_BASE(mod) \
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((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID)
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/* eSCI */
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#define MPC55XX_IRQ_ESCI(mod) \
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((mod) == 0 ? 113U : \
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((mod) == 1 ? 114U : \
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((mod) == 2 ? 115U : \
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((mod) == 3 ? 116U : \
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((mod) == 4 ? 270U : \
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((mod) == 5 ? 271U : \
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((mod) == 6 ? 272U : \
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((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID))))))))
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/* FlexCAN */
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#define MPC55XX_IRQ_CAN_BASE(mod) \
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((mod) == 0 ? 127U : \
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((mod) == 1 ? 157U : \
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((mod) == 2 ? 178U : \
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((mod) == 3 ? 199U : \
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((mod) == 4 ? 220U : \
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((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID))))))
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/* FlexRay */
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#define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
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((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
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#elif MPC55XX_CHIP_FAMILY == 564
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#define MPC55XX_IRQ_MAX 255U
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/* eDMA */
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#define MPC55XX_IRQ_EDMA_ERROR(group) \
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((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
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#define MPC55XX_IRQ_EDMA(ch) \
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((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
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/* SWT */
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#define MPC55XX_IRQ_SWT_0 28U
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#define MPC55XX_IRQ_SWT_1 29U
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/* STM */
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#define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U)
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/* ECSM */
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#define MPC55XX_IRQ_ECSM_FAS 9U
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#define MPC55XX_IRQ_ECSM_NCE 35U
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#define MPC55XX_IRQ_ECSM_COR 36U
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/* MC */
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#define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U
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#define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U
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#define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U
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#define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U
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#define MPC55XX_IRQ_MC_RGM_FRAE 56U
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/* XOSC */
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#define MPC55XX_IRQ_XOSC 57U
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/* PIT */
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#define MPC55XX_IRQ_PIT_CHANNEL(ch) \
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((ch) == 3 ? 127U : ((ch) + 59U))
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/* SIU external interrupts */
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#define MPC55XX_IRQ_SIU_EXTERNAL_0 41U
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#define MPC55XX_IRQ_SIU_EXTERNAL_1 42U
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#define MPC55XX_IRQ_SIU_EXTERNAL_2 43U
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#define MPC55XX_IRQ_SIU_EXTERNAL_3 44U
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/* ADC */
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#define MPC55XX_IRQ_ADC_BASE(mod) \
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((mod) == 0 ? 62U : \
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((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID))
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/* DSPI */
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#define MPC55XX_IRQ_DSPI_BASE(mod) \
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((mod) == 0 ? 74U : \
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((mod) == 1 ? 94U : \
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((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID)))
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/* FlexCAN */
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#define MPC55XX_IRQ_CAN_BASE(mod) \
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((mod) == 0 ? 65U : \
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((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID))
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/* FlexPWM */
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#define MPC55XX_IRQ_FLEXPWM_BASE(mod) \
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((mod) == 0 ? 179U : \
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((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID))
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/* FlexRay */
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#define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
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((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID)
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/* LINFlexD */
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#define MPC55XX_IRQ_LINFLEX_BASE(mod) \
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((mod) == 0 ? 79U : \
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((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID))
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/* eTimer */
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#define MPC55XX_IRQ_ETIMER_BASE(mod) \
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((mod) == 0 ? 157U : \
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((mod) == 1 ? 168U : \
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((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID)))
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/* CTU */
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#define MPC55XX_IRQ_CTU_MRS 193U
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#define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U)
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#define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U)
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#define MPC55XX_IRQ_CTU_ADC 206U
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#define MPC55XX_IRQ_CTU_ERR 207U
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/* SEMA */
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#define MPC55XX_IRQ_SEMA_0 247U
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#define MPC55XX_IRQ_SEMA_1 248U
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/* FCCU */
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#define MPC55XX_IRQ_FCCU_ALRM 250U
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#define MPC55XX_IRQ_FCCU_CFG_TO 251U
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#define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U
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#define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U
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/* PMU */
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#define MPC55XX_IRQ_PMU 254U
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/* SWG */
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#define MPC55XX_IRQ_SWG 255U
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#elif MPC55XX_CHIP_FAMILY == 566
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#define MPC55XX_IRQ_MAX 315U
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/* eDMA */
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#define MPC55XX_IRQ_EDMA_ERROR(group) \
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((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
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#define MPC55XX_IRQ_EDMA(ch) \
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((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
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/* PIT */
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#define MPC55XX_IRQ_PIT_CHANNEL(ch) \
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((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID)
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/* SIU external interrupts */
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#define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
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#define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
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#define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
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#define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
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/* eMIOS */
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#define MPC55XX_IRQ_EMIOS(ch) \
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((unsigned) (ch) < 24U ? 58U + (ch) : \
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((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID))
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/* eSCI */
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#define MPC55XX_IRQ_ESCI(mod) \
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((unsigned) (mod) < 4U ? 113U + (mod) : \
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((unsigned) (mod) < 8U ? 270U + (mod) : \
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((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID)))
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#else
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#if MPC55XX_CHIP_FAMILY == 555
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#define MPC55XX_IRQ_MAX 307U
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#elif MPC55XX_CHIP_FAMILY == 556
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#define MPC55XX_IRQ_MAX 360U
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#elif MPC55XX_CHIP_FAMILY == 567
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#define MPC55XX_IRQ_MAX 479U
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#else
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#error "unsupported chip type"
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#endif
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/* eDMA */
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#define MPC55XX_IRQ_EDMA_ERROR(group) \
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((group) == 0 ? 10U : \
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((group) == 1 ? 210U : \
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((group) == 2 ? 425U : MPC55XX_IRQ_INVALID)))
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#define MPC55XX_IRQ_EDMA(ch) \
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((unsigned) (ch) < 32U ? 11U + (ch) : \
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((unsigned) (ch) < 64U ? 179U + (ch) : \
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((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID)))
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/* I2C */
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#define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID
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/* SIU external interrupts */
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#define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
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#define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
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#define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
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#define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
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#define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
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/* PIT */
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#define MPC55XX_IRQ_RTI 305U
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#define MPC55XX_IRQ_PIT(ch) (301U + (ch))
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/* eTPU */
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#define MPC55XX_IRQ_ETPU_BASE(mod) \
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((mod) == 0 ? 67U : \
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((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID))
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/* DSPI */
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#define MPC55XX_IRQ_DSPI_BASE(mod) \
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((mod) == 0 ? 275U : \
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((mod) == 1 ? 131U : \
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((mod) == 2 ? 136U : \
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((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID))))
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/* eMIOS */
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#define MPC55XX_IRQ_EMIOS(ch) \
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((unsigned) (ch) < 16U ? 51U + (ch) : \
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((unsigned) (ch) < 24U ? 186U + (ch) : \
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((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID)))
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/* eQADC */
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#define MPC55XX_IRQ_EQADC_BASE(mod) \
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((mod) == 0 ? 100U : \
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((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID))
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/* eSCI */
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#define MPC55XX_IRQ_ESCI(mod) \
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((mod) == 0 ? 146U : \
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((mod) == 1 ? 149U : \
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((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID)))
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/* FlexCAN */
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#define MPC55XX_IRQ_CAN_BASE(mod) \
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((mod) == 0 ? 152U : \
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((mod) == 1 ? 280U : \
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((mod) == 2 ? 173U : \
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((mod) == 3 ? 308U : \
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((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID)))))
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/* FlexRay */
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#define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
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((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID)
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#endif
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#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
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/* ADC */
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#define MPC55XX_IRQ_ADC_EOC(mod) \
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(MPC55XX_IRQ_ADC_BASE(mod) + 0U)
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#define MPC55XX_IRQ_ADC_ER(mod) \
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(MPC55XX_IRQ_ADC_BASE(mod) + 1U)
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#define MPC55XX_IRQ_ADC_WD(mod) \
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(MPC55XX_IRQ_ADC_BASE(mod) + 2U)
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/* eTimer */
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#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \
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(MPC55XX_IRQ_ETIMER_BASE(mod) + (ch))
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#define MPC55XX_IRQ_ETIMER_WTIF(mod) \
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(MPC55XX_IRQ_ETIMER_BASE(mod) + 8U)
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#define MPC55XX_IRQ_ETIMER_RCF(mod) \
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(MPC55XX_IRQ_ETIMER_BASE(mod) + 10U)
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/* eTPU */
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#define MPC55XX_IRQ_ETPU(mod) \
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(MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
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#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \
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(MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch))
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/* DSPI */
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#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U)
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#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U)
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#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U)
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#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U)
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#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U)
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/* eQADC */
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#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \
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(MPC55XX_IRQ_EQADC_BASE(mod) + 0U)
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#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \
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(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U)
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#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \
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(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U)
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#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \
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(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U)
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#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \
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(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U)
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#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \
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(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U)
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/* FlexCAN */
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#if MPC55XX_CHIP_FAMILY == 564
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#define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
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#define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
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#define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
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#define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
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#define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
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#define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
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#define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
386
#else
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#define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
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#define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
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#define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
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#define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
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#define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
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#define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
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#define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
394
#define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
395
#define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
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#define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
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#define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
398
#define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
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#define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
400
#define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
401
#define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
402
#define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
403
#define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
404
#define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
405
#define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
406
#define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
407
#endif
408
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/* FlexPWM */
410
#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U)
411
#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U)
412
#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U)
413
#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U)
414
#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U)
415
416
/* FlexRay */
417
#if MPC55XX_CHIP_FAMILY == 564
418
#define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
419
#define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
420
#define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
421
#define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
422
#define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
423
#define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
424
#define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
425
#define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
426
#define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U)
427
#define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U)
428
#else
429
#define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
430
#define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
431
#define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
432
#define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
433
#define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
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#define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
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#define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
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#define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
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#endif
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/* LINFlexD */
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#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U)
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#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U)
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#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U)
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/* Checks */
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#define MPC55XX_IRQ_IS_VALID(v) \
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((v) >= MPC55XX_IRQ_MIN && \
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(v) <= MPC55XX_IRQ_MAX)
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#define MPC55XX_IRQ_IS_SOFTWARE(v) \
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((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \
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(v) <= MPC55XX_IRQ_SOFTWARE_MAX)
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/*
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* Interrupt controller
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*/
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/*
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* These are RTEMS API priority values, not INTC priority values. We have:
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* 15 - API-priority == INTC-priority
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*
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* The API-priority value 15 (which is INTC-priority 0) effectively disables
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* the interrupt.
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*/
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#define MPC55XX_INTC_MIN_PRIORITY 14U
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#define MPC55XX_INTC_MAX_PRIORITY 0U
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#define MPC55XX_INTC_DISABLED_PRIORITY 15U
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#define MPC55XX_INTC_INVALID_PRIORITY 16U
467
#define MPC55XX_INTC_DEFAULT_PRIORITY 13U
468
#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \
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(((uint32_t) (p)) <= MPC55XX_INTC_DISABLED_PRIORITY)
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471
rtems_status_code
mpc55xx_interrupt_handler_install
(
472
rtems_vector_number
vector,
473
const
char
*info,
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rtems_option
options,
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unsigned
priority,
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rtems_interrupt_handler
handler,
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void
*arg
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);
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rtems_status_code
mpc55xx_intc_raise_software_irq
(
rtems_vector_number
vector);
481
482
rtems_status_code
mpc55xx_intc_clear_software_irq
(
rtems_vector_number
vector);
483
489
490
#define BSP_INTERRUPT_VECTOR_COUNT (MPC55XX_IRQ_MAX + 1)
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#ifdef BSP_INTERRUPT_DISPATCH_TABLE_SIZE
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#define BSP_INTERRUPT_USE_INDEX_TABLE
494
#endif
495
497
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/* Legacy API */
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#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch)
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#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch)
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502
#ifdef __cplusplus
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};
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#endif
/* __cplusplus */
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#endif
/* LIBBSP_POWERPC_IRQ_H */
mpc55xx_interrupt_handler_install
rtems_status_code mpc55xx_interrupt_handler_install(rtems_vector_number vector, const char *info, rtems_option options, unsigned priority, rtems_interrupt_handler handler, void *arg)
Installs interrupt handler and sets priority.
Definition
irq.c:103
mpc55xx_intc_raise_software_irq
rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector)
Raises the software IRQ with number vector.
Definition
irq.c:77
mpc55xx_intc_clear_software_irq
rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector)
Clears the software IRQ with number vector.
Definition
irq.c:90
irq.h
rtems_vector_number
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition
intr.h:102
rtems_interrupt_handler
void(*) rtems_interrupt_handler(void *)
Interrupt handler routines shall have this type.
Definition
intr.h:1030
rtems_option
uint32_t rtems_option
This type represents a Classic API directive option set.
Definition
options.h:126
rtems_status_code
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition
status.h:85
irq-extension.h
This header file is provided for backward compatiblility.
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