RTEMS
6.3
Toggle main menu visibility
Loading...
Searching...
No Matches
bsps
bfin
include
bf52x.h
Go to the documentation of this file.
1
23
24
#ifndef _BF52X_H_
25
#define _BF52X_H_
26
27
/* register (or register block) addresses */
28
29
#define SIC_BASE_ADDRESS 0xffc00100
30
#define WDOG_BASE_ADDRESS 0xffc00200
31
#define RTC_BASE_ADDRESS 0xffc00300
32
#define UART0_BASE_ADDRESS 0xffc00400
33
#define UART1_BASE_ADDRESS 0xffc02000
34
#define SPI_BASE_ADDRESS 0xffc00500
35
#define TIMER_BASE_ADDRESS 0xffc00600
36
#define TIMER_CHANNELS 3
37
#define TIMER_PITCH 0x10
38
#define TIMER0_BASE_ADDRESS 0xffc00600
39
#define TIMER1_BASE_ADDRESS 0xffc00610
40
#define TIMER2_BASE_ADDRESS 0xffc00620
41
#define TIMER_ENABLE 0xffc00640
42
#define TIMER_DISABLE 0xffc00644
43
#define TIMER_STATUS 0xffc00648
44
#define PORTFIO_BASE_ADDRESS 0xffc00700
45
#define SPORT0_BASE_ADDRESS 0xffc00800
46
#define SPORT1_BASE_ADDRESS 0xffc00900
47
#define EBIU_BASE_ADDRESS 0xffc00a00
48
#define DMA_TC_PER 0xffc00b0c
49
#define DMA_TC_CNT 0xffc00b10
50
#define DMA_BASE_ADDRESS 0xffc00c00
51
#define DMA_CHANNELS 8
52
#define DMA_PITCH 0x40
53
#define DMA0_BASE_ADDRESS 0xffc00c00
54
#define DMA1_BASE_ADDRESS 0xffc00c40
55
#define DMA2_BASE_ADDRESS 0xffc00c80
56
#define DMA3_BASE_ADDRESS 0xffc00cc0
57
#define DMA4_BASE_ADDRESS 0xffc00d00
58
#define DMA5_BASE_ADDRESS 0xffc00d40
59
#define DMA6_BASE_ADDRESS 0xffc00d80
60
#define DMA7_BASE_ADDRESS 0xffc00dc0
61
#define DMA8_BASE_ADDRESS 0xffc00e00
62
#define DMA9_BASE_ADDRESS 0xffc00e40
63
#define DMA10_BASE_ADDRESS 0xffc00e80
64
#define DMA11_BASE_ADDRESS 0xffc00ec0
65
#define MDMA_BASE_ADDRESS 0xffc00e00
66
#define MDMA_CHANNELS 2
67
#define MDMA_D_S 0x40
68
#define MDMA_PITCH 0x80
69
#define MDMA0D_BASE_ADDRESS 0xffc00e00
70
#define MDMA0S_BASE_ADDRESS 0xffc00e40
71
#define MDMA1D_BASE_ADDRESS 0xffc00e80
72
#define MDMA1S_BASE_ADDRESS 0xffc00ec0
73
#define PPI_BASE_ADDRESS 0xffc01000
74
75
76
/* register fields */
77
78
#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800
79
#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11
80
#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700
81
#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8
82
#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0
83
#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4
84
#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f
85
#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0
86
87
#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800
88
#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11
89
#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700
90
#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8
91
#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0
92
#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4
93
#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f
94
#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0
95
96
#define TIMER_ENABLE_TIMEN2 0x0004
97
#define TIMER_ENABLE_TIMEN1 0x0002
98
#define TIMER_ENABLE_TIMEN0 0x0001
99
100
#define TIMER_DISABLE_TIMDIS2 0x0004
101
#define TIMER_DISABLE_TIMDIS1 0x0002
102
#define TIMER_DISABLE_TIMDIS0 0x0001
103
104
#define TIMER_STATUS_TRUN2 0x00004000
105
#define TIMER_STATUS_TRUN1 0x00002000
106
#define TIMER_STATUS_TRUN0 0x00001000
107
#define TIMER_STATUS_TOVF_ERR2 0x00000040
108
#define TIMER_STATUS_TOVF_ERR1 0x00000020
109
#define TIMER_STATUS_TOVF_ERR0 0x00000010
110
#define TIMER_STATUS_TIMIL2 0x00000004
111
#define TIMER_STATUS_TIMIL1 0x00000002
112
#define TIMER_STATUS_TIMIL0 0x00000001
113
114
/* Core Event Controller vectors */
115
116
#define CEC_EMULATION_VECTOR 0
117
#define CEC_RESET_VECTOR 1
118
#define CEC_NMI_VECTOR 2
119
#define CEC_EXCEPTIONS_VECTOR 3
120
#define CEC_HARDWARE_ERROR_VECTOR 5
121
#define CEC_CORE_TIMER_VECTOR 6
122
#define CEC_INTERRUPT_BASE_VECTOR 7
123
#define CEC_INTERRUPT_COUNT 9
124
125
126
/* System Interrupt Controller vectors */
127
128
#define SIC_IAR_COUNT 8
129
130
#endif
/* _BF52X_H_ */
131
Generated by
1.18.0
