RTEMS
6.3
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bsps
arm
atsam
include
libchip
compiler.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _COMPILER_H_
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#define _COMPILER_H_
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#ifdef __rtems__
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#include <bspopts.h>
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#endif
/* __rtems__ */
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/*
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* Peripherals registers definitions
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*/
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#if defined __SAMV71J19__ \
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|| defined __SAMV71J20__ \
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|| defined __SAMV71J21__ \
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|| defined __SAMV71N19__ \
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|| defined __SAMV71N20__ \
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|| defined __SAMV71N21__ \
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|| defined __SAMV71Q19__ \
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|| defined __SAMV71Q20__ \
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|| defined __SAMV71Q21__
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#include "include/samv71/samv71.h"
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#elif defined __SAMS70J19__ \
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|| defined __SAMS70J20__ \
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|| defined __SAMS70J21__ \
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|| defined __SAMS70N19__ \
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|| defined __SAMS70N20__ \
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|| defined __SAMS70N21__ \
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|| defined __SAMS70Q19__ \
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|| defined __SAMS70Q20__ \
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|| defined __SAMS70Q21__
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#include "include/sams70/sams70.h"
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#elif defined __SAME70J19__ \
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|| defined __SAME70J20__ \
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|| defined __SAME70J21__ \
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|| defined __SAME70N19__ \
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|| defined __SAME70N20__ \
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|| defined __SAME70N21__ \
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|| defined __SAME70Q19__ \
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|| defined __SAME70Q20__ \
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|| defined __SAME70Q21__
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#include "include/same70/same70.h"
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#else
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#error "please define correct macro for the chip first!"
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#endif
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//_____ D E C L A R A T I O N S ____________________________________________
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#ifndef __ASSEMBLY__
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#include <stddef.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <stdint.h>
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/* Define WEAK attribute */
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#if defined (__CC_ARM)
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#define WEAK __attribute__ ((weak))
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#elif defined (__ICCARM__)
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#define WEAK __weak
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#elif defined (__GNUC__)
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#define WEAK __attribute__ ((weak))
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#endif
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/* Define Compiler name of tool chains */
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#if defined (__CC_ARM)
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#define COMPILER_NAME "KEIL"
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#elif defined (__ICCARM__)
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#define COMPILER_NAME "IAR"
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#elif defined (__GNUC__)
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#define COMPILER_NAME "GCC"
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#endif
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/* Define NO_INIT attribute */
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#if defined (__CC_ARM)
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#define NO_INIT
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#elif defined (__ICCARM__)
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#define NO_INIT __no_init
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#elif defined (__GNUC__)
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#define NO_INIT
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#endif
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/* Define memory sync for tool chains */
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#if defined (__CC_ARM)
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#define memory_sync() __dsb(15);__isb(15);
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#elif defined (__ICCARM__)
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#define memory_sync() __DSB();__ISB();
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#elif defined (__GNUC__)
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#define memory_sync() __DSB();__ISB();
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#endif
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/* Define memory barrier for tool chains */
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#if defined (__CC_ARM)
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#define memory_barrier() __dmb(15);
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#elif defined (__ICCARM__)
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#define memory_barrier() __DMB();
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#elif defined (__GNUC__)
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#define memory_barrier() __DMB();
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#endif
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#define TPASTE2(a, b) a##b
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#define TPASTE3(a, b, c) a##b##c
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#define ATPASTE2(a, b) TPASTE2(a, b)
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#define ATPASTE3(a, b, c) TPASTE3(a, b, c)
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#define COMPILER_PRAGMA(arg) _Pragma(#arg)
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#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
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#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
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#if defined (__CC_ARM)
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#define COMPILER_SECTION(a) __attribute__((__section__(a)))
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#elif defined (__ICCARM__)
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#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a)
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#elif defined (__GNUC__)
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#define COMPILER_SECTION(a) __attribute__((__section__(a)))
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#endif
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#if defined (__CC_ARM)
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#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
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#elif defined (__ICCARM__)
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#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
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#elif defined (__GNUC__)
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#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
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#endif
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#if defined (__CC_ARM)
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#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
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#elif defined (__ICCARM__)
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#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
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#elif defined (__GNUC__)
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#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
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#endif
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#define Abs(a) (((a) < 0) ? -(a) : (a))
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#define Min(a, b) (((a) < (b)) ? (a) : (b))
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#define Max(a, b) (((a) > (b)) ? (a) : (b))
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// abs() is already defined by stdlib.h
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#define min(a, b) Min(a, b)
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#define max(a, b) Max(a, b)
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#define be32_to_cpu(x) __REV(x)
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#define cpu_to_be32(x) __REV(x)
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#define BE32_TO_CPU(x) __REV(x)
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#define CPU_TO_BE32(x) __REV(x)
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#define UNUSED(v) (void)(v)
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# define irq_initialize_vectors() \
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do { \
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} while (0)
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# define irq_register_handler(int_num, int_prio) \
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NVIC_ClearPendingIRQ((IRQn_Type)int_num); \
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NVIC_SetPriority((IRQn_Type)int_num, int_prio); \
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NVIC_EnableIRQ((IRQn_Type)int_num); \
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# define cpu_irq_enable() \
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do { \
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/*g_interrupt_enabled = true; */
\
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__DMB(); \
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__enable_irq(); \
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} while (0)
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# define cpu_irq_disable() \
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do { \
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__disable_irq(); \
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__DMB(); \
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/*g_interrupt_enabled = false; */
\
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} while (0)
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typedef
uint32_t irqflags_t;
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#if !defined(__DOXYGEN__)
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extern
volatile
bool
g_interrupt_enabled;
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#endif
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#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
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static
volatile
uint32_t cpu_irq_critical_section_counter;
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static
volatile
bool
cpu_irq_prev_interrupt_state;
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static
inline
irqflags_t cpu_irq_save(
void
)
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{
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irqflags_t flags = cpu_irq_is_enabled();
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cpu_irq_disable();
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return
flags;
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}
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static
inline
bool
cpu_irq_is_enabled_flags(irqflags_t flags)
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{
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return
(flags);
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}
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static
inline
void
cpu_irq_restore(irqflags_t flags)
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{
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if
(cpu_irq_is_enabled_flags(flags))
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cpu_irq_enable();
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}
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/*
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void cpu_irq_enter_critical(void);
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void cpu_irq_leave_critical(void);*/
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#define Enable_global_interrupt() cpu_irq_enable()
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#define Disable_global_interrupt() cpu_irq_disable()
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#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
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//_____ M A C R O S ________________________________________________________
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#define DISABLE 0
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#define ENABLE 1
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#define DISABLED 0
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#define ENABLED 1
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#define OFF 0
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#define ON 1
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#define FALSE 0
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#define TRUE 1
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#ifndef __cplusplus
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#if !defined(__bool_true_false_are_defined)
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#define false FALSE
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#define true TRUE
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#endif
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#endif
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#define KO 0
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#define OK 1
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#define PASS 0
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#define FAIL 1
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#define LOW 0
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#define HIGH 1
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#define CLR 0
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#define SET 1
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#define ctz(u) ((u) & (1ul << 0) ? 0 : \
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(u) & (1ul << 1) ? 1 : \
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(u) & (1ul << 2) ? 2 : \
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(u) & (1ul << 3) ? 3 : \
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(u) & (1ul << 4) ? 4 : \
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(u) & (1ul << 5) ? 5 : \
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(u) & (1ul << 6) ? 6 : \
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(u) & (1ul << 7) ? 7 : \
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(u) & (1ul << 8) ? 8 : \
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(u) & (1ul << 9) ? 9 : \
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(u) & (1ul << 10) ? 10 : \
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(u) & (1ul << 11) ? 11 : \
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(u) & (1ul << 12) ? 12 : \
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(u) & (1ul << 13) ? 13 : \
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(u) & (1ul << 14) ? 14 : \
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(u) & (1ul << 15) ? 15 : \
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(u) & (1ul << 16) ? 16 : \
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(u) & (1ul << 17) ? 17 : \
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(u) & (1ul << 18) ? 18 : \
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(u) & (1ul << 19) ? 19 : \
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(u) & (1ul << 20) ? 20 : \
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(u) & (1ul << 21) ? 21 : \
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(u) & (1ul << 22) ? 22 : \
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(u) & (1ul << 23) ? 23 : \
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(u) & (1ul << 24) ? 24 : \
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(u) & (1ul << 25) ? 25 : \
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(u) & (1ul << 26) ? 26 : \
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(u) & (1ul << 27) ? 27 : \
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(u) & (1ul << 28) ? 28 : \
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(u) & (1ul << 29) ? 29 : \
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(u) & (1ul << 30) ? 30 : \
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(u) & (1ul << 31) ? 31 : \
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32)
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#endif
// __ASSEMBLY__
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#endif
// _COMPILER_H_
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