cpu.h File Reference

This header file defines implementation interfaces pertaining to the port of the executive to the ARM architecture. More...

#include <rtems/score/basedefs.h>
#include <rtems/score/arm.h>

Go to the source code of this file.

Data Structures
struct	Context_Control
	Thread register context. More...
struct	ARM_VFP_context
struct	CPU_Exception_frame
	The set of registers that specifies the complete processor state. More...

Macros
#define	ARM_SWITCH_REGISTERS
#define	ARM_SWITCH_TO_ARM
#define	ARM_SWITCH_BACK
#define	ARM_SWITCH_OUTPUT
#define	ARM_SWITCH_ADDITIONAL_OUTPUT
#define	CPU_SIMPLE_VECTORED_INTERRUPTS   FALSE
#define	CPU_ISR_PASSES_FRAME_POINTER   FALSE
#define	CPU_HARDWARE_FP   FALSE
#define	CPU_SOFTWARE_FP   FALSE
#define	CPU_ALL_TASKS_ARE_FP   FALSE
#define	CPU_IDLE_TASK_IS_FP   FALSE
#define	CPU_USE_DEFERRED_FP_SWITCH   FALSE
#define	CPU_ENABLE_ROBUST_THREAD_DISPATCH   TRUE
#define	CPU_STACK_GROWS_UP   FALSE
#define	CPU_CACHE_LINE_BYTES   32
#define	CPU_STRUCTURE_ALIGNMENT   RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
#define	CPU_MODES_INTERRUPT_MASK   0x1
#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK   0
#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS   FALSE
#define	CPU_STACK_MINIMUM_SIZE   (1024 * 4)
#define	CPU_SIZEOF_POINTER   4
#define	CPU_ALIGNMENT   8
#define	CPU_HEAP_ALIGNMENT   CPU_ALIGNMENT
#define	CPU_STACK_ALIGNMENT   8
#define	CPU_INTERRUPT_STACK_ALIGNMENT   CPU_CACHE_LINE_BYTES
#define	CPU_USE_GENERIC_BITFIELD_CODE   TRUE
#define	CPU_USE_LIBC_INIT_FINI_ARRAY   TRUE
#define	CPU_MAXIMUM_PROCESSORS   32
#define	ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET   44
#define	ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE   40
#define	ARM_EXCEPTION_FRAME_SIZE   80
#define	ARM_EXCEPTION_FRAME_REGISTER_R8_OFFSET   32
#define	ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET   52
#define	ARM_EXCEPTION_FRAME_REGISTER_PC_OFFSET   60
#define	ARM_EXCEPTION_FRAME_REGISTER_CPSR_OFFSET   64
#define	ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET   72
#define	ARM_VFP_CONTEXT_SIZE   264
#define	_CPU_ISR_Disable(_isr_cookie)
#define	_CPU_ISR_Enable(_isr_cookie)
#define	_CPU_ISR_Flash(_isr_cookie)
#define	_CPU_Context_Get_SP(_context)
#define	_CPU_Context_Restart_self(_the_context)
#define	_CPU_Context_Initialize_fp(_destination)
Program Status Register
#define	ARM_PSR_N   (1 << 31)
#define	ARM_PSR_Z   (1 << 30)
#define	ARM_PSR_C   (1 << 29)
#define	ARM_PSR_V   (1 << 28)
#define	ARM_PSR_Q   (1 << 27)
#define	ARM_PSR_J   (1 << 24)
#define	ARM_PSR_GE_SHIFT   16
#define	ARM_PSR_GE_MASK   (0xf << ARM_PSR_GE_SHIFT)
#define	ARM_PSR_E   (1 << 9)
#define	ARM_PSR_A   (1 << 8)
#define	ARM_PSR_I   (1 << 7)
#define	ARM_PSR_F   (1 << 6)
#define	ARM_PSR_T   (1 << 5)
#define	ARM_PSR_M_SHIFT   0
#define	ARM_PSR_M_MASK   (0x1f << ARM_PSR_M_SHIFT)
#define	ARM_PSR_M_USR   0x10
#define	ARM_PSR_M_FIQ   0x11
#define	ARM_PSR_M_IRQ   0x12
#define	ARM_PSR_M_SVC   0x13
#define	ARM_PSR_M_ABT   0x17
#define	ARM_PSR_M_HYP   0x1a
#define	ARM_PSR_M_UND   0x1b
#define	ARM_PSR_M_SYS   0x1f

Typedefs
typedef void(*)	CPU_ISR_handler(void)
typedef uint32_t	CPU_Counter_ticks
typedef uintptr_t	CPU_Uint32ptr

Enumerations
enum	Arm_symbolic_exception_name {   ARM_EXCEPTION_RESET = 0 , ARM_EXCEPTION_UNDEF = 1 , ARM_EXCEPTION_SWI = 2 , ARM_EXCEPTION_PREF_ABORT = 3 ,   ARM_EXCEPTION_DATA_ABORT = 4 , ARM_EXCEPTION_RESERVED = 5 , ARM_EXCEPTION_IRQ = 6 , ARM_EXCEPTION_FIQ = 7 ,   MAX_EXCEPTIONS = 8 , ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0x7fffffff }

Functions
void	_CPU_ISR_Set_level (uint32_t level)
uint32_t	_CPU_ISR_Get_level (void)
void	_CPU_Context_Initialize (Context_Control *the_context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
void	_CPU_Initialize (void)
	CPU initialization.
void	_CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
void	_CPU_Context_switch (Context_Control *run, Context_Control *heir)
	CPU switch context.
RTEMS_NO_RETURN void	_CPU_Context_switch_no_return (Context_Control *executing, Context_Control *heir)
RTEMS_NO_RETURN void	_CPU_Context_restore (Context_Control *new_context)
uint32_t	_CPU_Counter_frequency (void)
CPU_Counter_ticks	_CPU_Counter_read (void)
RTEMS_NO_RETURN void *	_CPU_Thread_Idle_body (uintptr_t ignored)
void	_CPU_Exception_frame_print (const CPU_Exception_frame *frame)
RTEMS_NO_RETURN void	_ARM_Exception_default (CPU_Exception_frame *frame)

Detailed Description

This header file defines implementation interfaces pertaining to the port of the executive to the ARM architecture.