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bsps
arm
include
bsp
arm-pl111-regs.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (c) 2013 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
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#define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
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#include <
bsp/utility.h
>
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typedef
struct
{
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uint32_t timing0;
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#define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7)
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#define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
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#define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7)
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#define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15)
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#define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
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#define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
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#define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23)
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#define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
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#define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
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#define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31)
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#define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
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#define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
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uint32_t timing1;
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#define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9)
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#define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
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#define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
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#define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15)
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#define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
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#define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15)
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#define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23)
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#define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
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#define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
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#define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31)
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#define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
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#define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
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uint32_t timing2;
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#define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4)
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#define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
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#define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
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#define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5)
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#define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10)
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#define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
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#define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
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#define PL111_LCD_TIMING2_IVS BSP_BIT32(11)
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#define PL111_LCD_TIMING2_IHS BSP_BIT32(12)
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#define PL111_LCD_TIMING2_IPC BSP_BIT32(13)
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#define PL111_LCD_TIMING2_IOE BSP_BIT32(14)
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#define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25)
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#define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
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#define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
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#define PL111_LCD_TIMING2_BCD BSP_BIT32(26)
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#define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31)
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#define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
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#define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31)
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uint32_t timing3;
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#define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6)
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#define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6)
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#define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
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#define PL111_LCD_TIMING3_LEE BSP_BIT32(16)
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uint32_t upbase;
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uint32_t lpbase;
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uint32_t control;
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#define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0)
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#define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3)
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#define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
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#define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3)
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#define PL111_LCD_CONTROL_LCD_BPP_1 0x00U
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#define PL111_LCD_CONTROL_LCD_BPP_2 0x01U
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#define PL111_LCD_CONTROL_LCD_BPP_4 0x02U
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#define PL111_LCD_CONTROL_LCD_BPP_8 0x03U
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#define PL111_LCD_CONTROL_LCD_BPP_16 0x04U
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#define PL111_LCD_CONTROL_LCD_BPP_24 0x05U
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#define PL111_LCD_CONTROL_LCD_BPP_16_5_6_5 0x06U
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#define PL111_LCD_CONTROL_LCD_BPP_12 0x07U
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#define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4)
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#define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5)
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#define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6)
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#define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7)
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#define PL111_LCD_CONTROL_BGR BSP_BIT32(8)
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#define PL111_LCD_CONTROL_BEBO BSP_BIT32(9)
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#define PL111_LCD_CONTROL_BEPO BSP_BIT32(10)
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#define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11)
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#define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13)
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#define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
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#define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
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#define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16)
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uint32_t imsc;
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uint32_t ris;
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uint32_t mis;
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uint32_t icr;
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#define PL111_LCD_I_FUF BSP_BIT32(1)
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#define PL111_LCD_I_LNBU BSP_BIT32(2)
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#define PL111_LCD_I_VCOMP BSP_BIT32(3)
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#define PL111_LCD_I_MBERROR BSP_BIT32(4)
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uint32_t upcurr;
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uint32_t lpcurr;
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uint32_t reserved_34[115];
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uint16_t pal[256];
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#define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
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#define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4)
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#define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4)
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#define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
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#define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9)
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#define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9)
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#define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
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#define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14)
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#define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14)
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#define PL111_LCD_PAL_I BSP_BIT16(15)
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}
pl111_lcd
;
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typedef
struct
{
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uint8_t image[1024];
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uint32_t ctrl;
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#define PL111_CRSR_CTRL_ON BSP_BIT32(0)
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#define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5)
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#define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5)
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#define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
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uint32_t config;
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#define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0)
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#define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1)
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uint32_t palette0;
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uint32_t palette1;
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#define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7)
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#define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7)
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#define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
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#define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15)
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#define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15)
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#define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
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#define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23)
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#define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23)
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#define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
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uint32_t xy;
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#define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9)
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#define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9)
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#define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
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#define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11)
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#define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11)
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#define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11)
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#define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25)
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#define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25)
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#define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
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#define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27)
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#define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27)
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#define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27)
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uint32_t clip;
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#define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5)
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#define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5)
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#define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
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#define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13)
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#define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13)
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#define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
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uint32_t imsc;
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uint32_t icr;
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uint32_t ris;
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uint32_t mis;
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#define PL111_CRSR_I_CRSR BSP_BIT32(0)
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}
pl111_crsr
;
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typedef
struct
{
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pl111_lcd
lcd;
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uint32_t reserved_400[256];
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pl111_crsr
crsr;
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}
pl111
;
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#endif
/* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */
utility.h
This header file provides utility macros for BSPs.
pl111_crsr
Definition
arm-pl111-regs.h:143
pl111_lcd
Definition
arm-pl111-regs.h:41
pl111
Definition
arm-pl111-regs.h:191
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