RTEMS 6.3
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This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support specific to the GICv3. More...

#include <dev/irq/arm-gic.h>
#include <dev/irq/arm-gic-arch.h>

Go to the source code of this file.

Macros

#define PRIORITY_DEFAULT   127
#define MPIDR_AFFINITY2(val)
#define MPIDR_AFFINITY2_GET(reg)
#define MPIDR_AFFINITY2_SET(reg, val)
#define MPIDR_AFFINITY1(val)
#define MPIDR_AFFINITY1_GET(reg)
#define MPIDR_AFFINITY1_SET(reg, val)
#define MPIDR_AFFINITY0(val)
#define MPIDR_AFFINITY0_GET(reg)
#define MPIDR_AFFINITY0_SET(reg, val)
#define ICC_SGIR_AFFINITY3(val)
#define ICC_SGIR_AFFINITY3_GET(reg)
#define ICC_SGIR_AFFINITY3_SET(reg, val)
#define ICC_SGIR_IRM   BSP_BIT32(40)
#define ICC_SGIR_AFFINITY2(val)
#define ICC_SGIR_AFFINITY2_GET(reg)
#define ICC_SGIR_AFFINITY2_SET(reg, val)
#define ICC_SGIR_INTID(val)
#define ICC_SGIR_INTID_GET(reg)
#define ICC_SGIR_INTID_SET(reg, val)
#define ICC_SGIR_AFFINITY1(val)
#define ICC_SGIR_AFFINITY1_GET(reg)
#define ICC_SGIR_AFFINITY1_SET(reg, val)
#define ICC_SGIR_CPU_TARGET_LIST(val)
#define ICC_SGIR_CPU_TARGET_LIST_GET(reg)
#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val)
#define ICC_IGRPEN0_EL1   "S3_0_C12_C12_6, %0"
#define ICC_IGRPEN1_EL1   "S3_0_C12_C12_7, %0"
#define ICC_IGRPEN1_EL3   "S3_6_C12_C12_7, %0"
#define ICC_IGRPEN0   ICC_IGRPEN0_EL1
#define ICC_IGRPEN1   ICC_IGRPEN1_EL1
#define ICC_PMR   "S3_0_C4_C6_0, %0"
#define ICC_EOIR1   "S3_0_C12_C12_1, %0"
#define ICC_SRE   "S3_0_C12_C12_5, %0"
#define ICC_BPR0   "S3_0_C12_C8_3, %0"
#define ICC_BPR1   "S3_0_C12_C12_3, %0"
#define ICC_CTLR   "S3_0_C12_C12_4, %0"
#define ICC_IAR1   "%0, S3_0_C12_C12_0"
#define MPIDR   "%0, mpidr_el1"
#define MPIDR_AFFINITY3(val)
#define MPIDR_AFFINITY3_GET(reg)
#define MPIDR_AFFINITY3_SET(reg, val)
#define ICC_SGI1   "S3_0_C12_C11_5, %0"
#define WRITE64_SR(SR_NAME, VALUE)
#define WRITE_SR(SR_NAME, VALUE)
#define READ_SR(SR_NAME)

Detailed Description

This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support specific to the GICv3.