RTEMS 6.3
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altera_avalon_hbus_regs.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 *
5 * Copyright (C) 2024 Kevin Kirspel
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _ALTERA_AVALON_HBUS_REGS_H
30#define _ALTERA_AVALON_HBUS_REGS_H
31
32#include <bsp_system.h>
33
34/* CSR */
35#define ALTERA_HBUS_CSR_RACT_MSK (0x1)
36#define ALTERA_HBUS_CSR_RACT_OFST (0)
37#define ALTERA_HBUS_CSR_RDECERR_MSK (0x100)
38#define ALTERA_HBUS_CSR_RDECERR_OFST (8)
39#define ALTERA_HBUS_CSR_RTRSERR_MSK (0x200)
40#define ALTERA_HBUS_CSR_RTRSERR_OFST (9)
41#define ALTERA_HBUS_CSR_RRSTOERR_MSK (0x400)
42#define ALTERA_HBUS_CSR_RRSTOERR_OFST (10)
43#define ALTERA_HBUS_CSR_RDSSTALL_MSK (0x800)
44#define ALTERA_HBUS_CSR_RDSSTALL_OFST (11)
45#define ALTERA_HBUS_CSR_WACT_MSK (0x10000)
46#define ALTERA_HBUS_CSR_WACT_OFST (16)
47#define ALTERA_HBUS_CSR_WDECERR_MSK (0x1000000)
48#define ALTERA_HBUS_CSR_WDECERR_OFST (24)
49#define ALTERA_HBUS_CSR_WTRSERR_MSK (0x2000000)
50#define ALTERA_HBUS_CSR_WTRSERR_OFST (25)
51#define ALTERA_HBUS_CSR_WRSTOERR_MSK (0x4000000)
52#define ALTERA_HBUS_CSR_WRSTOERR_OFST (26)
53
54/* IEN */
55#define ALTERA_HBUS_IEN_RPCINTE_MSK (0x1)
56#define ALTERA_HBUS_IEN_RPCINTE_OFST (0)
57#define ALTERA_HBUS_IEN_INTP_MSK (0x80000000)
58#define ALTERA_HBUS_IEN_INTP_OFST (31)
59
60/* ISR */
61#define ALTERA_HBUS_ISR_RPCINTS_MSK (0x1)
62#define ALTERA_HBUS_ISR_RPCINTS_OFST (0)
63
64/* MBR */
65#define ALTERA_HBUS_MBR_ADDRESS_MSK (0xFF000000)
66#define ALTERA_HBUS_MBR_ADDRESS(x) (x & ALTERA_HBUS_MBR_ADDRESS_MSK)
67
68/* MCR */
69#define ALTERA_HBUS_MCR_WRAPSIZE_MSK (0x3)
70#define ALTERA_HBUS_MCR_WRAPSIZE_OFST (0)
71#define ALTERA_HBUS_MCR_DEVTYPE_MSK (0x10)
72#define ALTERA_HBUS_MCR_DEVTYPE_OFST (4)
73#define ALTERA_HBUS_MCR_CRT_MSK (0x20)
74#define ALTERA_HBUS_MCR_CRT_OFST (5)
75#define ALTERA_HBUS_MCR_ACS_MSK (0x10000)
76#define ALTERA_HBUS_MCR_ACS_OFST (16)
77#define ALTERA_HBUS_MCR_TCMO_MSK (0x20000)
78#define ALTERA_HBUS_MCR_TCMO_OFST (17)
79#define ALTERA_HBUS_MCR_MAXLEN_MSK (0x3FC0000)
80#define ALTERA_HBUS_MCR_MAXLEN_OFST (18)
81#define ALTERA_HBUS_MCR_MAXEN_MSK (0x80000000)
82#define ALTERA_HBUS_MCR_MAXEN_OFST (31)
83
84#define ALTERA_HBUS_MCR_WRAPSIZE_SELECT(x) \
85 ((x) == 32 ? 0x3 : (x) == 64 ? 0x1 : (x) == 16 ? 0x2 : 0x3)
86#define ALTERA_HBUS_MCR_WRAPSIZE(x) \
87 ((ALTERA_HBUS_MCR_WRAPSIZE_SELECT(x) << ALTERA_HBUS_MCR_WRAPSIZE_OFST) & \
88 ALTERA_HBUS_MCR_WRAPSIZE_MSK)
89#define ALTERA_HBUS_MCR_DEVTYPE(x) \
90 (((x) << ALTERA_HBUS_MCR_DEVTYPE_OFST) & ALTERA_HBUS_MCR_DEVTYPE_MSK)
91#define ALTERA_HBUS_MCR_CRT(x) \
92 (((x) << ALTERA_HBUS_MCR_CRT_OFST) & ALTERA_HBUS_MCR_CRT_MSK)
93#define ALTERA_HBUS_MCR_CRT_UPDATE(r, x) \
94 ((r) = ((r) & ALTERA_HBUS_MCR_CRT_MSK) | ALTERA_HBUS_MCR_CRT(x))
95#define ALTERA_HBUS_MCR_ACS(x) \
96 (((x) << ALTERA_HBUS_MCR_ACS_OFST) & ALTERA_HBUS_MCR_ACS_MSK)
97#define ALTERA_HBUS_MCR_TCMO(x) \
98 (((x) << ALTERA_HBUS_MCR_TCMO_OFST) & ALTERA_HBUS_MCR_TCMO_MSK)
99#define ALTERA_HBUS_MCR_MAXLEN(x) \
100 (((((x) / 2) - 1) << ALTERA_HBUS_MCR_MAXLEN_OFST) & \
101 ALTERA_HBUS_MCR_MAXLEN_MSK)
102#define ALTERA_HBUS_MCR_MAXEN(x) \
103 (((x) << ALTERA_HBUS_MCR_MAXEN_OFST) & ALTERA_HBUS_MCR_MAXEN_MSK)
104
105/* MTR */
106#define ALTERA_HBUS_MTR_LTCY_MSK (0xF)
107#define ALTERA_HBUS_MTR_LTCY_OFST (0)
108#define ALTERA_HBUS_MTR_RFU_MSK (0xF0)
109#define ALTERA_HBUS_MTR_RFU_OFST (4)
110#define ALTERA_HBUS_MTR_WCSH_MSK (0xF00)
111#define ALTERA_HBUS_MTR_WCSH_OFST (8)
112#define ALTERA_HBUS_MTR_RCSH_MSK (0xF000)
113#define ALTERA_HBUS_MTR_RCSH_OFST (12)
114#define ALTERA_HBUS_MTR_WCSS_MSK (0xF0000)
115#define ALTERA_HBUS_MTR_WCSS_OFST (16)
116#define ALTERA_HBUS_MTR_RCSS_MSK (0xF00000)
117#define ALTERA_HBUS_MTR_RCSS_OFST (20)
118#define ALTERA_HBUS_MTR_WCSHI_MSK (0xF000000)
119#define ALTERA_HBUS_MTR_WCSHI_OFST (24)
120#define ALTERA_HBUS_MTR_RCSHI_MSK (0xF0000000)
121#define ALTERA_HBUS_MTR_RCSHI_OFST (28)
122
123#define ALTERA_HBUS_MTR_LTCY_SELECT(x) \
124 ((x) == 6 ? 0x1 : (x) == 4 ? 0xf : (x) == 5 ? 0x0 : (x) == 3 ? 0xe : 0x1)
125#define ALTERA_HBUS_MTR_LTCY(x) \
126 ((ALTERA_HBUS_MTR_LTCY_SELECT(x) << ALTERA_HBUS_MTR_LTCY_OFST) & \
127 ALTERA_HBUS_MTR_LTCY_MSK)
128
129/* GPOR */
130#define ALTERA_HBUS_GPOR_GPO_MSK (0x3)
131#define ALTERA_HBUS_GPOR_GPO_OFST (0)
132
133/* WPR */
134#define ALTERA_HBUS_WPR_WP_MSK (0x1)
135#define ALTERA_HBUS_WPR_WP_OFST (0)
136
137/* LBR */
138#define ALTERA_HBUS_LBR_LOOPBACK_MSK (0x1)
139#define ALTERA_HBUS_LBR_LOOPBACK_OFST (0)
140
141/* TAR */
142#define ALTERA_HBUS_TAR_WTA_MSK (0x3)
143#define ALTERA_HBUS_TAR_WTA_OFST (0)
144#define ALTERA_HBUS_TAR_RTA_MSK (0x30)
145#define ALTERA_HBUS_TAR_RTA_OFST (4)
146
147#ifdef __cplusplus
148extern "C" {
149#endif
150
151typedef struct
152{
153 volatile uint32_t csr;
154 volatile uint32_t ien;
155 volatile uint32_t isr;
156 volatile uint32_t icr;
157 volatile uint32_t mbr0;
158 volatile uint32_t mbr1;
159 volatile uint32_t mbr2;
160 volatile uint32_t mbr3;
161 volatile uint32_t mcr0;
162 volatile uint32_t mcr1;
163 volatile uint32_t mcr2;
164 volatile uint32_t mcr3;
165 volatile uint32_t mtr0;
166 volatile uint32_t mtr1;
167 volatile uint32_t mtr2;
168 volatile uint32_t mtr3;
169 volatile uint32_t gpor;
170 volatile uint32_t wpr;
171 volatile uint32_t lbr;
172 volatile uint32_t tar;
173}altera_avalon_hbus_ctrl_regs;
174
175#define HBUS_CTRL_REGS \
176 (( volatile altera_avalon_hbus_ctrl_regs* ) \
177 HYPERBUS_CTRL_ALTERA_AXI4_SLAVE_REGISTER_BASE )
178
179#ifdef __cplusplus
180}
181#endif
182
183#endif
altera_avalon_hbus_ctrl_regs
Definition altera_avalon_hbus_regs.h:152
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