RTEMS 6.3
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8xx_immap.h
1/*
2 * RTEMS BSP support for TQ modules
3 *
4 * This file contains definitions to interact with TQC's
5 * processor modules.
6 *
7 * derived from mbx8xx BSP
8 *
9 * MPC8xx Internal Memory Map
10 */
11
12/*
13 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
14 * Copyright (c) 2007 embedded brains GmbH & Co. KG
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21/*
22 * The I/O on the MPC860 is comprised of blocks of special registers
23 * and the dual port ram for the Communication Processor Module.
24 * Within this space are functional units such as the SIU, memory
25 * controller, system timers, and other control functions. It is
26 * a combination that I found difficult to separate into logical
27 * functional files.....but anyone else is welcome to try. -- Dan
28 */
29#ifndef __IMMAP_8XX__
30#define __IMMAP_8XX__
31
32/* System configuration registers.
33*/
34typedef struct sys_conf {
35 unsigned int sc_siumcr;
36 unsigned int sc_sypcr;
37 unsigned int sc_swt;
38 char res1[2];
39 unsigned short sc_swsr;
40 unsigned int sc_sipend;
41 unsigned int sc_simask;
42 unsigned int sc_siel;
43 unsigned int sc_sivec;
44 unsigned int sc_tesr;
45 char res2[0xc];
46 unsigned int sc_sdcr;
47 char res3[0x4c];
48} sysconf8xx_t;
49
50/* PCMCIA configuration registers.
51*/
52typedef struct pcmcia_conf {
53 unsigned int pcmc_pbr0;
54 unsigned int pcmc_por0;
55 unsigned int pcmc_pbr1;
56 unsigned int pcmc_por1;
57 unsigned int pcmc_pbr2;
58 unsigned int pcmc_por2;
59 unsigned int pcmc_pbr3;
60 unsigned int pcmc_por3;
61 unsigned int pcmc_pbr4;
62 unsigned int pcmc_por4;
63 unsigned int pcmc_pbr5;
64 unsigned int pcmc_por5;
65 unsigned int pcmc_pbr6;
66 unsigned int pcmc_por6;
67 unsigned int pcmc_pbr7;
68 unsigned int pcmc_por7;
69 char res1[0x20];
70 unsigned int pcmc_pgcra;
71 unsigned int pcmc_pgcrb;
72 unsigned int pcmc_pscr;
73 char res2[4];
74 unsigned int pcmc_pipr;
75 char res3[4];
76 unsigned int pcmc_per;
77 char res4[4];
78} pcmconf8xx_t;
79
80/* Memory controller registers.
81*/
82typedef struct mem_ctlr {
83 unsigned int memc_br0;
84 unsigned int memc_or0;
85 unsigned int memc_br1;
86 unsigned int memc_or1;
87 unsigned int memc_br2;
88 unsigned int memc_or2;
89 unsigned int memc_br3;
90 unsigned int memc_or3;
91 unsigned int memc_br4;
92 unsigned int memc_or4;
93 unsigned int memc_br5;
94 unsigned int memc_or5;
95 unsigned int memc_br6;
96 unsigned int memc_or6;
97 unsigned int memc_br7;
98 unsigned int memc_or7;
99 char res1[0x24];
100 unsigned int memc_mar;
101 unsigned int memc_mcr;
102 char res2[4];
103 unsigned int memc_mamr;
104 unsigned int memc_mbmr;
105 unsigned short memc_mstat;
106 unsigned short memc_mptpr;
107 unsigned int memc_mdr;
108 char res3[0x80];
109} memctl8xx_t;
110
111/* System Integration Timers.
112*/
113typedef struct sys_int_timers {
114 unsigned short sit_tbscr;
115 unsigned int sit_tbreff0;
116 unsigned int sit_tbreff1;
117 char res1[0x14];
118 unsigned short sit_rtcsc;
119 unsigned int sit_rtc;
120 unsigned int sit_rtsec;
121 unsigned int sit_rtcal;
122 char res2[0x10];
123 unsigned short sit_piscr;
124 char res3[2];
125 unsigned int sit_pitc;
126 unsigned int sit_pitr;
127 char res4[0x34];
128} sit8xx_t;
129
130#define TBSCR_TBIRQ_MASK ((unsigned short)0xff00)
131#define TBSCR_REFA ((unsigned short)0x0080)
132#define TBSCR_REFB ((unsigned short)0x0040)
133#define TBSCR_REFAE ((unsigned short)0x0008)
134#define TBSCR_REFBE ((unsigned short)0x0004)
135#define TBSCR_TBF ((unsigned short)0x0002)
136#define TBSCR_TBE ((unsigned short)0x0001)
137
138#define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00)
139#define RTCSC_SEC ((unsigned short)0x0080)
140#define RTCSC_ALR ((unsigned short)0x0040)
141#define RTCSC_38K ((unsigned short)0x0010)
142#define RTCSC_SIE ((unsigned short)0x0008)
143#define RTCSC_ALE ((unsigned short)0x0004)
144#define RTCSC_RTF ((unsigned short)0x0002)
145#define RTCSC_RTE ((unsigned short)0x0001)
146
147#define PISCR_PIRQ_MASK ((unsigned short)0xff00)
148#define PISCR_PS ((unsigned short)0x0080)
149#define PISCR_PIE ((unsigned short)0x0004)
150#define PISCR_PTF ((unsigned short)0x0002)
151#define PISCR_PTE ((unsigned short)0x0001)
152
153/* Clocks and Reset.
154*/
155typedef struct clk_and_reset {
156 unsigned int car_sccr;
157 unsigned int car_plprcr;
158 unsigned int car_rsr;
159 char res[0x74]; /* Reserved area */
160} car8xx_t;
161
162/* System Integration Timers keys.
163*/
164typedef struct sitk {
165 unsigned int sitk_tbscrk;
166 unsigned int sitk_tbreff0k;
167 unsigned int sitk_tbreff1k;
168 unsigned int sitk_tbk;
169 char res1[0x10];
170 unsigned int sitk_rtcsck;
171 unsigned int sitk_rtck;
172 unsigned int sitk_rtseck;
173 unsigned int sitk_rtcalk;
174 char res2[0x10];
175 unsigned int sitk_piscrk;
176 unsigned int sitk_pitck;
177 char res3[0x38];
178} sitk8xx_t;
179
180/* Clocks and reset keys.
181*/
182typedef struct cark {
183 unsigned int cark_sccrk;
184 unsigned int cark_plprcrk;
185 unsigned int cark_rsrk;
186 char res[0x474];
187} cark8xx_t;
188
189/* The key to unlock registers maintained by keep-alive power.
190*/
191#define KAPWR_KEY ((unsigned int)0x55ccaa33)
192
193/* LCD interface. MPC821 Only.
194*/
195typedef struct lcd {
196 unsigned short lcd_lcolr[16];
197 char res[0x20];
198 unsigned int lcd_lccr;
199 unsigned int lcd_lchcr;
200 unsigned int lcd_lcvcr;
201 char res2[4];
202 unsigned int lcd_lcfaa;
203 unsigned int lcd_lcfba;
204 char lcd_lcsr;
205 char res3[0x7];
206} lcd8xx_t;
207
208/* I2C
209*/
210typedef struct i2c {
211 unsigned char i2c_i2mod;
212 char res1[3];
213 unsigned char i2c_i2add;
214 char res2[3];
215 unsigned char i2c_i2brg;
216 char res3[3];
217 unsigned char i2c_i2com;
218 char res4[3];
219 unsigned char i2c_i2cer;
220 char res5[3];
221 unsigned char i2c_i2cmr;
222 char res6[0x8b];
223} i2c8xx_t;
224
225/* DMA control/status registers.
226*/
227typedef struct sdma_csr {
228 char res1[4];
229 unsigned int sdma_sdar;
230 unsigned char sdma_sdsr;
231 char res3[3];
232 unsigned char sdma_sdmr;
233 char res4[3];
234 unsigned char sdma_idsr1;
235 char res5[3];
236 unsigned char sdma_idmr1;
237 char res6[3];
238 unsigned char sdma_idsr2;
239 char res7[3];
240 unsigned char sdma_idmr2;
241 char res8[0x13];
242} sdma8xx_t;
243
244/* Communication Processor Module Interrupt Controller.
245*/
246typedef struct cpm_ic {
247 unsigned short cpic_civr;
248 char res[0xe];
249 unsigned int cpic_cicr;
250 unsigned int cpic_cipr;
251 unsigned int cpic_cimr;
252 unsigned int cpic_cisr;
253} cpic8xx_t;
254
255/* Input/Output Port control/status registers.
256*/
257typedef struct io_port {
258 unsigned short iop_padir;
259 unsigned short iop_papar;
260 unsigned short iop_paodr;
261 unsigned short iop_padat;
262 char res1[8];
263 unsigned short iop_pcdir;
264 unsigned short iop_pcpar;
265 unsigned short iop_pcso;
266 unsigned short iop_pcdat;
267 unsigned short iop_pcint;
268 char res2[6];
269 unsigned short iop_pddir;
270 unsigned short iop_pdpar;
271 char res3[2];
272 unsigned short iop_pddat;
273 char res4[8];
274} iop8xx_t;
275
276/* Communication Processor Module Timers
277*/
278typedef struct cpm_timers {
279 unsigned short cpmt_tgcr;
280 char res1[0xe];
281 unsigned short cpmt_tmr1;
282 unsigned short cpmt_tmr2;
283 unsigned short cpmt_trr1;
284 unsigned short cpmt_trr2;
285 unsigned short cpmt_tcr1;
286 unsigned short cpmt_tcr2;
287 unsigned short cpmt_tcn1;
288 unsigned short cpmt_tcn2;
289 unsigned short cpmt_tmr3;
290 unsigned short cpmt_tmr4;
291 unsigned short cpmt_trr3;
292 unsigned short cpmt_trr4;
293 unsigned short cpmt_tcr3;
294 unsigned short cpmt_tcr4;
295 unsigned short cpmt_tcn3;
296 unsigned short cpmt_tcn4;
297 unsigned short cpmt_ter1;
298 unsigned short cpmt_ter2;
299 unsigned short cpmt_ter3;
300 unsigned short cpmt_ter4;
301 char res2[8];
302} cpmtimer8xx_t;
303
304/* Finally, the Communication Processor stuff.....
305*/
306typedef struct scc { /* Serial communication channels */
307 unsigned int scc_gsmrl;
308 unsigned int scc_gsmrh;
309 unsigned short scc_pmsr;
310 char res1[2];
311 unsigned short scc_todr;
312 unsigned short scc_dsr;
313 unsigned short scc_scce;
314 char res2[2];
315 unsigned short scc_sccm;
316 char res3;
317 unsigned char scc_sccs;
318 char res4[8];
319} scc_t;
320
321typedef struct smc { /* Serial management channels */
322 char res1[2];
323 unsigned short smc_smcmr;
324 char res2[2];
325 unsigned char smc_smce;
326 char res3[3];
327 unsigned char smc_smcm;
328 char res4[5];
329} smc_t;
330
331/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
332 * it fits within the address space.
333 */
334typedef struct fec {
335 unsigned int fec_addr_low; /* LS 32 bits of station address */
336 unsigned short fec_addr_high; /* MS 16 bits of address */
337 unsigned short res1;
338 unsigned int fec_hash_table_high;
339 unsigned int fec_hash_table_low;
340 unsigned int fec_r_des_start;
341 unsigned int fec_x_des_start;
342 unsigned int fec_r_buff_size;
343 unsigned int res2[9];
344 unsigned int fec_ecntrl;
345 unsigned int fec_ievent;
346 unsigned int fec_imask;
347 unsigned int fec_ivec;
348 unsigned int fec_r_des_active;
349 unsigned int fec_x_des_active;
350 unsigned int res3[10];
351 unsigned int fec_mii_data;
352 unsigned int fec_mii_speed;
353 unsigned int res4[17];
354 unsigned int fec_r_bound;
355 unsigned int fec_r_fstart;
356 unsigned int res5[6];
357 unsigned int fec_x_fstart;
358 unsigned int res6[17];
359 unsigned int fec_fun_code;
360 unsigned int res7[3];
361 unsigned int fec_r_cntrl;
362 unsigned int fec_r_hash;
363 unsigned int res8[14];
364 unsigned int fec_x_cntrl;
365 unsigned int res9[0x1e];
366} fec_t;
367
368typedef struct comm_proc {
369 /* General control and status registers.
370 */
371 unsigned short cp_cpcr;
372 char res1[2];
373 unsigned short cp_rccr;
374 char res2[6];
375 unsigned short cp_cpmcr1;
376 unsigned short cp_cpmcr2;
377 unsigned short cp_cpmcr3;
378 unsigned short cp_cpmcr4;
379 char res3[2];
380 unsigned short cp_rter;
381 char res4[2];
382 unsigned short cp_rtmr;
383 char res5[0x14];
384
385 /* Baud rate generators.
386 */
387 unsigned int cp_brgc1;
388 unsigned int cp_brgc2;
389 unsigned int cp_brgc3;
390 unsigned int cp_brgc4;
391
392 /* Serial Communication Channels.
393 */
394 scc_t cp_scc[4];
395
396 /* Serial Management Channels.
397 */
398 smc_t cp_smc[2];
399
400 /* Serial Peripheral Interface.
401 */
402 unsigned short cp_spmode;
403 char res6[4];
404 unsigned char cp_spie;
405 char res7[3];
406 unsigned char cp_spim;
407 char res8[2];
408 unsigned char cp_spcom;
409 char res9[2];
410
411 /* Parallel Interface Port.
412 */
413 char res10[2];
414 unsigned short cp_pipc;
415 char res11[2];
416 unsigned short cp_ptpr;
417 unsigned int cp_pbdir;
418 unsigned int cp_pbpar;
419 char res12[2];
420 unsigned short cp_pbodr;
421 unsigned int cp_pbdat;
422 char res13[0x18];
423
424 /* Serial Interface and Time Slot Assignment.
425 */
426 unsigned int cp_simode;
427 unsigned char cp_sigmr;
428 char res14;
429 unsigned char cp_sistr;
430 unsigned char cp_sicmr;
431 char res15[4];
432 unsigned int cp_sicr;
433 unsigned int cp_sirp;
434 char res16[0x10c];
435 unsigned char cp_siram[0x200];
436
437 /* The fast ethernet controller is not really part of the CPM,
438 * but it resides in the address space.
439 */
440 fec_t cp_fec;
441 char res18[0x1000];
442
443 /* Dual Ported RAM follows.
444 * There are many different formats for this memory area
445 * depending upon the devices used and options chosen.
446 */
447 unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */
448 unsigned char res19[0xc00];
449 unsigned char cp_dparam[0x400]; /* Parameter RAM */
450} cpm8xx_t;
451
452/* Internal memory map.
453*/
454typedef struct immap {
455 sysconf8xx_t im_siu_conf; /* SIU Configuration */
456 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
457 memctl8xx_t im_memctl; /* Memory Controller */
458 sit8xx_t im_sit; /* System integration timers */
459 car8xx_t im_clkrst; /* Clocks and reset */
460 sitk8xx_t im_sitk; /* Sys int timer keys */
461 cark8xx_t im_clkrstk; /* Clocks and reset keys */
462 lcd8xx_t im_lcd; /* LCD (821 only) */
463 i2c8xx_t im_i2c; /* I2C control/status */
464 sdma8xx_t im_sdma; /* SDMA control/status */
465 cpic8xx_t im_cpic; /* CPM Interrupt Controller */
466 iop8xx_t im_ioport; /* IO Port control/status */
467 cpmtimer8xx_t im_cpmtimer; /* CPM timers */
468 cpm8xx_t im_cpm; /* Communication processor */
469} immap_t;
470
471#endif /* __IMMAP_8XX__ */
cark
Definition 8xx_immap.h:182
clk_and_reset
Definition 8xx_immap.h:155
comm_proc
Definition 8xx_immap.h:368
cpm_ic
Definition 8xx_immap.h:246
cpm_timers
Definition 8xx_immap.h:278
fec
Definition 8xx_immap.h:334
i2c
Definition 8xx_immap.h:210
immap
Definition 8xx_immap.h:454
io_port
Definition 8xx_immap.h:257
lcd
Definition 8xx_immap.h:195
mem_ctlr
Definition 8xx_immap.h:82
pcmcia_conf
Definition 8xx_immap.h:52
scc
Definition 8xx_immap.h:306
sdma_csr
Definition 8xx_immap.h:227
sitk
Definition 8xx_immap.h:164
smc
Definition 8xx_immap.h:321
sys_conf
Definition 8xx_immap.h:34
sys_int_timers
Definition 8xx_immap.h:113
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