zynq-devcfg-regs.h File Reference

Device configuration interface register definitions. More...

#include <stdint.h>
#include <bsp/utility.h>

Go to the source code of this file.

Data Structures
struct	zynq_devcfg_regs

Macros
#define	ZYNQ_DEVCFG_BASE_ADDR   0xF8007000UL
#define	ZYNQ_DEVCFG_BITSTREAM_ADDR   0xFFFFFFFFUL
#define	ZYNQ_DEVCFG_INTERRUPT_VECTOR   40
#define	ZYNQ_DEVCFG_CTRL_FORCE_RST(val)
#define	ZYNQ_DEVCFG_CTRL_FORCE_RST_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_PROG_B_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_PROG_B(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K(val)
#define	ZYNQ_DEVCFG_CTRL_PCAP_PR(val)
#define	ZYNQ_DEVCFG_CTRL_PCAP_PR_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCAP_PR_ICAP   ( 0 )
#define	ZYNQ_DEVCFG_CTRL_PCAP_PR_PCAP   ( 1 )
#define	ZYNQ_DEVCFG_CTRL_PCAP_MODE(val)
#define	ZYNQ_DEVCFG_CTRL_PCAP_MODE_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN(val)
#define	ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN(val)
#define	ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS(val)
#define	ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_BBRAM   ( 0 )
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_EFUSE   ( 1 )
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_EN(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_ENABLE   ( 0x3 )
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_DISABLE   ( 0x0 )
#define	ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_LOCKDOWN   ( 0x1 )
#define	ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_SEC_EN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_NIDEN(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_NIDEN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_DBGEN(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_DBGEN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN(val)
#define	ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_GET(reg)
#define	ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_ENABLE   ( 0x3 )
#define	ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_BYPASS   ( 0x0 )
#define	ZYNQ_DEVCFG_CTRL_RESERVED_BITS   ( 0x6000 )
#define	ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT   BSP_BIT32( 27 )
#define	ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_AXI_WERR_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_AXI_RTO_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_AXI_RERR_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_RX_FIFO_OV_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_DMA_CMD_ERR_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_DMA_Q_OV_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_DMA_DONE_INT   BSP_BIT32( 13 )
#define	ZYNQ_DEVCFG_INT_DMA_DONE_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_D_P_DONE_INT   BSP_BIT32( 12 )
#define	ZYNQ_DEVCFG_INT_D_P_DONE_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_P2D_LEN_ERR_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_PCFG_HMAC_ERR_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_PCFG_SEU_ERR_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_PCFG_POR_B_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_PCFG_CFG_RST_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_PCFG_DONE_INT   BSP_BIT32( 2 )
#define	ZYNQ_DEVCFG_INT_PCFG_DONE_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT   BSP_BIT32( 1 )
#define	ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT   BSP_BIT32( 0 )
#define	ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT_GET(reg)
#define	ZYNQ_DEVCFG_INT_ALL   ( 0xf8f7f87f )
#define	ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F(val)
#define	ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F_GET(reg)
#define	ZYNQ_DEVCFG_STATUS_PCFG_INIT_GET(reg)
#define	ZYNQ_DEVCFG_DMA_SRC_ADDR_DMA_DONE_INT_WAIT_PCAP   ( 0x1 )
#define	ZYNQ_DEVCFG_DMA_DST_ADDR_DMA_DONE_INT_WAIT_PCAP   ( 0x1 )
#define	ZYNQ_DEVCFG_DMA_SRC_LEN_LEN(val)
#define	ZYNQ_DEVCFG_DMA_DEST_LEN_LEN(val)
#define	ZYNQ_DEVCFG_MCTRL_PS_VERSION_GET(reg)
#define	ZYNQ_DEVCFG_MCTRL_PS_VERSION_1_0   0x0
#define	ZYNQ_DEVCFG_MCTRL_PS_VERSION_2_0   0x1
#define	ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_0   0x2
#define	ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_1   0x3
#define	ZYNQ_DEVCFG_MCTRL_PCFG_POR_B_GET(reg)
#define	ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK_GET(reg)
#define	ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK(val)
#define	ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS   ( 0x800000 )
#define	ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS   ( 0x3 )
#define	ZYNQ_DEVCFG_MCTRL_SET(reg, val)

Detailed Description

Device configuration interface register definitions.

Macro Definition Documentation

ZYNQ_DEVCFG_CTRL_FORCE_RST

#define ZYNQ_DEVCFG_CTRL_FORCE_RST

(

val

)

Value:

BSP_FLD32( val, 31, 31 )

ZYNQ_DEVCFG_CTRL_FORCE_RST_GET

#define ZYNQ_DEVCFG_CTRL_FORCE_RST_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 31, 31 )

ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS

#define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS

(

val

)

Value:

BSP_FLD32( val, 23, 23 )

ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS_GET

#define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 23, 23 )

ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN

#define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN

(

val

)

Value:

BSP_FLD32( val, 24, 24 )

ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN_GET

#define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 24, 24 )

ZYNQ_DEVCFG_CTRL_PCAP_MODE

#define ZYNQ_DEVCFG_CTRL_PCAP_MODE

(

val

)

Value:

BSP_FLD32( val, 26, 26 )

ZYNQ_DEVCFG_CTRL_PCAP_MODE_GET

#define ZYNQ_DEVCFG_CTRL_PCAP_MODE_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 26, 26 )

ZYNQ_DEVCFG_CTRL_PCAP_PR

#define ZYNQ_DEVCFG_CTRL_PCAP_PR

(

val

)

Value:

BSP_FLD32( val, 27, 27 )

ZYNQ_DEVCFG_CTRL_PCAP_PR_GET

#define ZYNQ_DEVCFG_CTRL_PCAP_PR_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 27, 27 )

ZYNQ_DEVCFG_CTRL_PCFG_AES_EN

#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN

(

val

)

Value:

BSP_FLD32( val, 9, 11 )

ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 9, 11 )

ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE

#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE

(

val

)

Value:

BSP_FLD32( val, 12, 12 )

ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 12, 12 )

ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN

#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN

(

val

)

Value:

BSP_FLD32( val, 0, 2 )

ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 0, 2 )

ZYNQ_DEVCFG_CTRL_PCFG_DBGEN

#define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN

(

val

)

Value:

BSP_FLD32( val, 3, 3 )

ZYNQ_DEVCFG_CTRL_PCFG_DBGEN_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 3, 3 )

ZYNQ_DEVCFG_CTRL_PCFG_NIDEN

#define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN

(

val

)

Value:

BSP_FLD32( val, 4, 4 )

ZYNQ_DEVCFG_CTRL_PCFG_NIDEN_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 4, 4 )

ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K

#define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K

(

val

)

Value:

BSP_FLD32( val, 29, 29 )

ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 29, 29 )

ZYNQ_DEVCFG_CTRL_PCFG_PROG_B

#define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B

(

val

)

Value:

BSP_FLD32( val, 30, 30 )

ZYNQ_DEVCFG_CTRL_PCFG_PROG_B_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 30, 30 )

ZYNQ_DEVCFG_CTRL_PCFG_SEC_EN_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_SEC_EN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 7, 7 )

ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN

#define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN

(

val

)

Value:

BSP_FLD32( val, 8, 8 )

ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 8, 8 )

ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN

#define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN

(

val

)

Value:

BSP_FLD32( val, 5, 5 )

ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 5, 5 )

ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN

#define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN

(

val

)

Value:

BSP_FLD32( val, 6, 6 )

ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN_GET

#define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 6, 6 )

ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN

#define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN

(

val

)

Value:

BSP_FLD32( val, 25, 25 )

ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN_GET

#define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 25, 25 )

ZYNQ_DEVCFG_DMA_DEST_LEN_LEN

#define ZYNQ_DEVCFG_DMA_DEST_LEN_LEN

(

val

)

Value:

BSP_FLD32( val, 0, 26 )

ZYNQ_DEVCFG_DMA_SRC_LEN_LEN

#define ZYNQ_DEVCFG_DMA_SRC_LEN_LEN

(

val

)

Value:

BSP_FLD32( val, 0, 26 )

ZYNQ_DEVCFG_INT_AXI_RERR_INT_GET

#define ZYNQ_DEVCFG_INT_AXI_RERR_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 20, 20 )

ZYNQ_DEVCFG_INT_AXI_RTO_INT_GET

#define ZYNQ_DEVCFG_INT_AXI_RTO_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 21, 21 )

ZYNQ_DEVCFG_INT_AXI_WERR_INT_GET

#define ZYNQ_DEVCFG_INT_AXI_WERR_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 22, 22 )

ZYNQ_DEVCFG_INT_D_P_DONE_INT_GET

#define ZYNQ_DEVCFG_INT_D_P_DONE_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 12, 12 )

ZYNQ_DEVCFG_INT_DMA_CMD_ERR_INT_GET

#define ZYNQ_DEVCFG_INT_DMA_CMD_ERR_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 15, 15 )

ZYNQ_DEVCFG_INT_DMA_DONE_INT_GET

#define ZYNQ_DEVCFG_INT_DMA_DONE_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 13, 13 )

ZYNQ_DEVCFG_INT_DMA_Q_OV_INT_GET

#define ZYNQ_DEVCFG_INT_DMA_Q_OV_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 14, 14 )

ZYNQ_DEVCFG_INT_P2D_LEN_ERR_INT_GET

#define ZYNQ_DEVCFG_INT_P2D_LEN_ERR_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 11, 11 )

ZYNQ_DEVCFG_INT_PCFG_CFG_RST_INT_GET

#define ZYNQ_DEVCFG_INT_PCFG_CFG_RST_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 3, 3 )

ZYNQ_DEVCFG_INT_PCFG_DONE_INT_GET

#define ZYNQ_DEVCFG_INT_PCFG_DONE_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 2, 2 )

ZYNQ_DEVCFG_INT_PCFG_HMAC_ERR_INT_GET

#define ZYNQ_DEVCFG_INT_PCFG_HMAC_ERR_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 6, 6 )

ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT_GET

#define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 0, 0 )

ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT_GET

#define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 1, 1 )

ZYNQ_DEVCFG_INT_PCFG_POR_B_INT_GET

#define ZYNQ_DEVCFG_INT_PCFG_POR_B_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 4, 4 )

ZYNQ_DEVCFG_INT_PCFG_SEU_ERR_INT_GET

#define ZYNQ_DEVCFG_INT_PCFG_SEU_ERR_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 5, 5 )

ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT_GET

#define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 27, 27 )

ZYNQ_DEVCFG_INT_RX_FIFO_OV_INT_GET

#define ZYNQ_DEVCFG_INT_RX_FIFO_OV_INT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 18, 18 )

ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK

#define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK

(

val

)

Value:

BSP_FLD32( val, 4, 4 )

ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK_GET

#define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 4, 4 )

ZYNQ_DEVCFG_MCTRL_PCFG_POR_B_GET

#define ZYNQ_DEVCFG_MCTRL_PCFG_POR_B_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 8, 8 )

ZYNQ_DEVCFG_MCTRL_PS_VERSION_GET

#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 28, 31 )

ZYNQ_DEVCFG_MCTRL_SET

#define ZYNQ_DEVCFG_MCTRL_SET	(		reg,
			val )

Value:

( ( ( reg ) & \
~ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ) | \
ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS | ( val ) )

ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F

#define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F

(

val

)

Value:

BSP_FLD32( val, 31, 31 )

ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F_GET

#define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 31, 31 )

ZYNQ_DEVCFG_STATUS_PCFG_INIT_GET

#define ZYNQ_DEVCFG_STATUS_PCFG_INIT_GET

(

reg

)

Value:

BSP_FLD32GET( reg, 4, 4 )