RTEMS
6.3
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bsps
powerpc
virtex
include
xparameters_dflt.h
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/*******************************************************************
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
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* DO NOT EDIT.
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*
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* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
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*
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* Description: Driver parameters
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*
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*******************************************************************/
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#define STDIN_BASEADDRESS 0x40600000
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#define STDOUT_BASEADDRESS 0x40600000
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/******************************************************************/
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/* Definitions for driver PLBARB */
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#define XPAR_XPLBARB_NUM_INSTANCES 1
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/* Definitions for peripheral PLB */
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#define XPAR_PLB_BASEADDR 0x00000000
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#define XPAR_PLB_HIGHADDR 0x00000000
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#define XPAR_PLB_DEVICE_ID 0
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#define XPAR_PLB_PLB_NUM_MASTERS 3
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/******************************************************************/
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/* Definitions for driver OPBARB */
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#define XPAR_XOPBARB_NUM_INSTANCES 1
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/* Definitions for peripheral OPB */
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#define XPAR_OPB_BASEADDR 0xFFFFFFFF
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#define XPAR_OPB_HIGHADDR 0x00000000
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#define XPAR_OPB_DEVICE_ID 0
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#define XPAR_OPB_NUM_MASTERS 1
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/******************************************************************/
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/* Definitions for driver UARTLITE */
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#define XPAR_XUARTLITE_NUM_INSTANCES 1
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/* Definitions for peripheral CONSOLE */
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#define XPAR_CONSOLE_BASEADDR 0x40600000
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#define XPAR_CONSOLE_HIGHADDR 0x4060FFFF
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#define XPAR_CONSOLE_DEVICE_ID 0
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#define XPAR_CONSOLE_BAUDRATE 115200
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#define XPAR_CONSOLE_USE_PARITY 0
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#define XPAR_CONSOLE_ODD_PARITY 0
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#define XPAR_CONSOLE_DATA_BITS 8
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/******************************************************************/
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/* Definitions for driver GPIO */
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#define XPAR_XGPIO_NUM_INSTANCES 3
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/* Definitions for peripheral LEDS */
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#define XPAR_LEDS_BASEADDR 0x40000000
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#define XPAR_LEDS_HIGHADDR 0x4000FFFF
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#define XPAR_LEDS_DEVICE_ID 0
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#define XPAR_LEDS_INTERRUPT_PRESENT 0
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#define XPAR_LEDS_IS_DUAL 0
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/* Definitions for peripheral PBLEDS */
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#define XPAR_PBLEDS_BASEADDR 0x40020000
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#define XPAR_PBLEDS_HIGHADDR 0x4002FFFF
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#define XPAR_PBLEDS_DEVICE_ID 1
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#define XPAR_PBLEDS_INTERRUPT_PRESENT 0
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#define XPAR_PBLEDS_IS_DUAL 0
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/* Definitions for peripheral PUSHBUTTONS */
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#define XPAR_PUSHBUTTONS_BASEADDR 0x40040000
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#define XPAR_PUSHBUTTONS_HIGHADDR 0x4004FFFF
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#define XPAR_PUSHBUTTONS_DEVICE_ID 2
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#define XPAR_PUSHBUTTONS_INTERRUPT_PRESENT 1
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#define XPAR_PUSHBUTTONS_IS_DUAL 0
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/******************************************************************/
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/* Definitions for driver TMRCTR */
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#define XPAR_XTMRCTR_NUM_INSTANCES 1
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/* Definitions for peripheral OPBTIMER */
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#define XPAR_OPBTIMER_BASEADDR 0x41C00000
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#define XPAR_OPBTIMER_HIGHADDR 0x41C0FFFF
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#define XPAR_OPBTIMER_DEVICE_ID 0
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/******************************************************************/
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#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
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#define XPAR_XINTC_HAS_IPR 1
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#define XPAR_XINTC_USE_DCR 0
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/* Definitions for driver INTC */
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#define XPAR_XINTC_NUM_INSTANCES 1
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/* Definitions for peripheral INTC */
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#define XPAR_INTC_BASEADDR 0x41200000
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#define XPAR_INTC_HIGHADDR 0x4120FFFF
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#define XPAR_INTC_DEVICE_ID 0
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#define XPAR_INTC_KIND_OF_INTR 0x00000000
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/******************************************************************/
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#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
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#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
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#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_INTC_DEVICE_ID
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#define XPAR_OPBTIMER_INTERRUPT_MASK 0X000001
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#define XPAR_INTC_OPBTIMER_INTERRUPT_INTR 0
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#define XPAR_ETHERNET_IP2INTC_IRPT_MASK 0X000002
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#define XPAR_INTC_ETHERNET_IP2INTC_IRPT_INTR 1
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#define XPAR_PUSHBUTTONS_IP2INTC_IRPT_MASK 0X000004
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#define XPAR_INTC_PUSHBUTTONS_IP2INTC_IRPT_INTR 2
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/******************************************************************/
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/* Definitions for driver DDR */
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#define XPAR_XDDR_NUM_INSTANCES 1
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/* Definitions for peripheral DDR_SDRAM_64MX32 */
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#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF
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#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000
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#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0
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#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0
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/******************************************************************/
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/* Definitions for peripheral DDR_SDRAM_64MX32 */
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#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000
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#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF
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/******************************************************************/
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/* Definitions for peripheral HARD_TEMAC_0 */
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#define XPAR_HARD_TEMAC_0_PHY_TYPE 1
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/******************************************************************/
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/* Definitions for driver TEMAC */
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#define XPAR_XTEMAC_NUM_INSTANCES 1
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/* Definitions for peripheral ETHERNET */
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#define XPAR_ETHERNET_DEVICE_ID 0
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#define XPAR_ETHERNET_BASEADDR 0x81200000
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#define XPAR_ETHERNET_HIGHADDR 0x8120FFFF
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#define XPAR_ETHERNET_RXFIFO_DEPTH 32768
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#define XPAR_ETHERNET_TXFIFO_DEPTH 32768
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#define XPAR_ETHERNET_MAC_FIFO_DEPTH 64
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#define XPAR_ETHERNET_DMA_TYPE 1
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#define XPAR_ETHERNET_TX_DRE_TYPE 0
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#define XPAR_ETHERNET_RX_DRE_TYPE 0
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#define XPAR_ETHERNET_INCLUDE_TX_CSUM 0
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#define XPAR_ETHERNET_INCLUDE_RX_CSUM 0
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/******************************************************************/
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/* Definitions for peripheral FLASH */
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#define XPAR_FLASH_NUM_BANKS_MEM 1
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/******************************************************************/
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/* Definitions for peripheral FLASH */
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#define XPAR_FLASH_MEM0_BASEADDR 0x06000000
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#define XPAR_FLASH_MEM0_HIGHADDR 0x067FFFFF
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/******************************************************************/
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/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
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#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000
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#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff
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/******************************************************************/
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#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
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/******************************************************************/
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