xnandpsu_onfi.h

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/******************************************************************************
* Copyright (C) 2015 - 2022 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
 
/*****************************************************************************/
#ifndef XNANDPSU_ONFI_H     /* prevent circular inclusions */
#define XNANDPSU_ONFI_H     /* by using protection macros */
 
#ifdef __cplusplus
extern "C" {
#endif
 
/***************************** Include Files *********************************/
#ifndef __rtems__
#include "xil_types.h"
#else
#include <bsp/xil-compat.h>
#endif
 
/************************** Constant Definitions *****************************/
/* Standard ONFI 3.1 Commands */
/* ONFI 3.1 Mandatory Commands */
#define ONFI_CMD_RD1            0x00U   
#define ONFI_CMD_RD2            0x30U   
#define ONFI_CMD_CHNG_RD_COL1       0x05U   
#define ONFI_CMD_CHNG_RD_COL2       0xE0U   
#define ONFI_CMD_BLK_ERASE1     0x60U   
#define ONFI_CMD_BLK_ERASE2     0xD0U   
#define ONFI_CMD_RD_STS         0x70U   
#define ONFI_CMD_PG_PROG1       0x80U   
#define ONFI_CMD_PG_PROG2       0x10U   
#define ONFI_CMD_CHNG_WR_COL        0x85U   
#define ONFI_CMD_RD_ID          0x90U   
#define ONFI_CMD_RD_PRM_PG      0xECU   
#define ONFI_CMD_RST            0xFFU   
/* ONFI 3.1 Optional Commands */
#define ONFI_CMD_MUL_RD1        0x00U   
#define ONFI_CMD_MUL_RD2        0x32U   
#define ONFI_CMD_CPBK_RD1       0x00U   
#define ONFI_CMD_CPBK_RD2       0x35U   
#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U   
#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U   
#define ONFI_CMD_RD_CACHE_RND1      0x00U   
#define ONFI_CMD_RD_CACHE_RND2      0x31U   
#define ONFI_CMD_RD_CACHE_SEQ       0x31U   
#define ONFI_CMD_RD_CACHE_END       0x3FU   
#define ONFI_CMD_MUL_BLK_ERASE1     0x60U   
#define ONFI_CMD_MUL_BLK_ERASE2     0xD1U   
#define ONFI_CMD_RD_STS_ENHCD       0x78U   
#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U   
#define ONFI_CMD_MUL_PG_PROG1       0x80U   
#define ONFI_CMD_MUL_PG_PROG2       0x11U   
#define ONFI_CMD_PG_CACHE_PROG1     0x80U   
#define ONFI_CMD_PG_CACHE_PROG2     0x15U   
#define ONFI_CMD_CPBK_PROG1     0x85U   
#define ONFI_CMD_CPBK_PROG2     0x10U   
#define ONFI_CMD_MUL_CPBK_PROG1     0x85U   
#define ONFI_CMD_MUL_CPBK_PROG2     0x10U   
#define ONFI_CMD_SMALL_DATA_MV1     0x85U   
#define ONFI_CMD_SMALL_DATA_MV2     0x10U   
#define ONFI_CMD_CHNG_ROW_ADDR      0x85U   
#define ONFI_CMD_VOL_SEL        0xE1U   
#define ONFI_CMD_ODT_CONF       0xE2U   
#define ONFI_CMD_RD_UNIQID      0xEDU   
#define ONFI_CMD_GET_FEATURES       0xEEU   
#define ONFI_CMD_SET_FEATURES       0xEFU   
#define ONFI_CMD_LUN_GET_FEATURES   0xD4U   
#define ONFI_CMD_LUN_SET_FEATURES   0xD5U   
#define ONFI_CMD_RST_LUN        0xFAU   
#define ONFI_CMD_SYN_RST        0xFCU   
 
/* ONFI Status Register bit offsets */
#define ONFI_STS_FAIL           0x01U   
#define ONFI_STS_FAILC          0x02U   
#define ONFI_STS_CSP            0x08U   
#define ONFI_STS_VSP            0x10U   
#define ONFI_STS_ARDY           0x20U   
#define ONFI_STS_RDY            0x40U   
#define ONFI_STS_WP         0x80U   
 
/* ONFI constants */
#define ONFI_CRC_LEN            254U    
#define ONFI_PRM_PG_LEN         256U    
#define ONFI_MND_PRM_PGS        3U  
#define ONFI_SIG_LEN            4U  
#define ONFI_CMD_INVALID        0x00U   
 
#define ONFI_READ_ID_LEN        4U  
#define ONFI_READ_ID_ADDR       0x20U   
#define ONFI_READ_ID_ADDR_CYCLES    1U  
 
#define ONFI_PRM_PG_ADDR_CYCLES     1U  

enum OnfiCommandList {
    READ=0,             
    MULTIPLANE_READ,        
    COPYBACK_READ,          
    CHANGE_READ_COLUMN,     
    CHANGE_READ_COLUMN_ENHANCED,    
    READ_CACHE_RANDOM,      
    READ_CACHE_SEQUENTIAL,      
    READ_CACHE_END,         
    BLOCK_ERASE,            
    MULTIPLANE_BLOCK_ERASE,     
    READ_STATUS,            
    READ_STATUS_ENHANCED,       
    PAGE_PROGRAM,           
    MULTIPLANE_PAGE_PROGRAM,    
    PAGE_CACHE_PROGRAM,     
    COPYBACK_PROGRAM,       
    MULTIPLANE_COPYBACK_PROGRAM,    
    SMALL_DATA_MOVE,        
    CHANGE_WRITE_COLUMN,        
    CHANGE_ROW_ADDR,        
    READ_ID,            
    VOLUME_SELECT,          
    ODT_CONFIGURE,          
    READ_PARAM_PAGE,        
    READ_UNIQUE_ID,         
    GET_FEATURES,           
    SET_FEATURES,           
    LUN_GET_FEATURES,       
    LUN_SET_FEATURES,       
    RESET_LUN,          
    SYN_RESET,          
    RESET,              
    MAX_CMDS            
};
 
/**************************** Type Definitions *******************************/
/* Parameter page structure of ONFI 3.1 specification. */
#ifdef __ICCARM__
#pragma pack(push, 1)
#endif
typedef struct {
    /* Revision information and features block */
    u8 Signature[4];        
    u16 Revision;           
    u16 Features;           
    u16 OptionalCmds;       
    u8 JedecJtgPrmAdvCmd;       
    u8 Reserved0;           
    u16 ExtParamPageLen;        
    u8 NumOfParamPages;     
    u8 Reserved1[17];       
    /* Manufacturer information block */
    u8 DeviceManufacturer[12];  
    u8 DeviceModel[20];     
    u8 JedecManufacturerId;     
    u8 DateCode[2];         
    u8 Reserved2[13];       
    /* Memory organization block */
    u32 BytesPerPage;       
    u16 SpareBytesPerPage;      
    u32 BytesPerPartialPage;    
    u16 SpareBytesPerPartialPage;   
    u32 PagesPerBlock;      
    u32 BlocksPerLun;       
    u8 NumLuns;         
    u8 AddrCycles;          
    u8 BitsPerCell;         
    u16 MaxBadBlocksPerLun;     
    u16 BlockEndurance;     
    u8 GuaranteedValidBlock;    
    u16 BlockEnduranceGVB;      
    u8 ProgramsPerPage;     
    u8 PartialProgAttr;     
    u8 EccBits;         
    u8 PlaneAddrBits;       
    u8 PlaneOperationAttr;      
    u8 EzNandSupport;       
    u8 Reserved3[12];       
    /* Electrical parameters block */
    u8 IOPinCapacitance;        
    u16 SDRTimingMode;      
    u16 SDRPagecacheTimingMode; 
    u16 TProg;          
    u16 TBers;          
    u16 TR;             
    u16 TCcs;           
    u8 NVDDRTimingMode;     
    u8 NVDDR2TimingMode;        
    u8 SynFeatures;         
    u16 ClkInputPinCap;     
    u16 IOPinCap;           
    u16 InputPinCap;        
    u8 InputPinCapMax;      
    u8 DrvStrength;         
    u16 TMr;            
    u16 TAdl;           
    u16 TEr;            
    u8 NVDDR2Features;      
    u8 NVDDR2WarmupCycles;      
    u8 Reserved4[4];        
    /* Vendor block */
    u16 VendorRevisionNum;      
    u8 VendorSpecific[88];      
    u16 Crc;            
#ifdef __ICCARM__
} OnfiParamPage;
#pragma pack(pop)
#else
}__attribute__((packed))OnfiParamPage;
#endif
 
/* ONFI extended parameter page structure. */
#ifdef __ICCARM__
#pragma pack(push, 1)
#endif
typedef struct {
    u16 Crc;
    u8 Sig[4];
    u8 Reserved1[10];
    u8 Section0Type;
    u8 Section0Len;
    u8 Section1Type;
    u8 Section1Len;
    u8 ResSection[12];
    u8 SectionData[256];
#ifdef __ICCARM__
} OnfiExtPrmPage;
#pragma pack(pop)
#else
}__attribute__((packed))OnfiExtPrmPage;
#endif
 
/* Driver extended parameter page information. */
#ifdef __ICCARM__
#pragma pack(push, 1)
#endif
typedef struct {
    u8 NumEccBits;
    u8 CodeWordSize;
    u16 MaxBadBlocks;
    u16 BlockEndurance;
    u16 Reserved;
#ifdef __ICCARM__
} OnfiExtEccBlock;
#pragma pack(pop)
#else
}__attribute__((packed))OnfiExtEccBlock;
#endif
 
typedef struct {
    u8 Command1;            
    u8 Command2;            
} OnfiCmdFormat;
 
extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
 
/************************** Function Prototypes ******************************/
 
u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
 
#ifdef __cplusplus
}
#endif
 
#endif /* XNANDPSU_ONFI_H end of protection macro */