RTEMS
6.3
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bsps
bfin
include
libcpu
sportRegs.h
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/* Blackfin SPORT Registers
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*
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* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
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* written by Allan Hessenflow <allanh@kallisti.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef _sportRegs_h_
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#define _sportRegs_h_
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/* register addresses */
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#define SPORT_TCR1_OFFSET 0x0000
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#define SPORT_TCR2_OFFSET 0x0004
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#define SPORT_TCLKDIV_OFFSET 0x0008
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#define SPORT_TFSDIV_OFFSET 0x000c
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#define SPORT_TX_OFFSET 0x0010
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#define SPORT_RX_OFFSET 0x0018
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#define SPORT_RCR1_OFFSET 0x0020
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#define SPORT_RCR2_OFFSET 0x0024
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#define SPORT_RCLKDIV_OFFSET 0x0028
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#define SPORT_RFSDIV_OFFSET 0x002c
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#define SPORT_STAT_OFFSET 0x0030
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#define SPORT_CHNL_OFFSET 0x0034
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#define SPORT_MCMC1_OFFSET 0x0038
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#define SPORT_MCMC2_OFFSET 0x003c
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#define SPORT_MTCS0_OFFSET 0x0040
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#define SPORT_MTCS1_OFFSET 0x0044
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#define SPORT_MTCS2_OFFSET 0x0048
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#define SPORT_MTCS3_OFFSET 0x004c
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#define SPORT_MRCS0_OFFSET 0x0050
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#define SPORT_MRCS1_OFFSET 0x0054
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#define SPORT_MRCS2_OFFSET 0x0058
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#define SPORT_MRCS3_OFFSET 0x005c
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/* register fields */
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#define SPORT_TCR1_TCKFE 0x4000
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#define SPORT_TCR1_LATFS 0x2000
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#define SPORT_TCR1_LTFS 0x1000
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#define SPORT_TCR1_DITFS 0x0800
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#define SPORT_TCR1_TFSR 0x0400
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#define SPORT_TCR1_ITFS 0x0200
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#define SPORT_TCR1_TLSBIT 0x0010
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#define SPORT_TCR1_TDTYPE_MASK 0x000c
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#define SPORT_TCR1_TDTYPE_NORMAL 0x0000
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#define SPORT_TCR1_TDTYPE_ULAW 0x0008
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#define SPORT_TCR1_TDTYPE_ALAW 0x000c
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#define SPORT_TCR1_ITCLK 0x0002
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#define SPORT_TCR1_TSPEN 0x0001
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#define SPORT_TCR2_TRFST 0x0400
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#define SPORT_TCR2_TSFSE 0x0200
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#define SPORT_TCR2_TXSE 0x0100
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#define SPORT_TCR2_SLEN_MASK 0x001f
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#define SPORT_TCR2_SLEN_SHIFT 0
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#define SPORT_RCR1_RCKFE 0x4000
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#define SPORT_RCR1_LARFS 0x2000
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#define SPORT_RCR1_LRFS 0x1000
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#define SPORT_RCR1_RFSR 0x0400
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#define SPORT_RCR1_IRFS 0x0200
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#define SPORT_RCR1_RLSBIT 0x0010
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#define SPORT_RCR1_RDTYPE_MASK 0x000c
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#define SPORT_RCR1_RDTYPE_ZEROFILL 0x0000
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#define SPORT_RCR1_RDTYPE_SIGNEXTEND 0x0004
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#define SPORT_RCR1_RDTYPE_ULAW 0x0008
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#define SPORT_RCR1_RDTYPE_ALAW 0x000c
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#define SPORT_RCR1_IRCLK 0x0002
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#define SPORT_RCR1_RSPEN 0x0001
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#define SPORT_RCR2_RRFST 0x0400
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#define SPORT_RCR2_RSFSE 0x0200
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#define SPORT_RCR2_RXSE 0x0100
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#define SPORT_RCR2_SLEN_MASK 0x001f
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#define SPORT_RCR2_SLEN_SHIFT 0
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#define SPORT_STAT_TXHRE 0x0040
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#define SPORT_STAT_TOVF 0x0020
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#define SPORT_STAT_TUVF 0x0010
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#define SPORT_STAT_TXF 0x0008
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#define SPORT_STAT_ROVF 0x0004
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#define SPORT_STAT_RUVF 0x0002
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#define SPORT_STAT_RXNE 0x0001
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#define SPORT_CHNL_CHNL_MASK 0x03ff
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#define SPORT_CHNL_CHNL_SHIFT 0
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#define SPORT_MCMC1_WSIZE_MASK 0xf000
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#define SPORT_MCMC1_WSIZE_SHIFT 12
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#define SPORT_MCMC1_WOFF_MASK 0x03ff
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#define SPORT_MCMC1_WOFF_SHIFT 0
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#define SPORT_MCMC2_MFD_MASK 0xf000
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#define SPORT_MCMC2_MFD_SHIFT 12
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#define SPORT_MCMC2_FSDR 0x0080
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#define SPORT_MCMC2_MCMEN 0x0010
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#define SPORT_MCMC2_MCDRXPE 0x0008
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#define SPORT_MCMC2_MCDTXPE 0x0004
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#define SPORT_MCMC2_MCCRM_MASK 0x0003
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#define SPORT_MCMC2_MCCRM_BYPASS 0x0000
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#define SPORT_MCMC2_MCCRM_2_4 0x0002
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#define SPORT_MCMC2_MCCRM_8_16 0x0003
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#endif
/* _sportRegs_h_ */
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