RTEMS
6.3
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bsps
arm
atsam
include
libchip
include
samv71
component
component_smc.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMV71_SMC_COMPONENT_
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#define _SAMV71_SMC_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__IO
uint32_t SMC_SETUP;
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__IO
uint32_t SMC_PULSE;
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__IO
uint32_t SMC_CYCLE;
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__IO
uint32_t SMC_MODE;
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}
SmcCs_number
;
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#define SMCCS_NUMBER_NUMBER 4
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typedef
struct
{
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SmcCs_number
SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER];
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__I
uint32_t Reserved1[16];
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__IO
uint32_t SMC_OCMS;
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__O
uint32_t SMC_KEY1;
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__O
uint32_t SMC_KEY2;
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__I
uint32_t Reserved2[22];
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__IO
uint32_t SMC_WPMR;
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__I
uint32_t SMC_WPSR;
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__I
uint32_t Reserved3[4];
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__I
uint32_t
SMC_VERSION
;
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}
Smc
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
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#define SMC_SETUP_NWE_SETUP_Pos 0
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#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos)
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#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
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#define SMC_SETUP_NCS_WR_SETUP_Pos 8
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#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos)
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#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
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#define SMC_SETUP_NRD_SETUP_Pos 16
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#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos)
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#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
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#define SMC_SETUP_NCS_RD_SETUP_Pos 24
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#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos)
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#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
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/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
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#define SMC_PULSE_NWE_PULSE_Pos 0
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#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos)
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#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
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#define SMC_PULSE_NCS_WR_PULSE_Pos 8
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#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos)
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#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
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#define SMC_PULSE_NRD_PULSE_Pos 16
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#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos)
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#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
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#define SMC_PULSE_NCS_RD_PULSE_Pos 24
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#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos)
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#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
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/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
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#define SMC_CYCLE_NWE_CYCLE_Pos 0
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#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos)
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#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
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#define SMC_CYCLE_NRD_CYCLE_Pos 16
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#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos)
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#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
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/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */
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#define SMC_MODE_READ_MODE (0x1u << 0)
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#define SMC_MODE_WRITE_MODE (0x1u << 1)
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#define SMC_MODE_EXNW_MODE_Pos 4
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#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos)
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#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)))
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#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4)
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#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4)
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#define SMC_MODE_EXNW_MODE_READY (0x3u << 4)
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#define SMC_MODE_BAT (0x1u << 8)
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#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8)
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#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8)
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#define SMC_MODE_DBW (0x1u << 12)
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#define SMC_MODE_DBW_8_BIT (0x0u << 12)
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#define SMC_MODE_DBW_16_BIT (0x1u << 12)
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#define SMC_MODE_TDF_CYCLES_Pos 16
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#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos)
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#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
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#define SMC_MODE_TDF_MODE (0x1u << 20)
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#define SMC_MODE_PMEN (0x1u << 24)
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#define SMC_MODE_PS_Pos 28
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#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos)
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#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)))
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#define SMC_MODE_PS_4_BYTE (0x0u << 28)
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#define SMC_MODE_PS_8_BYTE (0x1u << 28)
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#define SMC_MODE_PS_16_BYTE (0x2u << 28)
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#define SMC_MODE_PS_32_BYTE (0x3u << 28)
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/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
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#define SMC_OCMS_SMSE (0x1u << 0)
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/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
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#define SMC_KEY1_KEY1_Pos 0
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#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos)
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#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
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/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
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#define SMC_KEY2_KEY2_Pos 0
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#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos)
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#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
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/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */
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#define SMC_WPMR_WPEN (0x1u << 0)
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#define SMC_WPMR_WPKEY_Pos 8
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#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos)
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#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
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#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8)
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/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */
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#define SMC_WPSR_WPVS (0x1u << 0)
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#define SMC_WPSR_WPVSRC_Pos 8
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#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos)
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/* -------- SMC_VERSION : (SMC Offset: 0xFC) SMC Version Register -------- */
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#define SMC_VERSION_VERSION_Pos 0
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#define SMC_VERSION_VERSION_Msk (0xfffu << SMC_VERSION_VERSION_Pos)
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#define SMC_VERSION_MFN_Pos 16
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#define SMC_VERSION_MFN_Msk (0x7u << SMC_VERSION_MFN_Pos)
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#endif
/* _SAMV71_SMC_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
SmcCs_number
SmcCs_number hardware registers.
Definition
component_smc.h:41
Smc
Definition
component_smc.h:49
Smc::SMC_VERSION
__I uint32_t SMC_VERSION
(Smc Offset: 0xFC) SMC Version Register
Definition
component_smc.h:59
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