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bsps
arm
atsam
include
libchip
include
sams70
component
component_twihs.h
1
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMS70_TWIHS_COMPONENT_
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#define _SAMS70_TWIHS_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__O
uint32_t TWIHS_CR;
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__IO
uint32_t TWIHS_MMR;
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__IO
uint32_t TWIHS_SMR;
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__IO
uint32_t TWIHS_IADR;
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__IO
uint32_t TWIHS_CWGR;
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__I
uint32_t Reserved1[3];
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__I
uint32_t TWIHS_SR;
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__O
uint32_t TWIHS_IER;
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__O
uint32_t TWIHS_IDR;
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__I
uint32_t TWIHS_IMR;
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__I
uint32_t TWIHS_RHR;
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__O
uint32_t TWIHS_THR;
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__IO
uint32_t TWIHS_SMBTR;
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__I
uint32_t Reserved2[2];
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__IO
uint32_t TWIHS_FILTR;
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__I
uint32_t Reserved3[1];
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__IO
uint32_t TWIHS_SWMR;
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__I
uint32_t Reserved4[37];
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__IO
uint32_t TWIHS_WPMR;
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__I
uint32_t TWIHS_WPSR;
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}
Twihs
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */
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#define TWIHS_CR_START (0x1u << 0)
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#define TWIHS_CR_STOP (0x1u << 1)
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#define TWIHS_CR_MSEN (0x1u << 2)
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#define TWIHS_CR_MSDIS (0x1u << 3)
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#define TWIHS_CR_SVEN (0x1u << 4)
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#define TWIHS_CR_SVDIS (0x1u << 5)
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#define TWIHS_CR_QUICK (0x1u << 6)
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#define TWIHS_CR_SWRST (0x1u << 7)
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#define TWIHS_CR_HSEN (0x1u << 8)
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#define TWIHS_CR_HSDIS (0x1u << 9)
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#define TWIHS_CR_SMBEN (0x1u << 10)
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#define TWIHS_CR_SMBDIS (0x1u << 11)
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#define TWIHS_CR_PECEN (0x1u << 12)
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#define TWIHS_CR_PECDIS (0x1u << 13)
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#define TWIHS_CR_PECRQ (0x1u << 14)
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#define TWIHS_CR_CLEAR (0x1u << 15)
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/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */
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#define TWIHS_MMR_IADRSZ_Pos 8
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#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos)
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#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)))
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#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8)
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#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8)
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#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8)
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#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8)
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#define TWIHS_MMR_MREAD (0x1u << 12)
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#define TWIHS_MMR_DADR_Pos 16
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#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos)
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#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)))
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/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */
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#define TWIHS_SMR_NACKEN (0x1u << 0)
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#define TWIHS_SMR_SMDA (0x1u << 2)
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#define TWIHS_SMR_SMHH (0x1u << 3)
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#define TWIHS_SMR_SCLWSDIS (0x1u << 6)
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#define TWIHS_SMR_MASK_Pos 8
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#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos)
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#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)))
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#define TWIHS_SMR_SADR_Pos 16
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#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos)
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#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)))
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#define TWIHS_SMR_SADR1EN (0x1u << 28)
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#define TWIHS_SMR_SADR2EN (0x1u << 29)
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#define TWIHS_SMR_SADR3EN (0x1u << 30)
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#define TWIHS_SMR_DATAMEN (0x1u << 31)
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/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */
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#define TWIHS_IADR_IADR_Pos 0
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#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos)
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#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)))
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/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */
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#define TWIHS_CWGR_CLDIV_Pos 0
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#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos)
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#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)))
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#define TWIHS_CWGR_CHDIV_Pos 8
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#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos)
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#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)))
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#define TWIHS_CWGR_CKDIV_Pos 16
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#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos)
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#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)))
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#define TWIHS_CWGR_HOLD_Pos 24
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#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos)
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#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)))
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/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */
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#define TWIHS_SR_TXCOMP (0x1u << 0)
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#define TWIHS_SR_RXRDY (0x1u << 1)
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#define TWIHS_SR_TXRDY (0x1u << 2)
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#define TWIHS_SR_SVREAD (0x1u << 3)
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#define TWIHS_SR_SVACC (0x1u << 4)
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#define TWIHS_SR_GACC (0x1u << 5)
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#define TWIHS_SR_OVRE (0x1u << 6)
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#define TWIHS_SR_UNRE (0x1u << 7)
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#define TWIHS_SR_NACK (0x1u << 8)
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#define TWIHS_SR_ARBLST (0x1u << 9)
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#define TWIHS_SR_SCLWS (0x1u << 10)
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#define TWIHS_SR_EOSACC (0x1u << 11)
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#define TWIHS_SR_MCACK (0x1u << 16)
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#define TWIHS_SR_TOUT (0x1u << 18)
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#define TWIHS_SR_PECERR (0x1u << 19)
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#define TWIHS_SR_SMBDAM (0x1u << 20)
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#define TWIHS_SR_SMBHHM (0x1u << 21)
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#define TWIHS_SR_SCL (0x1u << 24)
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#define TWIHS_SR_SDA (0x1u << 25)
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/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */
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#define TWIHS_IER_TXCOMP (0x1u << 0)
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#define TWIHS_IER_RXRDY (0x1u << 1)
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#define TWIHS_IER_TXRDY (0x1u << 2)
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#define TWIHS_IER_SVACC (0x1u << 4)
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#define TWIHS_IER_GACC (0x1u << 5)
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#define TWIHS_IER_OVRE (0x1u << 6)
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#define TWIHS_IER_UNRE (0x1u << 7)
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#define TWIHS_IER_NACK (0x1u << 8)
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#define TWIHS_IER_ARBLST (0x1u << 9)
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#define TWIHS_IER_SCL_WS (0x1u << 10)
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#define TWIHS_IER_EOSACC (0x1u << 11)
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#define TWIHS_IER_MCACK (0x1u << 16)
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#define TWIHS_IER_TOUT (0x1u << 18)
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#define TWIHS_IER_PECERR (0x1u << 19)
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#define TWIHS_IER_SMBDAM (0x1u << 20)
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#define TWIHS_IER_SMBHHM (0x1u << 21)
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/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */
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#define TWIHS_IDR_TXCOMP (0x1u << 0)
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#define TWIHS_IDR_RXRDY (0x1u << 1)
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#define TWIHS_IDR_TXRDY (0x1u << 2)
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#define TWIHS_IDR_SVACC (0x1u << 4)
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#define TWIHS_IDR_GACC (0x1u << 5)
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#define TWIHS_IDR_OVRE (0x1u << 6)
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#define TWIHS_IDR_UNRE (0x1u << 7)
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#define TWIHS_IDR_NACK (0x1u << 8)
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#define TWIHS_IDR_ARBLST (0x1u << 9)
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#define TWIHS_IDR_SCL_WS (0x1u << 10)
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#define TWIHS_IDR_EOSACC (0x1u << 11)
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#define TWIHS_IDR_MCACK (0x1u << 16)
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#define TWIHS_IDR_TOUT (0x1u << 18)
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#define TWIHS_IDR_PECERR (0x1u << 19)
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#define TWIHS_IDR_SMBDAM (0x1u << 20)
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#define TWIHS_IDR_SMBHHM (0x1u << 21)
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/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */
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#define TWIHS_IMR_TXCOMP (0x1u << 0)
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#define TWIHS_IMR_RXRDY (0x1u << 1)
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#define TWIHS_IMR_TXRDY (0x1u << 2)
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#define TWIHS_IMR_SVACC (0x1u << 4)
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#define TWIHS_IMR_GACC (0x1u << 5)
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#define TWIHS_IMR_OVRE (0x1u << 6)
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#define TWIHS_IMR_UNRE (0x1u << 7)
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#define TWIHS_IMR_NACK (0x1u << 8)
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#define TWIHS_IMR_ARBLST (0x1u << 9)
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#define TWIHS_IMR_SCL_WS (0x1u << 10)
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#define TWIHS_IMR_EOSACC (0x1u << 11)
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#define TWIHS_IMR_MCACK (0x1u << 16)
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#define TWIHS_IMR_TOUT (0x1u << 18)
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#define TWIHS_IMR_PECERR (0x1u << 19)
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#define TWIHS_IMR_SMBDAM (0x1u << 20)
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#define TWIHS_IMR_SMBHHM (0x1u << 21)
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/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */
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#define TWIHS_RHR_RXDATA_Pos 0
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#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos)
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/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */
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#define TWIHS_THR_TXDATA_Pos 0
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#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos)
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#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)))
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/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */
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#define TWIHS_SMBTR_PRESC_Pos 0
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#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos)
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#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)))
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#define TWIHS_SMBTR_TLOWS_Pos 8
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#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos)
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#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)))
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#define TWIHS_SMBTR_TLOWM_Pos 16
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#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos)
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#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)))
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#define TWIHS_SMBTR_THMAX_Pos 24
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#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos)
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#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)))
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/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */
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#define TWIHS_FILTR_FILT (0x1u << 0)
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#define TWIHS_FILTR_PADFEN (0x1u << 1)
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#define TWIHS_FILTR_PADFCFG (0x1u << 2)
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#define TWIHS_FILTR_THRES_Pos 8
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#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos)
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#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)))
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/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */
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#define TWIHS_SWMR_SADR1_Pos 0
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#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos)
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#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)))
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#define TWIHS_SWMR_SADR2_Pos 8
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#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos)
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#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)))
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#define TWIHS_SWMR_SADR3_Pos 16
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#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos)
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#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)))
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#define TWIHS_SWMR_DATAM_Pos 24
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#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos)
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#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)))
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/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */
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#define TWIHS_WPMR_WPEN (0x1u << 0)
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#define TWIHS_WPMR_WPKEY_Pos 8
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#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos)
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#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)))
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#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8)
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/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */
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#define TWIHS_WPSR_WPVS (0x1u << 0)
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#define TWIHS_WPSR_WPVSRC_Pos 8
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#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos)
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#endif
/* _SAMS70_TWIHS_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
Twihs
Twihs hardware registers.
Definition
component_twihs.h:41
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