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bsps
arm
atsam
include
libchip
include
sams70
component
component_qspi.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMS70_QSPI_COMPONENT_
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#define _SAMS70_QSPI_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__O
uint32_t QSPI_CR;
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__IO
uint32_t QSPI_MR;
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__I
uint32_t QSPI_RDR;
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__O
uint32_t QSPI_TDR;
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__I
uint32_t QSPI_SR;
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__O
uint32_t QSPI_IER;
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__O
uint32_t QSPI_IDR;
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__I
uint32_t QSPI_IMR;
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__IO
uint32_t QSPI_SCR;
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__I
uint32_t Reserved1[3];
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__IO
uint32_t QSPI_IAR;
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__IO
uint32_t QSPI_ICR;
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__IO
uint32_t QSPI_IFR;
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__I
uint32_t Reserved2[1];
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__IO
uint32_t QSPI_SMR;
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__O
uint32_t QSPI_SKR;
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__I
uint32_t Reserved3[39];
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__IO
uint32_t QSPI_WPMR;
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__I
uint32_t QSPI_WPSR;
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}
Qspi
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */
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#define QSPI_CR_QSPIEN (0x1u << 0)
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#define QSPI_CR_QSPIDIS (0x1u << 1)
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#define QSPI_CR_SWRST (0x1u << 7)
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#define QSPI_CR_LASTXFER (0x1u << 24)
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/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */
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#define QSPI_MR_SMM (0x1u << 0)
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#define QSPI_MR_SMM_SPI (0x0u << 0)
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#define QSPI_MR_SMM_MEMORY (0x1u << 0)
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#define QSPI_MR_LLB (0x1u << 1)
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#define QSPI_MR_LLB_DISABLED (0x0u << 1)
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#define QSPI_MR_LLB_ENABLED (0x1u << 1)
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#define QSPI_MR_WDRBT (0x1u << 2)
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#define QSPI_MR_WDRBT_DISABLED (0x0u << 2)
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#define QSPI_MR_WDRBT_ENABLED (0x1u << 2)
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#define QSPI_MR_CSMODE_Pos 4
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#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos)
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#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))
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#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4)
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#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4)
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#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4)
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#define QSPI_MR_NBBITS_Pos 8
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#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos)
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#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))
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#define QSPI_MR_NBBITS_8_BIT (0x0u << 8)
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#define QSPI_MR_NBBITS_16_BIT (0x8u << 8)
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#define QSPI_MR_DLYBCT_Pos 16
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#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos)
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#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))
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#define QSPI_MR_DLYCS_Pos 24
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#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos)
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#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))
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/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */
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#define QSPI_RDR_RD_Pos 0
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#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos)
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/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */
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#define QSPI_TDR_TD_Pos 0
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#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos)
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#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))
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/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */
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#define QSPI_SR_RDRF (0x1u << 0)
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#define QSPI_SR_TDRE (0x1u << 1)
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#define QSPI_SR_TXEMPTY (0x1u << 2)
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#define QSPI_SR_OVRES (0x1u << 3)
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#define QSPI_SR_CSR (0x1u << 8)
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#define QSPI_SR_CSS (0x1u << 9)
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#define QSPI_SR_INSTRE (0x1u << 10)
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#define QSPI_SR_QSPIENS (0x1u << 24)
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/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */
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#define QSPI_IER_RDRF (0x1u << 0)
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#define QSPI_IER_TDRE (0x1u << 1)
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#define QSPI_IER_TXEMPTY (0x1u << 2)
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#define QSPI_IER_OVRES (0x1u << 3)
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#define QSPI_IER_CSR (0x1u << 8)
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#define QSPI_IER_CSS (0x1u << 9)
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#define QSPI_IER_INSTRE (0x1u << 10)
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/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */
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#define QSPI_IDR_RDRF (0x1u << 0)
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#define QSPI_IDR_TDRE (0x1u << 1)
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#define QSPI_IDR_TXEMPTY (0x1u << 2)
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#define QSPI_IDR_OVRES (0x1u << 3)
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#define QSPI_IDR_CSR (0x1u << 8)
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#define QSPI_IDR_CSS (0x1u << 9)
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#define QSPI_IDR_INSTRE (0x1u << 10)
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/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */
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#define QSPI_IMR_RDRF (0x1u << 0)
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#define QSPI_IMR_TDRE (0x1u << 1)
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#define QSPI_IMR_TXEMPTY (0x1u << 2)
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#define QSPI_IMR_OVRES (0x1u << 3)
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#define QSPI_IMR_CSR (0x1u << 8)
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#define QSPI_IMR_CSS (0x1u << 9)
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#define QSPI_IMR_INSTRE (0x1u << 10)
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/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */
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#define QSPI_SCR_CPOL (0x1u << 0)
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#define QSPI_SCR_CPHA (0x1u << 1)
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#define QSPI_SCR_SCBR_Pos 8
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#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos)
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#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))
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#define QSPI_SCR_DLYBS_Pos 16
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#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos)
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#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))
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/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */
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#define QSPI_IAR_ADDR_Pos 0
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#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos)
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#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))
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/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */
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#define QSPI_ICR_INST_Pos 0
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#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos)
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#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))
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#define QSPI_ICR_OPT_Pos 16
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#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos)
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#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))
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/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */
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#define QSPI_IFR_WIDTH_Pos 0
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#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos)
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#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))
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#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0)
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#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0)
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#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0)
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#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0)
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#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0)
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#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0)
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#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0)
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#define QSPI_IFR_INSTEN (0x1u << 4)
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#define QSPI_IFR_ADDREN (0x1u << 5)
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#define QSPI_IFR_OPTEN (0x1u << 6)
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#define QSPI_IFR_DATAEN (0x1u << 7)
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#define QSPI_IFR_OPTL_Pos 8
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#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos)
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#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))
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#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8)
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#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8)
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#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8)
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#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8)
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#define QSPI_IFR_ADDRL (0x1u << 10)
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#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10)
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#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10)
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#define QSPI_IFR_TFRTYP_Pos 12
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#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos)
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#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))
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#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12)
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#define QSPI_IFR_CRM (0x1u << 14)
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#define QSPI_IFR_CRM_DISABLED (0x0u << 14)
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#define QSPI_IFR_CRM_ENABLED (0x1u << 14)
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#define QSPI_IFR_NBDUM_Pos 16
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#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos)
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#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))
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/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */
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#define QSPI_SMR_SCREN (0x1u << 0)
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#define QSPI_SMR_SCREN_DISABLED (0x0u << 0)
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#define QSPI_SMR_SCREN_ENABLED (0x1u << 0)
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#define QSPI_SMR_RVDIS (0x1u << 1)
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/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */
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#define QSPI_SKR_USRK_Pos 0
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#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos)
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#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))
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/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */
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#define QSPI_WPMR_WPEN (0x1u << 0)
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#define QSPI_WPMR_WPKEY_Pos 8
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#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos)
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#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))
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#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8)
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/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */
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#define QSPI_WPSR_WPVS (0x1u << 0)
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#define QSPI_WPSR_WPVSRC_Pos 8
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#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos)
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#endif
/* _SAMS70_QSPI_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
Qspi
Qspi hardware registers.
Definition
component_qspi.h:41
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