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bsps
arm
atsam
include
libchip
include
sams70
component
component_icm.h
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAMS70_ICM_COMPONENT_
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#define _SAMS70_ICM_COMPONENT_
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/* ============================================================================= */
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/* ============================================================================= */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef
struct
{
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__IO
uint32_t ICM_CFG;
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__O
uint32_t ICM_CTRL;
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__O
uint32_t ICM_SR;
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__I
uint32_t Reserved1[1];
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__O
uint32_t ICM_IER;
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__O
uint32_t ICM_IDR;
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__I
uint32_t ICM_IMR;
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__I
uint32_t ICM_ISR;
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__I
uint32_t ICM_UASR;
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__I
uint32_t Reserved2[3];
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__IO
uint32_t ICM_DSCR;
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__IO
uint32_t ICM_HASH;
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__O
uint32_t ICM_UIHVAL[8];
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}
Icm
;
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#endif
/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */
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#define ICM_CFG_WBDIS (0x1u << 0)
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#define ICM_CFG_EOMDIS (0x1u << 1)
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#define ICM_CFG_SLBDIS (0x1u << 2)
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#define ICM_CFG_BBC_Pos 4
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#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos)
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#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))
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#define ICM_CFG_ASCD (0x1u << 8)
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#define ICM_CFG_DUALBUFF (0x1u << 9)
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#define ICM_CFG_UIHASH (0x1u << 12)
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#define ICM_CFG_UALGO_Pos 13
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#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos)
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#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)))
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#define ICM_CFG_UALGO_SHA1 (0x0u << 13)
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#define ICM_CFG_UALGO_SHA256 (0x1u << 13)
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#define ICM_CFG_UALGO_SHA224 (0x4u << 13)
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#define ICM_CFG_HAPROT_Pos 16
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#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos)
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#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))
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#define ICM_CFG_DAPROT_Pos 24
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#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos)
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#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))
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/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */
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#define ICM_CTRL_ENABLE (0x1u << 0)
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#define ICM_CTRL_DISABLE (0x1u << 1)
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#define ICM_CTRL_SWRST (0x1u << 2)
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#define ICM_CTRL_REHASH_Pos 4
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#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos)
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#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))
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#define ICM_CTRL_RMDIS_Pos 8
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#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos)
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#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))
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#define ICM_CTRL_RMEN_Pos 12
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#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos)
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#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))
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/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */
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#define ICM_SR_ENABLE (0x1u << 0)
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#define ICM_SR_RAWRMDIS_Pos 8
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#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos)
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#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))
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#define ICM_SR_RMDIS_Pos 12
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#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos)
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#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))
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/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */
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#define ICM_IER_RHC_Pos 0
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#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos)
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#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))
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#define ICM_IER_RDM_Pos 4
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#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos)
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#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))
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#define ICM_IER_RBE_Pos 8
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#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos)
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#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))
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#define ICM_IER_RWC_Pos 12
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#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos)
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#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))
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#define ICM_IER_REC_Pos 16
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#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos)
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#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))
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#define ICM_IER_RSU_Pos 20
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#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos)
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#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))
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#define ICM_IER_URAD (0x1u << 24)
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/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */
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#define ICM_IDR_RHC_Pos 0
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#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos)
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#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))
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#define ICM_IDR_RDM_Pos 4
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#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos)
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#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))
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#define ICM_IDR_RBE_Pos 8
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#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos)
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#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))
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#define ICM_IDR_RWC_Pos 12
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#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos)
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#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))
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#define ICM_IDR_REC_Pos 16
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#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos)
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#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))
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#define ICM_IDR_RSU_Pos 20
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#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos)
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#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))
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#define ICM_IDR_URAD (0x1u << 24)
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/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */
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#define ICM_IMR_RHC_Pos 0
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#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos)
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#define ICM_IMR_RDM_Pos 4
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#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos)
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#define ICM_IMR_RBE_Pos 8
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#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos)
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#define ICM_IMR_RWC_Pos 12
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#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos)
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#define ICM_IMR_REC_Pos 16
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#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos)
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#define ICM_IMR_RSU_Pos 20
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#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos)
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#define ICM_IMR_URAD (0x1u << 24)
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/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */
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#define ICM_ISR_RHC_Pos 0
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#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos)
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#define ICM_ISR_RDM_Pos 4
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#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos)
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#define ICM_ISR_RBE_Pos 8
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#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos)
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#define ICM_ISR_RWC_Pos 12
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#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos)
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#define ICM_ISR_REC_Pos 16
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#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos)
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#define ICM_ISR_RSU_Pos 20
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#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos)
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#define ICM_ISR_URAD (0x1u << 24)
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/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */
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#define ICM_UASR_URAT_Pos 0
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#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos)
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#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0)
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#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0)
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#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0)
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#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0)
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#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0)
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/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */
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#define ICM_DSCR_DASA_Pos 6
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#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos)
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#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))
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/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */
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#define ICM_HASH_HASA_Pos 7
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#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos)
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#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))
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/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */
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#define ICM_UIHVAL_VAL_Pos 0
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#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos)
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#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))
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#endif
/* _SAMS70_ICM_COMPONENT_ */
__O
#define __O
Definition
core_cm4.h:238
__IO
#define __IO
Definition
core_cm4.h:239
__I
#define __I
Definition
core_cm4.h:236
Icm
Icm hardware registers.
Definition
component_icm.h:41
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