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#ifndef _SAMS70_AFEC_COMPONENT_

#define _SAMS70_AFEC_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __O  uint32_t AFEC_CR;

  __IO uint32_t AFEC_MR;

  __IO uint32_t AFEC_EMR;

  __IO uint32_t AFEC_SEQ1R;

  __IO uint32_t AFEC_SEQ2R;

  __O  uint32_t AFEC_CHER;

  __O  uint32_t AFEC_CHDR;

  __I  uint32_t AFEC_CHSR;

  __I  uint32_t AFEC_LCDR;

  __O  uint32_t AFEC_IER;

  __O  uint32_t AFEC_IDR;

  __I  uint32_t AFEC_IMR;

  __I  uint32_t AFEC_ISR;

  __I  uint32_t Reserved1[6];

  __I  uint32_t AFEC_OVER;

  __IO uint32_t AFEC_CWR;

  __IO uint32_t AFEC_CGR;

  __I  uint32_t Reserved2[2];

  __IO uint32_t AFEC_DIFFR;

  __IO uint32_t AFEC_CSELR;

  __I  uint32_t AFEC_CDR;

  __IO uint32_t AFEC_COCR;

  __IO uint32_t AFEC_TEMPMR;

  __IO uint32_t AFEC_TEMPCWR;

  __I  uint32_t Reserved3[7];

  __IO uint32_t AFEC_ACR;

  __I  uint32_t Reserved4[2];

  __IO uint32_t AFEC_SHMR;

  __I  uint32_t Reserved5[11];

  __IO uint32_t AFEC_COSR;

  __IO uint32_t AFEC_CVR;

  __IO uint32_t AFEC_CECR;

  __I  uint32_t Reserved6[2];

  __IO uint32_t AFEC_WPMR;

  __I  uint32_t AFEC_WPSR;

} Afec;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */

#define AFEC_CR_SWRST (0x1u << 0)

#define AFEC_CR_START (0x1u << 1)

/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */

#define AFEC_MR_TRGEN (0x1u << 0)

#define   AFEC_MR_TRGEN_DIS (0x0u << 0)

#define   AFEC_MR_TRGEN_EN (0x1u << 0)

#define AFEC_MR_TRGSEL_Pos 1

#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos)

#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)))

#define   AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1)

#define   AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1)

#define   AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1)

#define   AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1)

#define   AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1)

#define   AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1)

#define   AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1)

#define AFEC_MR_SLEEP (0x1u << 5)

#define   AFEC_MR_SLEEP_NORMAL (0x0u << 5)

#define   AFEC_MR_SLEEP_SLEEP (0x1u << 5)

#define AFEC_MR_FWUP (0x1u << 6)

#define   AFEC_MR_FWUP_OFF (0x0u << 6)

#define   AFEC_MR_FWUP_ON (0x1u << 6)

#define AFEC_MR_FREERUN (0x1u << 7)

#define   AFEC_MR_FREERUN_OFF (0x0u << 7)

#define   AFEC_MR_FREERUN_ON (0x1u << 7)

#define AFEC_MR_PRESCAL_Pos 8

#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos)

#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))

#define AFEC_MR_STARTUP_Pos 16

#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos)

#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)))

#define   AFEC_MR_STARTUP_SUT0 (0x0u << 16)

#define   AFEC_MR_STARTUP_SUT8 (0x1u << 16)

#define   AFEC_MR_STARTUP_SUT16 (0x2u << 16)

#define   AFEC_MR_STARTUP_SUT24 (0x3u << 16)

#define   AFEC_MR_STARTUP_SUT64 (0x4u << 16)

#define   AFEC_MR_STARTUP_SUT80 (0x5u << 16)

#define   AFEC_MR_STARTUP_SUT96 (0x6u << 16)

#define   AFEC_MR_STARTUP_SUT112 (0x7u << 16)

#define   AFEC_MR_STARTUP_SUT512 (0x8u << 16)

#define   AFEC_MR_STARTUP_SUT576 (0x9u << 16)

#define   AFEC_MR_STARTUP_SUT640 (0xAu << 16)

#define   AFEC_MR_STARTUP_SUT704 (0xBu << 16)

#define   AFEC_MR_STARTUP_SUT768 (0xCu << 16)

#define   AFEC_MR_STARTUP_SUT832 (0xDu << 16)

#define   AFEC_MR_STARTUP_SUT896 (0xEu << 16)

#define   AFEC_MR_STARTUP_SUT960 (0xFu << 16)

#define AFEC_MR_ONE (0x1u << 23)

#define AFEC_MR_TRACKTIM_Pos 24

#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos)

#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))

#define AFEC_MR_TRANSFER_Pos 28

#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos)

#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))

#define AFEC_MR_USEQ (0x1u << 31)

#define   AFEC_MR_USEQ_NUM_ORDER (0x0u << 31)

#define   AFEC_MR_USEQ_REG_ORDER (0x1u << 31)

/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */

#define AFEC_EMR_CMPMODE_Pos 0

#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos)

#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)))

#define   AFEC_EMR_CMPMODE_LOW (0x0u << 0)

#define   AFEC_EMR_CMPMODE_HIGH (0x1u << 0)

#define   AFEC_EMR_CMPMODE_IN (0x2u << 0)

#define   AFEC_EMR_CMPMODE_OUT (0x3u << 0)

#define AFEC_EMR_CMPSEL_Pos 3

#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos)

#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))

#define AFEC_EMR_CMPALL (0x1u << 9)

#define AFEC_EMR_CMPFILTER_Pos 12

#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos)

#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))

#define AFEC_EMR_RES_Pos 16

#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos)

#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)))

#define   AFEC_EMR_RES_NO_AVERAGE (0x0u << 16)

#define   AFEC_EMR_RES_OSR4 (0x2u << 16)

#define   AFEC_EMR_RES_OSR16 (0x3u << 16)

#define   AFEC_EMR_RES_OSR64 (0x4u << 16)

#define   AFEC_EMR_RES_OSR256 (0x5u << 16)

#define AFEC_EMR_TAG (0x1u << 24)

#define AFEC_EMR_STM (0x1u << 25)

#define AFEC_EMR_SIGNMODE_Pos 28

#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos)

#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)))

#define   AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28)

#define   AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28)

#define   AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28)

#define   AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28)

/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */

#define AFEC_SEQ1R_USCH0_Pos 0

#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos)

#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))

#define AFEC_SEQ1R_USCH1_Pos 4

#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos)

#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))

#define AFEC_SEQ1R_USCH2_Pos 8

#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos)

#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))

#define AFEC_SEQ1R_USCH3_Pos 12

#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos)

#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))

#define AFEC_SEQ1R_USCH4_Pos 16

#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos)

#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))

#define AFEC_SEQ1R_USCH5_Pos 20

#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos)

#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))

#define AFEC_SEQ1R_USCH6_Pos 24

#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos)

#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))

#define AFEC_SEQ1R_USCH7_Pos 28

#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos)

#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))

/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */

#define AFEC_SEQ2R_USCH8_Pos 0

#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos)

#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))

#define AFEC_SEQ2R_USCH9_Pos 4

#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos)

#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))

#define AFEC_SEQ2R_USCH10_Pos 8

#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos)

#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))

#define AFEC_SEQ2R_USCH11_Pos 12

#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos)

#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))

#define AFEC_SEQ2R_USCH12_Pos 16

#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos)

#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))

#define AFEC_SEQ2R_USCH13_Pos 20

#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos)

#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))

#define AFEC_SEQ2R_USCH14_Pos 24

#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos)

#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))

#define AFEC_SEQ2R_USCH15_Pos 28

#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos)

#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))

/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */

#define AFEC_CHER_CH0 (0x1u << 0)

#define AFEC_CHER_CH1 (0x1u << 1)

#define AFEC_CHER_CH2 (0x1u << 2)

#define AFEC_CHER_CH3 (0x1u << 3)

#define AFEC_CHER_CH4 (0x1u << 4)

#define AFEC_CHER_CH5 (0x1u << 5)

#define AFEC_CHER_CH6 (0x1u << 6)

#define AFEC_CHER_CH7 (0x1u << 7)

#define AFEC_CHER_CH8 (0x1u << 8)

#define AFEC_CHER_CH9 (0x1u << 9)

#define AFEC_CHER_CH10 (0x1u << 10)

#define AFEC_CHER_CH11 (0x1u << 11)

/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */

#define AFEC_CHDR_CH0 (0x1u << 0)

#define AFEC_CHDR_CH1 (0x1u << 1)

#define AFEC_CHDR_CH2 (0x1u << 2)

#define AFEC_CHDR_CH3 (0x1u << 3)

#define AFEC_CHDR_CH4 (0x1u << 4)

#define AFEC_CHDR_CH5 (0x1u << 5)

#define AFEC_CHDR_CH6 (0x1u << 6)

#define AFEC_CHDR_CH7 (0x1u << 7)

#define AFEC_CHDR_CH8 (0x1u << 8)

#define AFEC_CHDR_CH9 (0x1u << 9)

#define AFEC_CHDR_CH10 (0x1u << 10)

#define AFEC_CHDR_CH11 (0x1u << 11)

/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */

#define AFEC_CHSR_CH0 (0x1u << 0)

#define AFEC_CHSR_CH1 (0x1u << 1)

#define AFEC_CHSR_CH2 (0x1u << 2)

#define AFEC_CHSR_CH3 (0x1u << 3)

#define AFEC_CHSR_CH4 (0x1u << 4)

#define AFEC_CHSR_CH5 (0x1u << 5)

#define AFEC_CHSR_CH6 (0x1u << 6)

#define AFEC_CHSR_CH7 (0x1u << 7)

#define AFEC_CHSR_CH8 (0x1u << 8)

#define AFEC_CHSR_CH9 (0x1u << 9)

#define AFEC_CHSR_CH10 (0x1u << 10)

#define AFEC_CHSR_CH11 (0x1u << 11)

/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */

#define AFEC_LCDR_LDATA_Pos 0

#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos)

#define AFEC_LCDR_CHNB_Pos 24

#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos)

/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */

#define AFEC_IER_EOC0 (0x1u << 0)

#define AFEC_IER_EOC1 (0x1u << 1)

#define AFEC_IER_EOC2 (0x1u << 2)

#define AFEC_IER_EOC3 (0x1u << 3)

#define AFEC_IER_EOC4 (0x1u << 4)

#define AFEC_IER_EOC5 (0x1u << 5)

#define AFEC_IER_EOC6 (0x1u << 6)

#define AFEC_IER_EOC7 (0x1u << 7)

#define AFEC_IER_EOC8 (0x1u << 8)

#define AFEC_IER_EOC9 (0x1u << 9)

#define AFEC_IER_EOC10 (0x1u << 10)

#define AFEC_IER_EOC11 (0x1u << 11)

#define AFEC_IER_DRDY (0x1u << 24)

#define AFEC_IER_GOVRE (0x1u << 25)

#define AFEC_IER_COMPE (0x1u << 26)

#define AFEC_IER_TEMPCHG (0x1u << 30)

/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */

#define AFEC_IDR_EOC0 (0x1u << 0)

#define AFEC_IDR_EOC1 (0x1u << 1)

#define AFEC_IDR_EOC2 (0x1u << 2)

#define AFEC_IDR_EOC3 (0x1u << 3)

#define AFEC_IDR_EOC4 (0x1u << 4)

#define AFEC_IDR_EOC5 (0x1u << 5)

#define AFEC_IDR_EOC6 (0x1u << 6)

#define AFEC_IDR_EOC7 (0x1u << 7)

#define AFEC_IDR_EOC8 (0x1u << 8)

#define AFEC_IDR_EOC9 (0x1u << 9)

#define AFEC_IDR_EOC10 (0x1u << 10)

#define AFEC_IDR_EOC11 (0x1u << 11)

#define AFEC_IDR_DRDY (0x1u << 24)

#define AFEC_IDR_GOVRE (0x1u << 25)

#define AFEC_IDR_COMPE (0x1u << 26)

#define AFEC_IDR_TEMPCHG (0x1u << 30)

/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */

#define AFEC_IMR_EOC0 (0x1u << 0)

#define AFEC_IMR_EOC1 (0x1u << 1)

#define AFEC_IMR_EOC2 (0x1u << 2)

#define AFEC_IMR_EOC3 (0x1u << 3)

#define AFEC_IMR_EOC4 (0x1u << 4)

#define AFEC_IMR_EOC5 (0x1u << 5)

#define AFEC_IMR_EOC6 (0x1u << 6)

#define AFEC_IMR_EOC7 (0x1u << 7)

#define AFEC_IMR_EOC8 (0x1u << 8)

#define AFEC_IMR_EOC9 (0x1u << 9)

#define AFEC_IMR_EOC10 (0x1u << 10)

#define AFEC_IMR_EOC11 (0x1u << 11)

#define AFEC_IMR_DRDY (0x1u << 24)

#define AFEC_IMR_GOVRE (0x1u << 25)

#define AFEC_IMR_COMPE (0x1u << 26)

#define AFEC_IMR_TEMPCHG (0x1u << 30)

/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */

#define AFEC_ISR_EOC0 (0x1u << 0)

#define AFEC_ISR_EOC1 (0x1u << 1)

#define AFEC_ISR_EOC2 (0x1u << 2)

#define AFEC_ISR_EOC3 (0x1u << 3)

#define AFEC_ISR_EOC4 (0x1u << 4)

#define AFEC_ISR_EOC5 (0x1u << 5)

#define AFEC_ISR_EOC6 (0x1u << 6)

#define AFEC_ISR_EOC7 (0x1u << 7)

#define AFEC_ISR_EOC8 (0x1u << 8)

#define AFEC_ISR_EOC9 (0x1u << 9)

#define AFEC_ISR_EOC10 (0x1u << 10)

#define AFEC_ISR_EOC11 (0x1u << 11)

#define AFEC_ISR_DRDY (0x1u << 24)

#define AFEC_ISR_GOVRE (0x1u << 25)

#define AFEC_ISR_COMPE (0x1u << 26)

#define AFEC_ISR_TEMPCHG (0x1u << 30)

/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */

#define AFEC_OVER_OVRE0 (0x1u << 0)

#define AFEC_OVER_OVRE1 (0x1u << 1)

#define AFEC_OVER_OVRE2 (0x1u << 2)

#define AFEC_OVER_OVRE3 (0x1u << 3)

#define AFEC_OVER_OVRE4 (0x1u << 4)

#define AFEC_OVER_OVRE5 (0x1u << 5)

#define AFEC_OVER_OVRE6 (0x1u << 6)

#define AFEC_OVER_OVRE7 (0x1u << 7)

#define AFEC_OVER_OVRE8 (0x1u << 8)

#define AFEC_OVER_OVRE9 (0x1u << 9)

#define AFEC_OVER_OVRE10 (0x1u << 10)

#define AFEC_OVER_OVRE11 (0x1u << 11)

/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */

#define AFEC_CWR_LOWTHRES_Pos 0

#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos)

#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))

#define AFEC_CWR_HIGHTHRES_Pos 16

#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos)

#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))

/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */

#define AFEC_CGR_GAIN0_Pos 0

#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos)

#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)))

#define AFEC_CGR_GAIN1_Pos 2

#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos)

#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)))

#define AFEC_CGR_GAIN2_Pos 4

#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos)

#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)))

#define AFEC_CGR_GAIN3_Pos 6

#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos)

#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)))

#define AFEC_CGR_GAIN4_Pos 8

#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos)

#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)))

#define AFEC_CGR_GAIN5_Pos 10

#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos)

#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)))

#define AFEC_CGR_GAIN6_Pos 12

#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos)

#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)))

#define AFEC_CGR_GAIN7_Pos 14

#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos)

#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)))

#define AFEC_CGR_GAIN8_Pos 16

#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos)

#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)))

#define AFEC_CGR_GAIN9_Pos 18

#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos)

#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)))

#define AFEC_CGR_GAIN10_Pos 20

#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos)

#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)))

#define AFEC_CGR_GAIN11_Pos 22

#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos)

#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)))

/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */

#define AFEC_DIFFR_DIFF0 (0x1u << 0)

#define AFEC_DIFFR_DIFF1 (0x1u << 1)

#define AFEC_DIFFR_DIFF2 (0x1u << 2)

#define AFEC_DIFFR_DIFF3 (0x1u << 3)

#define AFEC_DIFFR_DIFF4 (0x1u << 4)

#define AFEC_DIFFR_DIFF5 (0x1u << 5)

#define AFEC_DIFFR_DIFF6 (0x1u << 6)

#define AFEC_DIFFR_DIFF7 (0x1u << 7)

#define AFEC_DIFFR_DIFF8 (0x1u << 8)

#define AFEC_DIFFR_DIFF9 (0x1u << 9)

#define AFEC_DIFFR_DIFF10 (0x1u << 10)

#define AFEC_DIFFR_DIFF11 (0x1u << 11)

/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */

#define AFEC_CSELR_CSEL_Pos 0

#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos)

#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))

/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */

#define AFEC_CDR_DATA_Pos 0

#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos)

/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */

#define AFEC_COCR_AOFF_Pos 0

#define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos)

#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))

/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */

#define AFEC_TEMPMR_RTCT (0x1u << 0)

#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4

#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos)

#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)))

#define   AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4)

#define   AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4)

#define   AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4)

#define   AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4)

/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */

#define AFEC_TEMPCWR_TLOWTHRES_Pos 0

#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos)

#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))

#define AFEC_TEMPCWR_THIGHTHRES_Pos 16

#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos)

#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))

/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */

#define AFEC_ACR_PGA0EN (0x1u << 2)

#define AFEC_ACR_PGA1EN (0x1u << 3)

#define AFEC_ACR_IBCTL_Pos 8

#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos)

#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))

/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */

#define AFEC_SHMR_DUAL0 (0x1u << 0)

#define AFEC_SHMR_DUAL1 (0x1u << 1)

#define AFEC_SHMR_DUAL2 (0x1u << 2)

#define AFEC_SHMR_DUAL3 (0x1u << 3)

#define AFEC_SHMR_DUAL4 (0x1u << 4)

#define AFEC_SHMR_DUAL5 (0x1u << 5)

#define AFEC_SHMR_DUAL6 (0x1u << 6)

#define AFEC_SHMR_DUAL7 (0x1u << 7)

#define AFEC_SHMR_DUAL8 (0x1u << 8)

#define AFEC_SHMR_DUAL9 (0x1u << 9)

#define AFEC_SHMR_DUAL10 (0x1u << 10)

#define AFEC_SHMR_DUAL11 (0x1u << 11)

/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */

#define AFEC_COSR_CSEL (0x1u << 0)

/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */

#define AFEC_CVR_OFFSETCORR_Pos 0

#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos)

#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)))

#define AFEC_CVR_GAINCORR_Pos 16

#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos)

#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)))

/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */

#define AFEC_CECR_ECORR0 (0x1u << 0)

#define AFEC_CECR_ECORR1 (0x1u << 1)

#define AFEC_CECR_ECORR2 (0x1u << 2)

#define AFEC_CECR_ECORR3 (0x1u << 3)

#define AFEC_CECR_ECORR4 (0x1u << 4)

#define AFEC_CECR_ECORR5 (0x1u << 5)

#define AFEC_CECR_ECORR6 (0x1u << 6)

#define AFEC_CECR_ECORR7 (0x1u << 7)

#define AFEC_CECR_ECORR8 (0x1u << 8)

#define AFEC_CECR_ECORR9 (0x1u << 9)

#define AFEC_CECR_ECORR10 (0x1u << 10)

#define AFEC_CECR_ECORR11 (0x1u << 11)

/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */

#define AFEC_WPMR_WPEN (0x1u << 0)

#define AFEC_WPMR_WPKEY_Pos 8

#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos)

#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)))

#define   AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8)

/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */

#define AFEC_WPSR_WPVS (0x1u << 0)

#define AFEC_WPSR_WPVSRC_Pos 8

#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos)


#endif /* _SAMS70_AFEC_COMPONENT_ */

__O
#define __O
Definition core_cm4.h:238

__IO
#define __IO
Definition core_cm4.h:239

__I
#define __I
Definition core_cm4.h:236

Afec
Afec hardware registers.
Definition component_afec.h:41