html/doxygen/same70_2component_2component__supc_8h_source.html

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/*                  Atmel Microcontroller Software Support                      */

/*                       SAM Software Package License                           */

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/* Copyright (c) 2015, Atmel Corporation                                        */

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#ifndef _SAME70_SUPC_COMPONENT_

#define _SAME70_SUPC_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))


typedef struct {

  __O  uint32_t SUPC_CR;

  __IO uint32_t SUPC_SMMR;

  __IO uint32_t SUPC_MR;

  __IO uint32_t SUPC_WUMR;

  __IO uint32_t SUPC_WUIR;

  __I  uint32_t SUPC_SR;

} Supc;


#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */

#define SUPC_CR_VROFF (0x1u << 2)

#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2)

#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2)

#define SUPC_CR_XTALSEL (0x1u << 3)

#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3)

#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3)

#define SUPC_CR_KEY_Pos 24

#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos)

#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))

#define   SUPC_CR_KEY_PASSWD (0xA5u << 24)

/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */

#define SUPC_SMMR_SMTH_Pos 0

#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos)

#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)))

#define SUPC_SMMR_SMSMPL_Pos 8

#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos)

#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos)))

#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8)

#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8)

#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8)

#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8)

#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8)

#define SUPC_SMMR_SMRSTEN (0x1u << 12)

#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12)

#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12)

#define SUPC_SMMR_SMIEN (0x1u << 13)

#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13)

#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13)

/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */

#define SUPC_MR_BODRSTEN (0x1u << 12)

#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12)

#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12)

#define SUPC_MR_BODDIS (0x1u << 13)

#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13)

#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13)

#define SUPC_MR_ONREG (0x1u << 14)

#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14)

#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14)

#define SUPC_MR_BKUPRETON (0x1u << 17)

#define SUPC_MR_OSCBYPASS (0x1u << 20)

#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20)

#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20)

#define SUPC_MR_KEY_Pos 24

#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos)

#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))

#define   SUPC_MR_KEY_PASSWD (0xA5u << 24)

/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */

#define SUPC_WUMR_SMEN (0x1u << 1)

#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1)

#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1)

#define SUPC_WUMR_RTTEN (0x1u << 2)

#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2)

#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2)

#define SUPC_WUMR_RTCEN (0x1u << 3)

#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3)

#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3)

#define SUPC_WUMR_LPDBCEN0 (0x1u << 5)

#define   SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5)

#define   SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5)

#define SUPC_WUMR_LPDBCEN1 (0x1u << 6)

#define   SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6)

#define   SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6)

#define SUPC_WUMR_LPDBCCLR (0x1u << 7)

#define   SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7)

#define   SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7)

#define SUPC_WUMR_WKUPDBC_Pos 12

#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos)

#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos)))

#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12)

#define   SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12)

#define   SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12)

#define   SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12)

#define   SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12)

#define   SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12)

#define SUPC_WUMR_LPDBC_Pos 16

#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos)

#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos)))

#define   SUPC_WUMR_LPDBC_DISABLE (0x0u << 16)

#define   SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16)

#define   SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16)

#define   SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16)

#define   SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16)

#define   SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16)

#define   SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16)

#define   SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16)

/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */

#define SUPC_WUIR_WKUPEN0 (0x1u << 0)

#define   SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0)

#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0)

#define SUPC_WUIR_WKUPEN1 (0x1u << 1)

#define   SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1)

#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1)

#define SUPC_WUIR_WKUPEN2 (0x1u << 2)

#define   SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2)

#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2)

#define SUPC_WUIR_WKUPEN3 (0x1u << 3)

#define   SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3)

#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3)

#define SUPC_WUIR_WKUPEN4 (0x1u << 4)

#define   SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4)

#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4)

#define SUPC_WUIR_WKUPEN5 (0x1u << 5)

#define   SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5)

#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5)

#define SUPC_WUIR_WKUPEN6 (0x1u << 6)

#define   SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6)

#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6)

#define SUPC_WUIR_WKUPEN7 (0x1u << 7)

#define   SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7)

#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7)

#define SUPC_WUIR_WKUPEN8 (0x1u << 8)

#define   SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8)

#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8)

#define SUPC_WUIR_WKUPEN9 (0x1u << 9)

#define   SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9)

#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9)

#define SUPC_WUIR_WKUPEN10 (0x1u << 10)

#define   SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10)

#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10)

#define SUPC_WUIR_WKUPEN11 (0x1u << 11)

#define   SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11)

#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11)

#define SUPC_WUIR_WKUPEN12 (0x1u << 12)

#define   SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12)

#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12)

#define SUPC_WUIR_WKUPEN13 (0x1u << 13)

#define   SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13)

#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13)

#define SUPC_WUIR_WKUPT0 (0x1u << 16)

#define   SUPC_WUIR_WKUPT0_LOW (0x0u << 16)

#define   SUPC_WUIR_WKUPT0_HIGH (0x1u << 16)

#define SUPC_WUIR_WKUPT1 (0x1u << 17)

#define   SUPC_WUIR_WKUPT1_LOW (0x0u << 17)

#define   SUPC_WUIR_WKUPT1_HIGH (0x1u << 17)

#define SUPC_WUIR_WKUPT2 (0x1u << 18)

#define   SUPC_WUIR_WKUPT2_LOW (0x0u << 18)

#define   SUPC_WUIR_WKUPT2_HIGH (0x1u << 18)

#define SUPC_WUIR_WKUPT3 (0x1u << 19)

#define   SUPC_WUIR_WKUPT3_LOW (0x0u << 19)

#define   SUPC_WUIR_WKUPT3_HIGH (0x1u << 19)

#define SUPC_WUIR_WKUPT4 (0x1u << 20)

#define   SUPC_WUIR_WKUPT4_LOW (0x0u << 20)

#define   SUPC_WUIR_WKUPT4_HIGH (0x1u << 20)

#define SUPC_WUIR_WKUPT5 (0x1u << 21)

#define   SUPC_WUIR_WKUPT5_LOW (0x0u << 21)

#define   SUPC_WUIR_WKUPT5_HIGH (0x1u << 21)

#define SUPC_WUIR_WKUPT6 (0x1u << 22)

#define   SUPC_WUIR_WKUPT6_LOW (0x0u << 22)

#define   SUPC_WUIR_WKUPT6_HIGH (0x1u << 22)

#define SUPC_WUIR_WKUPT7 (0x1u << 23)

#define   SUPC_WUIR_WKUPT7_LOW (0x0u << 23)

#define   SUPC_WUIR_WKUPT7_HIGH (0x1u << 23)

#define SUPC_WUIR_WKUPT8 (0x1u << 24)

#define   SUPC_WUIR_WKUPT8_LOW (0x0u << 24)

#define   SUPC_WUIR_WKUPT8_HIGH (0x1u << 24)

#define SUPC_WUIR_WKUPT9 (0x1u << 25)

#define   SUPC_WUIR_WKUPT9_LOW (0x0u << 25)

#define   SUPC_WUIR_WKUPT9_HIGH (0x1u << 25)

#define SUPC_WUIR_WKUPT10 (0x1u << 26)

#define   SUPC_WUIR_WKUPT10_LOW (0x0u << 26)

#define   SUPC_WUIR_WKUPT10_HIGH (0x1u << 26)

#define SUPC_WUIR_WKUPT11 (0x1u << 27)

#define   SUPC_WUIR_WKUPT11_LOW (0x0u << 27)

#define   SUPC_WUIR_WKUPT11_HIGH (0x1u << 27)

#define SUPC_WUIR_WKUPT12 (0x1u << 28)

#define   SUPC_WUIR_WKUPT12_LOW (0x0u << 28)

#define   SUPC_WUIR_WKUPT12_HIGH (0x1u << 28)

#define SUPC_WUIR_WKUPT13 (0x1u << 29)

#define   SUPC_WUIR_WKUPT13_LOW (0x0u << 29)

#define   SUPC_WUIR_WKUPT13_HIGH (0x1u << 29)

/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */

#define SUPC_SR_WKUPS (0x1u << 1)

#define   SUPC_SR_WKUPS_NO (0x0u << 1)

#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1)

#define SUPC_SR_SMWS (0x1u << 2)

#define   SUPC_SR_SMWS_NO (0x0u << 2)

#define   SUPC_SR_SMWS_PRESENT (0x1u << 2)

#define SUPC_SR_BODRSTS (0x1u << 3)

#define   SUPC_SR_BODRSTS_NO (0x0u << 3)

#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3)

#define SUPC_SR_SMRSTS (0x1u << 4)

#define   SUPC_SR_SMRSTS_NO (0x0u << 4)

#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4)

#define SUPC_SR_SMS (0x1u << 5)

#define   SUPC_SR_SMS_NO (0x0u << 5)

#define   SUPC_SR_SMS_PRESENT (0x1u << 5)

#define SUPC_SR_SMOS (0x1u << 6)

#define   SUPC_SR_SMOS_HIGH (0x0u << 6)

#define   SUPC_SR_SMOS_LOW (0x1u << 6)

#define SUPC_SR_OSCSEL (0x1u << 7)

#define   SUPC_SR_OSCSEL_RC (0x0u << 7)

#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7)

#define SUPC_SR_LPDBCS0 (0x1u << 13)

#define   SUPC_SR_LPDBCS0_NO (0x0u << 13)

#define   SUPC_SR_LPDBCS0_PRESENT (0x1u << 13)

#define SUPC_SR_LPDBCS1 (0x1u << 14)

#define   SUPC_SR_LPDBCS1_NO (0x0u << 14)

#define   SUPC_SR_LPDBCS1_PRESENT (0x1u << 14)

#define SUPC_SR_WKUPIS0 (0x1u << 16)

#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16)

#define   SUPC_SR_WKUPIS0_EN (0x1u << 16)

#define SUPC_SR_WKUPIS1 (0x1u << 17)

#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17)

#define   SUPC_SR_WKUPIS1_EN (0x1u << 17)

#define SUPC_SR_WKUPIS2 (0x1u << 18)

#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18)

#define   SUPC_SR_WKUPIS2_EN (0x1u << 18)

#define SUPC_SR_WKUPIS3 (0x1u << 19)

#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19)

#define   SUPC_SR_WKUPIS3_EN (0x1u << 19)

#define SUPC_SR_WKUPIS4 (0x1u << 20)

#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20)

#define   SUPC_SR_WKUPIS4_EN (0x1u << 20)

#define SUPC_SR_WKUPIS5 (0x1u << 21)

#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21)

#define   SUPC_SR_WKUPIS5_EN (0x1u << 21)

#define SUPC_SR_WKUPIS6 (0x1u << 22)

#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22)

#define   SUPC_SR_WKUPIS6_EN (0x1u << 22)

#define SUPC_SR_WKUPIS7 (0x1u << 23)

#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23)

#define   SUPC_SR_WKUPIS7_EN (0x1u << 23)

#define SUPC_SR_WKUPIS8 (0x1u << 24)

#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24)

#define   SUPC_SR_WKUPIS8_EN (0x1u << 24)

#define SUPC_SR_WKUPIS9 (0x1u << 25)

#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25)

#define   SUPC_SR_WKUPIS9_EN (0x1u << 25)

#define SUPC_SR_WKUPIS10 (0x1u << 26)

#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26)

#define   SUPC_SR_WKUPIS10_EN (0x1u << 26)

#define SUPC_SR_WKUPIS11 (0x1u << 27)

#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27)

#define   SUPC_SR_WKUPIS11_EN (0x1u << 27)

#define SUPC_SR_WKUPIS12 (0x1u << 28)

#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28)

#define   SUPC_SR_WKUPIS12_EN (0x1u << 28)

#define SUPC_SR_WKUPIS13 (0x1u << 29)

#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29)

#define   SUPC_SR_WKUPIS13_EN (0x1u << 29)


#endif /* _SAME70_SUPC_COMPONENT_ */

__O
#define __O
Definition core_cm4.h:238

__IO
#define __IO
Definition core_cm4.h:239

__I
#define __I
Definition core_cm4.h:236

Supc
Supc hardware registers.
Definition component_supc.h:41

Supc::SUPC_CR
__O uint32_t SUPC_CR
(Supc Offset: 0x00) Supply Controller Control Register
Definition component_supc.h:42

Supc::SUPC_SMMR
__IO uint32_t SUPC_SMMR
(Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register
Definition component_supc.h:43

Supc::SUPC_MR
__IO uint32_t SUPC_MR
(Supc Offset: 0x08) Supply Controller Mode Register
Definition component_supc.h:44

Supc::SUPC_WUIR
__IO uint32_t SUPC_WUIR
(Supc Offset: 0x10) Supply Controller Wake-up Inputs Register
Definition component_supc.h:46

Supc::SUPC_SR
__I uint32_t SUPC_SR
(Supc Offset: 0x14) Supply Controller Status Register
Definition component_supc.h:47

Supc::SUPC_WUMR
__IO uint32_t SUPC_WUMR
(Supc Offset: 0x0C) Supply Controller Wake-up Mode Register
Definition component_supc.h:45